2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #ifndef OPENOCD_TARGET_ARM_H
26 #define OPENOCD_TARGET_ARM_H
28 #include <helper/command.h>
34 * Holds the interface to ARM cores.
36 * At this writing, only "classic ARM" cores built on the ARMv4 register
37 * and mode model are supported. The Thumb2-only microcontroller profile
38 * support has not yet been integrated, affecting Cortex-M parts.
42 * Represent state of an ARM core.
44 * Most numbers match the five low bits of the *PSR registers on
45 * "classic ARM" processors, which build on the ARMv4 processor
46 * modes and register set.
48 * ARM_MODE_ANY is a magic value, often used as a wildcard.
50 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
51 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
62 ARM_MODE_1176_MON
= 28,
66 ARM_MODE_USER_THREAD
= 1,
72 const char *arm_mode_name(unsigned psr_mode
);
73 bool is_arm_mode(unsigned psr_mode
);
75 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
83 #define ARM_COMMON_MAGIC 0x0A450A45
86 * Represents a generic ARM core, with standard application registers.
88 * There are sixteen application registers (including PC, SP, LR) and a PSR.
89 * Cortex-M series cores do not support as many core states or shadowed
90 * registers as traditional ARM cores, and only support Thumb2 instructions.
94 struct reg_cache
*core_cache
;
96 /** Handle to the PC; valid in all core modes. */
99 /** Handle to the CPSR/xPSR; valid in all core modes. */
102 /** Handle to the SPSR; valid only in core modes with an SPSR. */
105 /** Support for arm_reg_current() */
109 * Indicates what registers are in the ARM state core register set.
110 * ARM_MODE_ANY indicates the standard set of 37 registers,
111 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
112 * more registers are shadowed, for "Secure Monitor" mode.
113 * ARM_MODE_THREAD indicates a microcontroller profile core,
114 * which only shadows SP.
116 enum arm_mode core_type
;
118 /** Record the current core mode: SVC, USR, or some other mode. */
119 enum arm_mode core_mode
;
121 /** Record the current core state: ARM, Thumb, or otherwise. */
122 enum arm_state core_state
;
124 /** Flag reporting unavailability of the BKPT instruction. */
127 /** Flag reporting armv6m based core. */
130 /** Flag reporting whether semihosting is active. */
133 /** Flag reporting whether semihosting fileio is active. */
134 bool is_semihosting_fileio
;
136 /** Flag reporting whether semihosting fileio operation is active. */
137 bool semihosting_hit_fileio
;
139 /** Current semihosting operation. */
142 /** Current semihosting result. */
143 int semihosting_result
;
145 /** Value to be returned by semihosting SYS_ERRNO request. */
146 int semihosting_errno
;
148 int (*setup_semihosting
)(struct target
*target
, int enable
);
150 /** Backpointer to the target. */
151 struct target
*target
;
153 /** Handle for the debug module, if one is present. */
156 /** Handle for the Embedded Trace Module, if one is present. */
157 struct etm_context
*etm
;
159 /* FIXME all these methods should take "struct arm *" not target */
161 /** Retrieve all core registers, for display. */
162 int (*full_context
)(struct target
*target
);
164 /** Retrieve a single core register. */
165 int (*read_core_reg
)(struct target
*target
, struct reg
*reg
,
166 int num
, enum arm_mode mode
);
167 int (*write_core_reg
)(struct target
*target
, struct reg
*reg
,
168 int num
, enum arm_mode mode
, uint8_t *value
);
170 /** Read coprocessor register. */
171 int (*mrc
)(struct target
*target
, int cpnum
,
172 uint32_t op1
, uint32_t op2
,
173 uint32_t CRn
, uint32_t CRm
,
176 /** Write coprocessor register. */
177 int (*mcr
)(struct target
*target
, int cpnum
,
178 uint32_t op1
, uint32_t op2
,
179 uint32_t CRn
, uint32_t CRm
,
184 /** For targets conforming to ARM Debug Interface v5,
185 * this handle references the Debug Access Port (DAP)
186 * used to make requests to the target.
188 struct adiv5_dap
*dap
;
191 /** Convert target handle to generic ARM target state handle. */
192 static inline struct arm
*target_to_arm(struct target
*target
)
194 assert(target
!= NULL
);
195 return target
->arch_info
;
198 static inline bool is_arm(struct arm
*arm
)
201 return arm
->common_magic
== ARM_COMMON_MAGIC
;
204 struct arm_algorithm
{
207 enum arm_mode core_mode
;
208 enum arm_state core_state
;
214 struct target
*target
;
219 struct reg_cache
*arm_build_reg_cache(struct target
*target
, struct arm
*arm
);
221 extern const struct command_registration arm_command_handlers
[];
223 int arm_arch_state(struct target
*target
);
224 int arm_get_gdb_reg_list(struct target
*target
,
225 struct reg
**reg_list
[], int *reg_list_size
,
226 enum target_register_class reg_class
);
228 int arm_init_arch_info(struct target
*target
, struct arm
*arm
);
230 /* REVISIT rename this once it's usable by ARMv7-M */
231 int armv4_5_run_algorithm(struct target
*target
,
232 int num_mem_params
, struct mem_param
*mem_params
,
233 int num_reg_params
, struct reg_param
*reg_params
,
234 uint32_t entry_point
, uint32_t exit_point
,
235 int timeout_ms
, void *arch_info
);
236 int armv4_5_run_algorithm_inner(struct target
*target
,
237 int num_mem_params
, struct mem_param
*mem_params
,
238 int num_reg_params
, struct reg_param
*reg_params
,
239 uint32_t entry_point
, uint32_t exit_point
,
240 int timeout_ms
, void *arch_info
,
241 int (*run_it
)(struct target
*target
, uint32_t exit_point
,
242 int timeout_ms
, void *arch_info
));
244 int arm_checksum_memory(struct target
*target
,
245 uint32_t address
, uint32_t count
, uint32_t *checksum
);
246 int arm_blank_check_memory(struct target
*target
,
247 uint32_t address
, uint32_t count
, uint32_t *blank
, uint8_t erased_value
);
249 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
250 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
);
252 extern struct reg arm_gdb_dummy_fp_reg
;
253 extern struct reg arm_gdb_dummy_fps_reg
;
255 #endif /* OPENOCD_TARGET_ARM_H */