1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * Copyright (C) 2010 Øyvind Harboe *
15 * oyvind.harboe@zylin.com *
17 * Copyright (C) ST-Ericsson SA 2011 *
18 * michel.jaouen@stericsson.com : smp minimum support *
20 * Copyright (C) Broadcom 2012 *
21 * ehunter@broadcom.com : Cortex-R4 support *
23 * Copyright (C) 2013 Kamal Dasu *
24 * kdasu.kdev@gmail.com *
26 * This program is free software; you can redistribute it and/or modify *
27 * it under the terms of the GNU General Public License as published by *
28 * the Free Software Foundation; either version 2 of the License, or *
29 * (at your option) any later version. *
31 * This program is distributed in the hope that it will be useful, *
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
34 * GNU General Public License for more details. *
36 * You should have received a copy of the GNU General Public License *
37 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
39 * Cortex-A8(tm) TRM, ARM DDI 0344H *
40 * Cortex-A9(tm) TRM, ARM DDI 0407F *
41 * Cortex-A4(tm) TRM, ARM DDI 0363E *
42 * Cortex-A15(tm)TRM, ARM DDI 0438C *
44 ***************************************************************************/
50 #include "breakpoints.h"
53 #include "target_request.h"
54 #include "target_type.h"
55 #include "arm_opcodes.h"
56 #include "arm_semihosting.h"
58 #include <helper/time_support.h>
60 static int cortex_a_poll(struct target
*target
);
61 static int cortex_a_debug_entry(struct target
*target
);
62 static int cortex_a_restore_context(struct target
*target
, bool bpwp
);
63 static int cortex_a_set_breakpoint(struct target
*target
,
64 struct breakpoint
*breakpoint
, uint8_t matchmode
);
65 static int cortex_a_set_context_breakpoint(struct target
*target
,
66 struct breakpoint
*breakpoint
, uint8_t matchmode
);
67 static int cortex_a_set_hybrid_breakpoint(struct target
*target
,
68 struct breakpoint
*breakpoint
);
69 static int cortex_a_unset_breakpoint(struct target
*target
,
70 struct breakpoint
*breakpoint
);
71 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
72 uint32_t *value
, int regnum
);
73 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
74 uint32_t value
, int regnum
);
75 static int cortex_a_mmu(struct target
*target
, int *enabled
);
76 static int cortex_a_mmu_modify(struct target
*target
, int enable
);
77 static int cortex_a_virt2phys(struct target
*target
,
78 target_addr_t virt
, target_addr_t
*phys
);
79 static int cortex_a_read_cpu_memory(struct target
*target
,
80 uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
83 /* restore cp15_control_reg at resume */
84 static int cortex_a_restore_cp15_control_reg(struct target
*target
)
86 int retval
= ERROR_OK
;
87 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
88 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
90 if (cortex_a
->cp15_control_reg
!= cortex_a
->cp15_control_reg_curr
) {
91 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
92 /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); */
93 retval
= armv7a
->arm
.mcr(target
, 15,
96 cortex_a
->cp15_control_reg
);
102 * Set up ARM core for memory access.
103 * If !phys_access, switch to SVC mode and make sure MMU is on
104 * If phys_access, switch off mmu
106 static int cortex_a_prep_memaccess(struct target
*target
, int phys_access
)
108 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
109 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
112 if (phys_access
== 0) {
113 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
114 cortex_a_mmu(target
, &mmu_enabled
);
116 cortex_a_mmu_modify(target
, 1);
117 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
118 /* overwrite DACR to all-manager */
119 armv7a
->arm
.mcr(target
, 15,
124 cortex_a_mmu(target
, &mmu_enabled
);
126 cortex_a_mmu_modify(target
, 0);
132 * Restore ARM core after memory access.
133 * If !phys_access, switch to previous mode
134 * If phys_access, restore MMU setting
136 static int cortex_a_post_memaccess(struct target
*target
, int phys_access
)
138 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
139 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
141 if (phys_access
== 0) {
142 if (cortex_a
->dacrfixup_mode
== CORTEX_A_DACRFIXUP_ON
) {
144 armv7a
->arm
.mcr(target
, 15,
146 cortex_a
->cp15_dacr_reg
);
148 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
151 cortex_a_mmu(target
, &mmu_enabled
);
153 cortex_a_mmu_modify(target
, 1);
159 /* modify cp15_control_reg in order to enable or disable mmu for :
160 * - virt2phys address conversion
161 * - read or write memory in phys or virt address */
162 static int cortex_a_mmu_modify(struct target
*target
, int enable
)
164 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
165 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
166 int retval
= ERROR_OK
;
170 /* if mmu enabled at target stop and mmu not enable */
171 if (!(cortex_a
->cp15_control_reg
& 0x1U
)) {
172 LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
175 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0) {
176 cortex_a
->cp15_control_reg_curr
|= 0x1U
;
180 if ((cortex_a
->cp15_control_reg_curr
& 0x1U
) == 0x1U
) {
181 cortex_a
->cp15_control_reg_curr
&= ~0x1U
;
187 LOG_DEBUG("%s, writing cp15 ctrl: %" PRIx32
,
188 enable
? "enable mmu" : "disable mmu",
189 cortex_a
->cp15_control_reg_curr
);
191 retval
= armv7a
->arm
.mcr(target
, 15,
194 cortex_a
->cp15_control_reg_curr
);
200 * Cortex-A Basic debug access, very low level assumes state is saved
202 static int cortex_a_init_debug_access(struct target
*target
)
204 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
207 /* lock memory-mapped access to debug registers to prevent
208 * software interference */
209 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
210 armv7a
->debug_base
+ CPUDBG_LOCKACCESS
, 0);
211 if (retval
!= ERROR_OK
)
214 /* Disable cacheline fills and force cache write-through in debug state */
215 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
216 armv7a
->debug_base
+ CPUDBG_DSCCR
, 0);
217 if (retval
!= ERROR_OK
)
220 /* Disable TLB lookup and refill/eviction in debug state */
221 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
222 armv7a
->debug_base
+ CPUDBG_DSMCR
, 0);
223 if (retval
!= ERROR_OK
)
226 /* Enabling of instruction execution in debug mode is done in debug_entry code */
228 /* Resync breakpoint registers */
230 /* Since this is likely called from init or reset, update target state information*/
231 return cortex_a_poll(target
);
234 static int cortex_a_wait_instrcmpl(struct target
*target
, uint32_t *dscr
, bool force
)
236 /* Waits until InstrCmpl_l becomes 1, indicating instruction is done.
237 * Writes final value of DSCR into *dscr. Pass force to force always
238 * reading DSCR at least once. */
239 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
240 int64_t then
= timeval_ms();
241 while ((*dscr
& DSCR_INSTR_COMP
) == 0 || force
) {
243 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
244 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
245 if (retval
!= ERROR_OK
) {
246 LOG_ERROR("Could not read DSCR register");
249 if (timeval_ms() > then
+ 1000) {
250 LOG_ERROR("Timeout waiting for InstrCompl=1");
257 /* To reduce needless round-trips, pass in a pointer to the current
258 * DSCR value. Initialize it to zero if you just need to know the
259 * value on return from this function; or DSCR_INSTR_COMP if you
260 * happen to know that no instruction is pending.
262 static int cortex_a_exec_opcode(struct target
*target
,
263 uint32_t opcode
, uint32_t *dscr_p
)
267 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
269 dscr
= dscr_p
? *dscr_p
: 0;
271 LOG_DEBUG("exec opcode 0x%08" PRIx32
, opcode
);
273 /* Wait for InstrCompl bit to be set */
274 retval
= cortex_a_wait_instrcmpl(target
, dscr_p
, false);
275 if (retval
!= ERROR_OK
)
278 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
279 armv7a
->debug_base
+ CPUDBG_ITR
, opcode
);
280 if (retval
!= ERROR_OK
)
283 int64_t then
= timeval_ms();
285 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
286 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
287 if (retval
!= ERROR_OK
) {
288 LOG_ERROR("Could not read DSCR register");
291 if (timeval_ms() > then
+ 1000) {
292 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
295 } while ((dscr
& DSCR_INSTR_COMP
) == 0); /* Wait for InstrCompl bit to be set */
303 /**************************************************************************
304 Read core register with very few exec_opcode, fast but needs work_area.
305 This can cause problems with MMU active.
306 **************************************************************************/
307 static int cortex_a_read_regs_through_mem(struct target
*target
, uint32_t address
,
310 int retval
= ERROR_OK
;
311 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
313 retval
= cortex_a_dap_read_coreregister_u32(target
, regfile
, 0);
314 if (retval
!= ERROR_OK
)
316 retval
= cortex_a_dap_write_coreregister_u32(target
, address
, 0);
317 if (retval
!= ERROR_OK
)
319 retval
= cortex_a_exec_opcode(target
, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL
);
320 if (retval
!= ERROR_OK
)
323 retval
= mem_ap_read_buf(armv7a
->memory_ap
,
324 (uint8_t *)(®file
[1]), 4, 15, address
);
329 static int cortex_a_dap_read_coreregister_u32(struct target
*target
,
330 uint32_t *value
, int regnum
)
332 int retval
= ERROR_OK
;
333 uint8_t reg
= regnum
&0xFF;
335 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
341 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
342 retval
= cortex_a_exec_opcode(target
,
343 ARMV4_5_MCR(14, 0, reg
, 0, 5, 0),
345 if (retval
!= ERROR_OK
)
347 } else if (reg
== 15) {
348 /* "MOV r0, r15"; then move r0 to DCCTX */
349 retval
= cortex_a_exec_opcode(target
, 0xE1A0000F, &dscr
);
350 if (retval
!= ERROR_OK
)
352 retval
= cortex_a_exec_opcode(target
,
353 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
355 if (retval
!= ERROR_OK
)
358 /* "MRS r0, CPSR" or "MRS r0, SPSR"
359 * then move r0 to DCCTX
361 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRS(0, reg
& 1), &dscr
);
362 if (retval
!= ERROR_OK
)
364 retval
= cortex_a_exec_opcode(target
,
365 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
367 if (retval
!= ERROR_OK
)
371 /* Wait for DTRRXfull then read DTRRTX */
372 int64_t then
= timeval_ms();
373 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
374 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
375 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
376 if (retval
!= ERROR_OK
)
378 if (timeval_ms() > then
+ 1000) {
379 LOG_ERROR("Timeout waiting for cortex_a_exec_opcode");
384 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
385 armv7a
->debug_base
+ CPUDBG_DTRTX
, value
);
386 LOG_DEBUG("read DCC 0x%08" PRIx32
, *value
);
391 static int cortex_a_dap_write_coreregister_u32(struct target
*target
,
392 uint32_t value
, int regnum
)
394 int retval
= ERROR_OK
;
395 uint8_t Rd
= regnum
&0xFF;
397 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
399 LOG_DEBUG("register %i, value 0x%08" PRIx32
, regnum
, value
);
401 /* Check that DCCRX is not full */
402 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
403 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
404 if (retval
!= ERROR_OK
)
406 if (dscr
& DSCR_DTR_RX_FULL
) {
407 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
408 /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
409 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
411 if (retval
!= ERROR_OK
)
418 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
419 LOG_DEBUG("write DCC 0x%08" PRIx32
, value
);
420 retval
= mem_ap_write_u32(armv7a
->debug_ap
,
421 armv7a
->debug_base
+ CPUDBG_DTRRX
, value
);
422 if (retval
!= ERROR_OK
)
426 /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
427 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, Rd
, 0, 5, 0),
430 if (retval
!= ERROR_OK
)
432 } else if (Rd
== 15) {
433 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
436 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
438 if (retval
!= ERROR_OK
)
440 retval
= cortex_a_exec_opcode(target
, 0xE1A0F000, &dscr
);
441 if (retval
!= ERROR_OK
)
444 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
445 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
447 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
449 if (retval
!= ERROR_OK
)
451 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MSR_GP(0, 0xF, Rd
& 1),
453 if (retval
!= ERROR_OK
)
456 /* "Prefetch flush" after modifying execution status in CPSR */
458 retval
= cortex_a_exec_opcode(target
,
459 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
461 if (retval
!= ERROR_OK
)
469 /* Write to memory mapped registers directly with no cache or mmu handling */
470 static int cortex_a_dap_write_memap_register_u32(struct target
*target
,
475 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
477 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
, address
, value
);
483 * Cortex-A implementation of Debug Programmer's Model
485 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
486 * so there's no need to poll for it before executing an instruction.
488 * NOTE that in several of these cases the "stall" mode might be useful.
489 * It'd let us queue a few operations together... prepare/finish might
490 * be the places to enable/disable that mode.
493 static inline struct cortex_a_common
*dpm_to_a(struct arm_dpm
*dpm
)
495 return container_of(dpm
, struct cortex_a_common
, armv7a_common
.dpm
);
498 static int cortex_a_write_dcc(struct cortex_a_common
*a
, uint32_t data
)
500 LOG_DEBUG("write DCC 0x%08" PRIx32
, data
);
501 return mem_ap_write_u32(a
->armv7a_common
.debug_ap
,
502 a
->armv7a_common
.debug_base
+ CPUDBG_DTRRX
, data
);
505 static int cortex_a_read_dcc(struct cortex_a_common
*a
, uint32_t *data
,
508 uint32_t dscr
= DSCR_INSTR_COMP
;
514 /* Wait for DTRRXfull */
515 int64_t then
= timeval_ms();
516 while ((dscr
& DSCR_DTR_TX_FULL
) == 0) {
517 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
518 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
520 if (retval
!= ERROR_OK
)
522 if (timeval_ms() > then
+ 1000) {
523 LOG_ERROR("Timeout waiting for read dcc");
528 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
529 a
->armv7a_common
.debug_base
+ CPUDBG_DTRTX
, data
);
530 if (retval
!= ERROR_OK
)
532 /* LOG_DEBUG("read DCC 0x%08" PRIx32, *data); */
540 static int cortex_a_dpm_prepare(struct arm_dpm
*dpm
)
542 struct cortex_a_common
*a
= dpm_to_a(dpm
);
546 /* set up invariant: INSTR_COMP is set after ever DPM operation */
547 int64_t then
= timeval_ms();
549 retval
= mem_ap_read_atomic_u32(a
->armv7a_common
.debug_ap
,
550 a
->armv7a_common
.debug_base
+ CPUDBG_DSCR
,
552 if (retval
!= ERROR_OK
)
554 if ((dscr
& DSCR_INSTR_COMP
) != 0)
556 if (timeval_ms() > then
+ 1000) {
557 LOG_ERROR("Timeout waiting for dpm prepare");
562 /* this "should never happen" ... */
563 if (dscr
& DSCR_DTR_RX_FULL
) {
564 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32
, dscr
);
566 retval
= cortex_a_exec_opcode(
567 a
->armv7a_common
.arm
.target
,
568 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
570 if (retval
!= ERROR_OK
)
577 static int cortex_a_dpm_finish(struct arm_dpm
*dpm
)
579 /* REVISIT what could be done here? */
583 static int cortex_a_instr_write_data_dcc(struct arm_dpm
*dpm
,
584 uint32_t opcode
, uint32_t data
)
586 struct cortex_a_common
*a
= dpm_to_a(dpm
);
588 uint32_t dscr
= DSCR_INSTR_COMP
;
590 retval
= cortex_a_write_dcc(a
, data
);
591 if (retval
!= ERROR_OK
)
594 return cortex_a_exec_opcode(
595 a
->armv7a_common
.arm
.target
,
600 static int cortex_a_instr_write_data_r0(struct arm_dpm
*dpm
,
601 uint32_t opcode
, uint32_t data
)
603 struct cortex_a_common
*a
= dpm_to_a(dpm
);
604 uint32_t dscr
= DSCR_INSTR_COMP
;
607 retval
= cortex_a_write_dcc(a
, data
);
608 if (retval
!= ERROR_OK
)
611 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
612 retval
= cortex_a_exec_opcode(
613 a
->armv7a_common
.arm
.target
,
614 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
616 if (retval
!= ERROR_OK
)
619 /* then the opcode, taking data from R0 */
620 retval
= cortex_a_exec_opcode(
621 a
->armv7a_common
.arm
.target
,
628 static int cortex_a_instr_cpsr_sync(struct arm_dpm
*dpm
)
630 struct target
*target
= dpm
->arm
->target
;
631 uint32_t dscr
= DSCR_INSTR_COMP
;
633 /* "Prefetch flush" after modifying execution status in CPSR */
634 return cortex_a_exec_opcode(target
,
635 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
639 static int cortex_a_instr_read_data_dcc(struct arm_dpm
*dpm
,
640 uint32_t opcode
, uint32_t *data
)
642 struct cortex_a_common
*a
= dpm_to_a(dpm
);
644 uint32_t dscr
= DSCR_INSTR_COMP
;
646 /* the opcode, writing data to DCC */
647 retval
= cortex_a_exec_opcode(
648 a
->armv7a_common
.arm
.target
,
651 if (retval
!= ERROR_OK
)
654 return cortex_a_read_dcc(a
, data
, &dscr
);
658 static int cortex_a_instr_read_data_r0(struct arm_dpm
*dpm
,
659 uint32_t opcode
, uint32_t *data
)
661 struct cortex_a_common
*a
= dpm_to_a(dpm
);
662 uint32_t dscr
= DSCR_INSTR_COMP
;
665 /* the opcode, writing data to R0 */
666 retval
= cortex_a_exec_opcode(
667 a
->armv7a_common
.arm
.target
,
670 if (retval
!= ERROR_OK
)
673 /* write R0 to DCC */
674 retval
= cortex_a_exec_opcode(
675 a
->armv7a_common
.arm
.target
,
676 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
678 if (retval
!= ERROR_OK
)
681 return cortex_a_read_dcc(a
, data
, &dscr
);
684 static int cortex_a_bpwp_enable(struct arm_dpm
*dpm
, unsigned index_t
,
685 uint32_t addr
, uint32_t control
)
687 struct cortex_a_common
*a
= dpm_to_a(dpm
);
688 uint32_t vr
= a
->armv7a_common
.debug_base
;
689 uint32_t cr
= a
->armv7a_common
.debug_base
;
693 case 0 ... 15: /* breakpoints */
694 vr
+= CPUDBG_BVR_BASE
;
695 cr
+= CPUDBG_BCR_BASE
;
697 case 16 ... 31: /* watchpoints */
698 vr
+= CPUDBG_WVR_BASE
;
699 cr
+= CPUDBG_WCR_BASE
;
708 LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
709 (unsigned) vr
, (unsigned) cr
);
711 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
713 if (retval
!= ERROR_OK
)
715 retval
= cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
,
720 static int cortex_a_bpwp_disable(struct arm_dpm
*dpm
, unsigned index_t
)
722 struct cortex_a_common
*a
= dpm_to_a(dpm
);
727 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_BCR_BASE
;
730 cr
= a
->armv7a_common
.debug_base
+ CPUDBG_WCR_BASE
;
738 LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr
);
740 /* clear control register */
741 return cortex_a_dap_write_memap_register_u32(dpm
->arm
->target
, cr
, 0);
744 static int cortex_a_dpm_setup(struct cortex_a_common
*a
, uint32_t didr
)
746 struct arm_dpm
*dpm
= &a
->armv7a_common
.dpm
;
749 dpm
->arm
= &a
->armv7a_common
.arm
;
752 dpm
->prepare
= cortex_a_dpm_prepare
;
753 dpm
->finish
= cortex_a_dpm_finish
;
755 dpm
->instr_write_data_dcc
= cortex_a_instr_write_data_dcc
;
756 dpm
->instr_write_data_r0
= cortex_a_instr_write_data_r0
;
757 dpm
->instr_cpsr_sync
= cortex_a_instr_cpsr_sync
;
759 dpm
->instr_read_data_dcc
= cortex_a_instr_read_data_dcc
;
760 dpm
->instr_read_data_r0
= cortex_a_instr_read_data_r0
;
762 dpm
->bpwp_enable
= cortex_a_bpwp_enable
;
763 dpm
->bpwp_disable
= cortex_a_bpwp_disable
;
765 retval
= arm_dpm_setup(dpm
);
766 if (retval
== ERROR_OK
)
767 retval
= arm_dpm_initialize(dpm
);
771 static struct target
*get_cortex_a(struct target
*target
, int32_t coreid
)
773 struct target_list
*head
;
777 while (head
!= (struct target_list
*)NULL
) {
779 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
785 static int cortex_a_halt(struct target
*target
);
787 static int cortex_a_halt_smp(struct target
*target
)
790 struct target_list
*head
;
793 while (head
!= (struct target_list
*)NULL
) {
795 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
)
796 && target_was_examined(curr
))
797 retval
+= cortex_a_halt(curr
);
803 static int update_halt_gdb(struct target
*target
)
806 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
807 target
->gdb_service
->target
= target
;
808 target
->gdb_service
->core
[0] = target
->coreid
;
809 retval
+= cortex_a_halt_smp(target
);
815 * Cortex-A Run control
818 static int cortex_a_poll(struct target
*target
)
820 int retval
= ERROR_OK
;
822 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
823 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
824 enum target_state prev_target_state
= target
->state
;
825 /* toggle to another core is done by gdb as follow */
826 /* maint packet J core_id */
828 /* the next polling trigger an halt event sent to gdb */
829 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
830 (target
->gdb_service
) &&
831 (target
->gdb_service
->target
== NULL
)) {
832 target
->gdb_service
->target
=
833 get_cortex_a(target
, target
->gdb_service
->core
[1]);
834 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
837 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
838 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
839 if (retval
!= ERROR_OK
)
841 cortex_a
->cpudbg_dscr
= dscr
;
843 if (DSCR_RUN_MODE(dscr
) == (DSCR_CORE_HALTED
| DSCR_CORE_RESTARTED
)) {
844 if (prev_target_state
!= TARGET_HALTED
) {
845 /* We have a halting debug event */
846 LOG_DEBUG("Target halted");
847 target
->state
= TARGET_HALTED
;
848 if ((prev_target_state
== TARGET_RUNNING
)
849 || (prev_target_state
== TARGET_UNKNOWN
)
850 || (prev_target_state
== TARGET_RESET
)) {
851 retval
= cortex_a_debug_entry(target
);
852 if (retval
!= ERROR_OK
)
855 retval
= update_halt_gdb(target
);
856 if (retval
!= ERROR_OK
)
860 if (arm_semihosting(target
, &retval
) != 0)
863 target_call_event_callbacks(target
,
864 TARGET_EVENT_HALTED
);
866 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
869 retval
= cortex_a_debug_entry(target
);
870 if (retval
!= ERROR_OK
)
873 retval
= update_halt_gdb(target
);
874 if (retval
!= ERROR_OK
)
878 target_call_event_callbacks(target
,
879 TARGET_EVENT_DEBUG_HALTED
);
883 target
->state
= TARGET_RUNNING
;
888 static int cortex_a_halt(struct target
*target
)
890 int retval
= ERROR_OK
;
892 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
895 * Tell the core to be halted by writing DRCR with 0x1
896 * and then wait for the core to be halted.
898 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
899 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_HALT
);
900 if (retval
!= ERROR_OK
)
904 * enter halting debug mode
906 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
907 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
908 if (retval
!= ERROR_OK
)
911 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
912 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
| DSCR_HALT_DBG_MODE
);
913 if (retval
!= ERROR_OK
)
916 int64_t then
= timeval_ms();
918 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
919 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
920 if (retval
!= ERROR_OK
)
922 if ((dscr
& DSCR_CORE_HALTED
) != 0)
924 if (timeval_ms() > then
+ 1000) {
925 LOG_ERROR("Timeout waiting for halt");
930 target
->debug_reason
= DBG_REASON_DBGRQ
;
935 static int cortex_a_internal_restore(struct target
*target
, int current
,
936 target_addr_t
*address
, int handle_breakpoints
, int debug_execution
)
938 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
939 struct arm
*arm
= &armv7a
->arm
;
943 if (!debug_execution
)
944 target_free_all_working_areas(target
);
947 if (debug_execution
) {
948 /* Disable interrupts */
949 /* We disable interrupts in the PRIMASK register instead of
950 * masking with C_MASKINTS,
951 * This is probably the same issue as Cortex-M3 Errata 377493:
952 * C_MASKINTS in parallel with disabled interrupts can cause
953 * local faults to not be taken. */
954 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].value
, 0, 32, 1);
955 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].dirty
= 1;
956 armv7m
->core_cache
->reg_list
[ARMV7M_PRIMASK
].valid
= 1;
958 /* Make sure we are in Thumb mode */
959 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0, 32,
960 buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].value
, 0,
962 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].dirty
= 1;
963 armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
].valid
= 1;
967 /* current = 1: continue on current pc, otherwise continue at <address> */
968 resume_pc
= buf_get_u32(arm
->pc
->value
, 0, 32);
970 resume_pc
= *address
;
972 *address
= resume_pc
;
974 /* Make sure that the Armv7 gdb thumb fixups does not
975 * kill the return address
977 switch (arm
->core_state
) {
979 resume_pc
&= 0xFFFFFFFC;
981 case ARM_STATE_THUMB
:
982 case ARM_STATE_THUMB_EE
:
983 /* When the return address is loaded into PC
984 * bit 0 must be 1 to stay in Thumb state
988 case ARM_STATE_JAZELLE
:
989 LOG_ERROR("How do I resume into Jazelle state??");
991 case ARM_STATE_AARCH64
:
992 LOG_ERROR("Shoudn't be in AARCH64 state");
995 LOG_DEBUG("resume pc = 0x%08" PRIx32
, resume_pc
);
996 buf_set_u32(arm
->pc
->value
, 0, 32, resume_pc
);
1000 /* restore dpm_mode at system halt */
1001 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1002 /* called it now before restoring context because it uses cpu
1003 * register r0 for restoring cp15 control register */
1004 retval
= cortex_a_restore_cp15_control_reg(target
);
1005 if (retval
!= ERROR_OK
)
1007 retval
= cortex_a_restore_context(target
, handle_breakpoints
);
1008 if (retval
!= ERROR_OK
)
1010 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1011 target
->state
= TARGET_RUNNING
;
1013 /* registers are now invalid */
1014 register_cache_invalidate(arm
->core_cache
);
1017 /* the front-end may request us not to handle breakpoints */
1018 if (handle_breakpoints
) {
1019 /* Single step past breakpoint at current address */
1020 breakpoint
= breakpoint_find(target
, resume_pc
);
1022 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint
->address
);
1023 cortex_m3_unset_breakpoint(target
, breakpoint
);
1024 cortex_m3_single_step_core(target
);
1025 cortex_m3_set_breakpoint(target
, breakpoint
);
1033 static int cortex_a_internal_restart(struct target
*target
)
1035 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1036 struct arm
*arm
= &armv7a
->arm
;
1040 * * Restart core and wait for it to be started. Clear ITRen and sticky
1041 * * exception flags: see ARMv7 ARM, C5.9.
1043 * REVISIT: for single stepping, we probably want to
1044 * disable IRQs by default, with optional override...
1047 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1048 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1049 if (retval
!= ERROR_OK
)
1052 if ((dscr
& DSCR_INSTR_COMP
) == 0)
1053 LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
1055 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1056 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
& ~DSCR_ITR_EN
);
1057 if (retval
!= ERROR_OK
)
1060 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1061 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_RESTART
|
1062 DRCR_CLEAR_EXCEPTIONS
);
1063 if (retval
!= ERROR_OK
)
1066 int64_t then
= timeval_ms();
1068 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1069 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1070 if (retval
!= ERROR_OK
)
1072 if ((dscr
& DSCR_CORE_RESTARTED
) != 0)
1074 if (timeval_ms() > then
+ 1000) {
1075 LOG_ERROR("Timeout waiting for resume");
1080 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1081 target
->state
= TARGET_RUNNING
;
1083 /* registers are now invalid */
1084 register_cache_invalidate(arm
->core_cache
);
1089 static int cortex_a_restore_smp(struct target
*target
, int handle_breakpoints
)
1092 struct target_list
*head
;
1093 struct target
*curr
;
1094 target_addr_t address
;
1095 head
= target
->head
;
1096 while (head
!= (struct target_list
*)NULL
) {
1097 curr
= head
->target
;
1098 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)
1099 && target_was_examined(curr
)) {
1100 /* resume current address , not in step mode */
1101 retval
+= cortex_a_internal_restore(curr
, 1, &address
,
1102 handle_breakpoints
, 0);
1103 retval
+= cortex_a_internal_restart(curr
);
1111 static int cortex_a_resume(struct target
*target
, int current
,
1112 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1115 /* dummy resume for smp toggle in order to reduce gdb impact */
1116 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
1117 /* simulate a start and halt of target */
1118 target
->gdb_service
->target
= NULL
;
1119 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
1120 /* fake resume at next poll we play the target core[1], see poll*/
1121 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1124 cortex_a_internal_restore(target
, current
, &address
, handle_breakpoints
, debug_execution
);
1126 target
->gdb_service
->core
[0] = -1;
1127 retval
= cortex_a_restore_smp(target
, handle_breakpoints
);
1128 if (retval
!= ERROR_OK
)
1131 cortex_a_internal_restart(target
);
1133 if (!debug_execution
) {
1134 target
->state
= TARGET_RUNNING
;
1135 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1136 LOG_DEBUG("target resumed at " TARGET_ADDR_FMT
, address
);
1138 target
->state
= TARGET_DEBUG_RUNNING
;
1139 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1140 LOG_DEBUG("target debug resumed at " TARGET_ADDR_FMT
, address
);
1146 static int cortex_a_debug_entry(struct target
*target
)
1149 uint32_t regfile
[16], cpsr
, spsr
, dscr
;
1150 int retval
= ERROR_OK
;
1151 struct working_area
*regfile_working_area
= NULL
;
1152 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1153 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1154 struct arm
*arm
= &armv7a
->arm
;
1157 LOG_DEBUG("dscr = 0x%08" PRIx32
, cortex_a
->cpudbg_dscr
);
1159 /* REVISIT surely we should not re-read DSCR !! */
1160 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1161 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1162 if (retval
!= ERROR_OK
)
1165 /* REVISIT see A TRM 12.11.4 steps 2..3 -- make sure that any
1166 * imprecise data aborts get discarded by issuing a Data
1167 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
1170 /* Enable the ITR execution once we are in debug mode */
1171 dscr
|= DSCR_ITR_EN
;
1172 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1173 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1174 if (retval
!= ERROR_OK
)
1177 /* Examine debug reason */
1178 arm_dpm_report_dscr(&armv7a
->dpm
, cortex_a
->cpudbg_dscr
);
1180 /* save address of instruction that triggered the watchpoint? */
1181 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
) {
1184 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1185 armv7a
->debug_base
+ CPUDBG_WFAR
,
1187 if (retval
!= ERROR_OK
)
1189 arm_dpm_report_wfar(&armv7a
->dpm
, wfar
);
1192 /* REVISIT fast_reg_read is never set ... */
1194 /* Examine target state and mode */
1195 if (cortex_a
->fast_reg_read
)
1196 target_alloc_working_area(target
, 64, ®file_working_area
);
1199 /* First load register acessible through core debug port*/
1200 if (!regfile_working_area
)
1201 retval
= arm_dpm_read_current_registers(&armv7a
->dpm
);
1203 retval
= cortex_a_read_regs_through_mem(target
,
1204 regfile_working_area
->address
, regfile
);
1206 target_free_working_area(target
, regfile_working_area
);
1207 if (retval
!= ERROR_OK
)
1210 /* read Current PSR */
1211 retval
= cortex_a_dap_read_coreregister_u32(target
, &cpsr
, 16);
1212 /* store current cpsr */
1213 if (retval
!= ERROR_OK
)
1216 LOG_DEBUG("cpsr: %8.8" PRIx32
, cpsr
);
1218 arm_set_cpsr(arm
, cpsr
);
1221 for (i
= 0; i
<= ARM_PC
; i
++) {
1222 reg
= arm_reg_current(arm
, i
);
1224 buf_set_u32(reg
->value
, 0, 32, regfile
[i
]);
1229 /* Fixup PC Resume Address */
1230 if (cpsr
& (1 << 5)) {
1231 /* T bit set for Thumb or ThumbEE state */
1232 regfile
[ARM_PC
] -= 4;
1235 regfile
[ARM_PC
] -= 8;
1239 buf_set_u32(reg
->value
, 0, 32, regfile
[ARM_PC
]);
1240 reg
->dirty
= reg
->valid
;
1244 /* read Saved PSR */
1245 retval
= cortex_a_dap_read_coreregister_u32(target
, &spsr
, 17);
1246 /* store current spsr */
1247 if (retval
!= ERROR_OK
)
1251 buf_set_u32(reg
->value
, 0, 32, spsr
);
1257 /* TODO, Move this */
1258 uint32_t cp15_control_register
, cp15_cacr
, cp15_nacr
;
1259 cortex_a_read_cp(target
, &cp15_control_register
, 15, 0, 1, 0, 0);
1260 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register
);
1262 cortex_a_read_cp(target
, &cp15_cacr
, 15, 0, 1, 0, 2);
1263 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr
);
1265 cortex_a_read_cp(target
, &cp15_nacr
, 15, 0, 1, 1, 2);
1266 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr
);
1269 /* Are we in an exception handler */
1270 /* armv4_5->exception_number = 0; */
1271 if (armv7a
->post_debug_entry
) {
1272 retval
= armv7a
->post_debug_entry(target
);
1273 if (retval
!= ERROR_OK
)
1280 static int cortex_a_post_debug_entry(struct target
*target
)
1282 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1283 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1286 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
1287 retval
= armv7a
->arm
.mrc(target
, 15,
1288 0, 0, /* op1, op2 */
1289 1, 0, /* CRn, CRm */
1290 &cortex_a
->cp15_control_reg
);
1291 if (retval
!= ERROR_OK
)
1293 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
, cortex_a
->cp15_control_reg
);
1294 cortex_a
->cp15_control_reg_curr
= cortex_a
->cp15_control_reg
;
1296 if (armv7a
->armv7a_mmu
.armv7a_cache
.info
== -1)
1297 armv7a_identify_cache(target
);
1299 if (armv7a
->is_armv7r
) {
1300 armv7a
->armv7a_mmu
.mmu_enabled
= 0;
1302 armv7a
->armv7a_mmu
.mmu_enabled
=
1303 (cortex_a
->cp15_control_reg
& 0x1U
) ? 1 : 0;
1305 armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
=
1306 (cortex_a
->cp15_control_reg
& 0x4U
) ? 1 : 0;
1307 armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
=
1308 (cortex_a
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
1309 cortex_a
->curr_mode
= armv7a
->arm
.core_mode
;
1311 /* switch to SVC mode to read DACR */
1312 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_SVC
);
1313 armv7a
->arm
.mrc(target
, 15,
1315 &cortex_a
->cp15_dacr_reg
);
1317 LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32
,
1318 cortex_a
->cp15_dacr_reg
);
1320 dpm_modeswitch(&armv7a
->dpm
, ARM_MODE_ANY
);
1324 int cortex_a_set_dscr_bits(struct target
*target
, unsigned long bit_mask
, unsigned long value
)
1326 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1330 int retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1331 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
1332 if (ERROR_OK
!= retval
)
1335 /* clear bitfield */
1338 dscr
|= value
& bit_mask
;
1340 /* write new DSCR */
1341 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1342 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1346 static int cortex_a_step(struct target
*target
, int current
, target_addr_t address
,
1347 int handle_breakpoints
)
1349 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1350 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1351 struct arm
*arm
= &armv7a
->arm
;
1352 struct breakpoint
*breakpoint
= NULL
;
1353 struct breakpoint stepbreakpoint
;
1357 if (target
->state
!= TARGET_HALTED
) {
1358 LOG_WARNING("target not halted");
1359 return ERROR_TARGET_NOT_HALTED
;
1362 /* current = 1: continue on current pc, otherwise continue at <address> */
1365 buf_set_u32(r
->value
, 0, 32, address
);
1367 address
= buf_get_u32(r
->value
, 0, 32);
1369 /* The front-end may request us not to handle breakpoints.
1370 * But since Cortex-A uses breakpoint for single step,
1371 * we MUST handle breakpoints.
1373 handle_breakpoints
= 1;
1374 if (handle_breakpoints
) {
1375 breakpoint
= breakpoint_find(target
, address
);
1377 cortex_a_unset_breakpoint(target
, breakpoint
);
1380 /* Setup single step breakpoint */
1381 stepbreakpoint
.address
= address
;
1382 stepbreakpoint
.length
= (arm
->core_state
== ARM_STATE_THUMB
)
1384 stepbreakpoint
.type
= BKPT_HARD
;
1385 stepbreakpoint
.set
= 0;
1387 /* Disable interrupts during single step if requested */
1388 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1389 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, DSCR_INT_DIS
);
1390 if (ERROR_OK
!= retval
)
1394 /* Break on IVA mismatch */
1395 cortex_a_set_breakpoint(target
, &stepbreakpoint
, 0x04);
1397 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1399 retval
= cortex_a_resume(target
, 1, address
, 0, 0);
1400 if (retval
!= ERROR_OK
)
1403 int64_t then
= timeval_ms();
1404 while (target
->state
!= TARGET_HALTED
) {
1405 retval
= cortex_a_poll(target
);
1406 if (retval
!= ERROR_OK
)
1408 if (timeval_ms() > then
+ 1000) {
1409 LOG_ERROR("timeout waiting for target halt");
1414 cortex_a_unset_breakpoint(target
, &stepbreakpoint
);
1416 /* Re-enable interrupts if they were disabled */
1417 if (cortex_a
->isrmasking_mode
== CORTEX_A_ISRMASK_ON
) {
1418 retval
= cortex_a_set_dscr_bits(target
, DSCR_INT_DIS
, 0);
1419 if (ERROR_OK
!= retval
)
1424 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
1427 cortex_a_set_breakpoint(target
, breakpoint
, 0);
1429 if (target
->state
!= TARGET_HALTED
)
1430 LOG_DEBUG("target stepped");
1435 static int cortex_a_restore_context(struct target
*target
, bool bpwp
)
1437 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1441 if (armv7a
->pre_restore_context
)
1442 armv7a
->pre_restore_context(target
);
1444 return arm_dpm_write_dirty_registers(&armv7a
->dpm
, bpwp
);
1448 * Cortex-A Breakpoint and watchpoint functions
1451 /* Setup hardware Breakpoint Register Pair */
1452 static int cortex_a_set_breakpoint(struct target
*target
,
1453 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1458 uint8_t byte_addr_select
= 0x0F;
1459 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1460 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1461 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1463 if (breakpoint
->set
) {
1464 LOG_WARNING("breakpoint already set");
1468 if (breakpoint
->type
== BKPT_HARD
) {
1469 while (brp_list
[brp_i
].used
&& (brp_i
< cortex_a
->brp_num
))
1471 if (brp_i
>= cortex_a
->brp_num
) {
1472 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1473 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1475 breakpoint
->set
= brp_i
+ 1;
1476 if (breakpoint
->length
== 2)
1477 byte_addr_select
= (3 << (breakpoint
->address
& 0x02));
1478 control
= ((matchmode
& 0x7) << 20)
1479 | (byte_addr_select
<< 5)
1481 brp_list
[brp_i
].used
= 1;
1482 brp_list
[brp_i
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1483 brp_list
[brp_i
].control
= control
;
1484 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1485 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1486 brp_list
[brp_i
].value
);
1487 if (retval
!= ERROR_OK
)
1489 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1490 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1491 brp_list
[brp_i
].control
);
1492 if (retval
!= ERROR_OK
)
1494 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1495 brp_list
[brp_i
].control
,
1496 brp_list
[brp_i
].value
);
1497 } else if (breakpoint
->type
== BKPT_SOFT
) {
1499 if (breakpoint
->length
== 2)
1500 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1502 buf_set_u32(code
, 0, 32, ARMV5_BKPT(0x11));
1503 retval
= target_read_memory(target
,
1504 breakpoint
->address
& 0xFFFFFFFE,
1505 breakpoint
->length
, 1,
1506 breakpoint
->orig_instr
);
1507 if (retval
!= ERROR_OK
)
1510 /* make sure data cache is cleaned & invalidated down to PoC */
1511 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1512 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1513 breakpoint
->length
);
1516 retval
= target_write_memory(target
,
1517 breakpoint
->address
& 0xFFFFFFFE,
1518 breakpoint
->length
, 1, code
);
1519 if (retval
!= ERROR_OK
)
1522 /* update i-cache at breakpoint location */
1523 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1524 breakpoint
->length
);
1525 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1526 breakpoint
->length
);
1528 breakpoint
->set
= 0x11; /* Any nice value but 0 */
1534 static int cortex_a_set_context_breakpoint(struct target
*target
,
1535 struct breakpoint
*breakpoint
, uint8_t matchmode
)
1537 int retval
= ERROR_FAIL
;
1540 uint8_t byte_addr_select
= 0x0F;
1541 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1542 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1543 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1545 if (breakpoint
->set
) {
1546 LOG_WARNING("breakpoint already set");
1549 /*check available context BRPs*/
1550 while ((brp_list
[brp_i
].used
||
1551 (brp_list
[brp_i
].type
!= BRP_CONTEXT
)) && (brp_i
< cortex_a
->brp_num
))
1554 if (brp_i
>= cortex_a
->brp_num
) {
1555 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1559 breakpoint
->set
= brp_i
+ 1;
1560 control
= ((matchmode
& 0x7) << 20)
1561 | (byte_addr_select
<< 5)
1563 brp_list
[brp_i
].used
= 1;
1564 brp_list
[brp_i
].value
= (breakpoint
->asid
);
1565 brp_list
[brp_i
].control
= control
;
1566 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1567 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1568 brp_list
[brp_i
].value
);
1569 if (retval
!= ERROR_OK
)
1571 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1572 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1573 brp_list
[brp_i
].control
);
1574 if (retval
!= ERROR_OK
)
1576 LOG_DEBUG("brp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1577 brp_list
[brp_i
].control
,
1578 brp_list
[brp_i
].value
);
1583 static int cortex_a_set_hybrid_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1585 int retval
= ERROR_FAIL
;
1586 int brp_1
= 0; /* holds the contextID pair */
1587 int brp_2
= 0; /* holds the IVA pair */
1588 uint32_t control_CTX
, control_IVA
;
1589 uint8_t CTX_byte_addr_select
= 0x0F;
1590 uint8_t IVA_byte_addr_select
= 0x0F;
1591 uint8_t CTX_machmode
= 0x03;
1592 uint8_t IVA_machmode
= 0x01;
1593 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1594 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1595 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1597 if (breakpoint
->set
) {
1598 LOG_WARNING("breakpoint already set");
1601 /*check available context BRPs*/
1602 while ((brp_list
[brp_1
].used
||
1603 (brp_list
[brp_1
].type
!= BRP_CONTEXT
)) && (brp_1
< cortex_a
->brp_num
))
1606 printf("brp(CTX) found num: %d\n", brp_1
);
1607 if (brp_1
>= cortex_a
->brp_num
) {
1608 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1612 while ((brp_list
[brp_2
].used
||
1613 (brp_list
[brp_2
].type
!= BRP_NORMAL
)) && (brp_2
< cortex_a
->brp_num
))
1616 printf("brp(IVA) found num: %d\n", brp_2
);
1617 if (brp_2
>= cortex_a
->brp_num
) {
1618 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1622 breakpoint
->set
= brp_1
+ 1;
1623 breakpoint
->linked_BRP
= brp_2
;
1624 control_CTX
= ((CTX_machmode
& 0x7) << 20)
1627 | (CTX_byte_addr_select
<< 5)
1629 brp_list
[brp_1
].used
= 1;
1630 brp_list
[brp_1
].value
= (breakpoint
->asid
);
1631 brp_list
[brp_1
].control
= control_CTX
;
1632 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1633 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1634 brp_list
[brp_1
].value
);
1635 if (retval
!= ERROR_OK
)
1637 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1638 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_1
].BRPn
,
1639 brp_list
[brp_1
].control
);
1640 if (retval
!= ERROR_OK
)
1643 control_IVA
= ((IVA_machmode
& 0x7) << 20)
1645 | (IVA_byte_addr_select
<< 5)
1647 brp_list
[brp_2
].used
= 1;
1648 brp_list
[brp_2
].value
= (breakpoint
->address
& 0xFFFFFFFC);
1649 brp_list
[brp_2
].control
= control_IVA
;
1650 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1651 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1652 brp_list
[brp_2
].value
);
1653 if (retval
!= ERROR_OK
)
1655 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1656 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_2
].BRPn
,
1657 brp_list
[brp_2
].control
);
1658 if (retval
!= ERROR_OK
)
1664 static int cortex_a_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1667 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1668 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
1669 struct cortex_a_brp
*brp_list
= cortex_a
->brp_list
;
1671 if (!breakpoint
->set
) {
1672 LOG_WARNING("breakpoint not set");
1676 if (breakpoint
->type
== BKPT_HARD
) {
1677 if ((breakpoint
->address
!= 0) && (breakpoint
->asid
!= 0)) {
1678 int brp_i
= breakpoint
->set
- 1;
1679 int brp_j
= breakpoint
->linked_BRP
;
1680 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1681 LOG_DEBUG("Invalid BRP number in breakpoint");
1684 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1685 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1686 brp_list
[brp_i
].used
= 0;
1687 brp_list
[brp_i
].value
= 0;
1688 brp_list
[brp_i
].control
= 0;
1689 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1690 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1691 brp_list
[brp_i
].control
);
1692 if (retval
!= ERROR_OK
)
1694 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1695 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1696 brp_list
[brp_i
].value
);
1697 if (retval
!= ERROR_OK
)
1699 if ((brp_j
< 0) || (brp_j
>= cortex_a
->brp_num
)) {
1700 LOG_DEBUG("Invalid BRP number in breakpoint");
1703 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_j
,
1704 brp_list
[brp_j
].control
, brp_list
[brp_j
].value
);
1705 brp_list
[brp_j
].used
= 0;
1706 brp_list
[brp_j
].value
= 0;
1707 brp_list
[brp_j
].control
= 0;
1708 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1709 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1710 brp_list
[brp_j
].control
);
1711 if (retval
!= ERROR_OK
)
1713 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1714 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_j
].BRPn
,
1715 brp_list
[brp_j
].value
);
1716 if (retval
!= ERROR_OK
)
1718 breakpoint
->linked_BRP
= 0;
1719 breakpoint
->set
= 0;
1723 int brp_i
= breakpoint
->set
- 1;
1724 if ((brp_i
< 0) || (brp_i
>= cortex_a
->brp_num
)) {
1725 LOG_DEBUG("Invalid BRP number in breakpoint");
1728 LOG_DEBUG("rbp %i control 0x%0" PRIx32
" value 0x%0" PRIx32
, brp_i
,
1729 brp_list
[brp_i
].control
, brp_list
[brp_i
].value
);
1730 brp_list
[brp_i
].used
= 0;
1731 brp_list
[brp_i
].value
= 0;
1732 brp_list
[brp_i
].control
= 0;
1733 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1734 + CPUDBG_BCR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1735 brp_list
[brp_i
].control
);
1736 if (retval
!= ERROR_OK
)
1738 retval
= cortex_a_dap_write_memap_register_u32(target
, armv7a
->debug_base
1739 + CPUDBG_BVR_BASE
+ 4 * brp_list
[brp_i
].BRPn
,
1740 brp_list
[brp_i
].value
);
1741 if (retval
!= ERROR_OK
)
1743 breakpoint
->set
= 0;
1748 /* make sure data cache is cleaned & invalidated down to PoC */
1749 if (!armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
) {
1750 armv7a_cache_flush_virt(target
, breakpoint
->address
,
1751 breakpoint
->length
);
1754 /* restore original instruction (kept in target endianness) */
1755 if (breakpoint
->length
== 4) {
1756 retval
= target_write_memory(target
,
1757 breakpoint
->address
& 0xFFFFFFFE,
1758 4, 1, breakpoint
->orig_instr
);
1759 if (retval
!= ERROR_OK
)
1762 retval
= target_write_memory(target
,
1763 breakpoint
->address
& 0xFFFFFFFE,
1764 2, 1, breakpoint
->orig_instr
);
1765 if (retval
!= ERROR_OK
)
1769 /* update i-cache at breakpoint location */
1770 armv7a_l1_d_cache_inval_virt(target
, breakpoint
->address
,
1771 breakpoint
->length
);
1772 armv7a_l1_i_cache_inval_virt(target
, breakpoint
->address
,
1773 breakpoint
->length
);
1775 breakpoint
->set
= 0;
1780 static int cortex_a_add_breakpoint(struct target
*target
,
1781 struct breakpoint
*breakpoint
)
1783 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1785 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1786 LOG_INFO("no hardware breakpoint available");
1787 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1790 if (breakpoint
->type
== BKPT_HARD
)
1791 cortex_a
->brp_num_available
--;
1793 return cortex_a_set_breakpoint(target
, breakpoint
, 0x00); /* Exact match */
1796 static int cortex_a_add_context_breakpoint(struct target
*target
,
1797 struct breakpoint
*breakpoint
)
1799 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1801 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1802 LOG_INFO("no hardware breakpoint available");
1803 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1806 if (breakpoint
->type
== BKPT_HARD
)
1807 cortex_a
->brp_num_available
--;
1809 return cortex_a_set_context_breakpoint(target
, breakpoint
, 0x02); /* asid match */
1812 static int cortex_a_add_hybrid_breakpoint(struct target
*target
,
1813 struct breakpoint
*breakpoint
)
1815 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1817 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_a
->brp_num_available
< 1)) {
1818 LOG_INFO("no hardware breakpoint available");
1819 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1822 if (breakpoint
->type
== BKPT_HARD
)
1823 cortex_a
->brp_num_available
--;
1825 return cortex_a_set_hybrid_breakpoint(target
, breakpoint
); /* ??? */
1829 static int cortex_a_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1831 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
1834 /* It is perfectly possible to remove breakpoints while the target is running */
1835 if (target
->state
!= TARGET_HALTED
) {
1836 LOG_WARNING("target not halted");
1837 return ERROR_TARGET_NOT_HALTED
;
1841 if (breakpoint
->set
) {
1842 cortex_a_unset_breakpoint(target
, breakpoint
);
1843 if (breakpoint
->type
== BKPT_HARD
)
1844 cortex_a
->brp_num_available
++;
1852 * Cortex-A Reset functions
1855 static int cortex_a_assert_reset(struct target
*target
)
1857 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1861 /* FIXME when halt is requested, make it work somehow... */
1863 /* This function can be called in "target not examined" state */
1865 /* Issue some kind of warm reset. */
1866 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
))
1867 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1868 else if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1869 /* REVISIT handle "pulls" cases, if there's
1870 * hardware that needs them to work.
1874 * FIXME: fix reset when transport is SWD. This is a temporary
1875 * work-around for release v0.10 that is not intended to stay!
1877 if (transport_is_swd() ||
1878 (target
->reset_halt
&& (jtag_get_reset_config() & RESET_SRST_NO_GATING
)))
1879 jtag_add_reset(0, 1);
1882 LOG_ERROR("%s: how to reset?", target_name(target
));
1886 /* registers are now invalid */
1887 if (target_was_examined(target
))
1888 register_cache_invalidate(armv7a
->arm
.core_cache
);
1890 target
->state
= TARGET_RESET
;
1895 static int cortex_a_deassert_reset(struct target
*target
)
1901 /* be certain SRST is off */
1902 jtag_add_reset(0, 0);
1904 if (target_was_examined(target
)) {
1905 retval
= cortex_a_poll(target
);
1906 if (retval
!= ERROR_OK
)
1910 if (target
->reset_halt
) {
1911 if (target
->state
!= TARGET_HALTED
) {
1912 LOG_WARNING("%s: ran after reset and before halt ...",
1913 target_name(target
));
1914 if (target_was_examined(target
)) {
1915 retval
= target_halt(target
);
1916 if (retval
!= ERROR_OK
)
1919 target
->state
= TARGET_UNKNOWN
;
1926 static int cortex_a_set_dcc_mode(struct target
*target
, uint32_t mode
, uint32_t *dscr
)
1928 /* Changes the mode of the DCC between non-blocking, stall, and fast mode.
1929 * New desired mode must be in mode. Current value of DSCR must be in
1930 * *dscr, which is updated with new value.
1932 * This function elides actually sending the mode-change over the debug
1933 * interface if the mode is already set as desired.
1935 uint32_t new_dscr
= (*dscr
& ~DSCR_EXT_DCC_MASK
) | mode
;
1936 if (new_dscr
!= *dscr
) {
1937 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1938 int retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
1939 armv7a
->debug_base
+ CPUDBG_DSCR
, new_dscr
);
1940 if (retval
== ERROR_OK
)
1948 static int cortex_a_wait_dscr_bits(struct target
*target
, uint32_t mask
,
1949 uint32_t value
, uint32_t *dscr
)
1951 /* Waits until the specified bit(s) of DSCR take on a specified value. */
1952 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1953 int64_t then
= timeval_ms();
1956 while ((*dscr
& mask
) != value
) {
1957 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1958 armv7a
->debug_base
+ CPUDBG_DSCR
, dscr
);
1959 if (retval
!= ERROR_OK
)
1961 if (timeval_ms() > then
+ 1000) {
1962 LOG_ERROR("timeout waiting for DSCR bit change");
1969 static int cortex_a_read_copro(struct target
*target
, uint32_t opcode
,
1970 uint32_t *data
, uint32_t *dscr
)
1973 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
1975 /* Move from coprocessor to R0. */
1976 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
1977 if (retval
!= ERROR_OK
)
1980 /* Move from R0 to DTRTX. */
1981 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), dscr
);
1982 if (retval
!= ERROR_OK
)
1985 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
1986 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
1987 * must also check TXfull_l). Most of the time this will be free
1988 * because TXfull_l will be set immediately and cached in dscr. */
1989 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
1990 DSCR_DTRTX_FULL_LATCHED
, dscr
);
1991 if (retval
!= ERROR_OK
)
1994 /* Read the value transferred to DTRTX. */
1995 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
1996 armv7a
->debug_base
+ CPUDBG_DTRTX
, data
);
1997 if (retval
!= ERROR_OK
)
2003 static int cortex_a_read_dfar_dfsr(struct target
*target
, uint32_t *dfar
,
2004 uint32_t *dfsr
, uint32_t *dscr
)
2009 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2010 if (retval
!= ERROR_OK
)
2015 retval
= cortex_a_read_copro(target
, ARMV4_5_MRC(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2016 if (retval
!= ERROR_OK
)
2023 static int cortex_a_write_copro(struct target
*target
, uint32_t opcode
,
2024 uint32_t data
, uint32_t *dscr
)
2027 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2029 /* Write the value into DTRRX. */
2030 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2031 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2032 if (retval
!= ERROR_OK
)
2035 /* Move from DTRRX to R0. */
2036 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), dscr
);
2037 if (retval
!= ERROR_OK
)
2040 /* Move from R0 to coprocessor. */
2041 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2042 if (retval
!= ERROR_OK
)
2045 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2046 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2047 * check RXfull_l). Most of the time this will be free because RXfull_l
2048 * will be cleared immediately and cached in dscr. */
2049 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2050 if (retval
!= ERROR_OK
)
2056 static int cortex_a_write_dfar_dfsr(struct target
*target
, uint32_t dfar
,
2057 uint32_t dfsr
, uint32_t *dscr
)
2061 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 6, 0, 0), dfar
, dscr
);
2062 if (retval
!= ERROR_OK
)
2065 retval
= cortex_a_write_copro(target
, ARMV4_5_MCR(15, 0, 0, 5, 0, 0), dfsr
, dscr
);
2066 if (retval
!= ERROR_OK
)
2072 static int cortex_a_dfsr_to_error_code(uint32_t dfsr
)
2074 uint32_t status
, upper4
;
2076 if (dfsr
& (1 << 9)) {
2078 status
= dfsr
& 0x3f;
2079 upper4
= status
>> 2;
2080 if (upper4
== 1 || upper4
== 2 || upper4
== 3 || upper4
== 15)
2081 return ERROR_TARGET_TRANSLATION_FAULT
;
2082 else if (status
== 33)
2083 return ERROR_TARGET_UNALIGNED_ACCESS
;
2085 return ERROR_TARGET_DATA_ABORT
;
2087 /* Normal format. */
2088 status
= ((dfsr
>> 6) & 0x10) | (dfsr
& 0xf);
2090 return ERROR_TARGET_UNALIGNED_ACCESS
;
2091 else if (status
== 5 || status
== 7 || status
== 3 || status
== 6 ||
2092 status
== 9 || status
== 11 || status
== 13 || status
== 15)
2093 return ERROR_TARGET_TRANSLATION_FAULT
;
2095 return ERROR_TARGET_DATA_ABORT
;
2099 static int cortex_a_write_cpu_memory_slow(struct target
*target
,
2100 uint32_t size
, uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2102 /* Writes count objects of size size from *buffer. Old value of DSCR must
2103 * be in *dscr; updated to new value. This is slow because it works for
2104 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2105 * the address is aligned, cortex_a_write_cpu_memory_fast should be
2108 * - Address is in R0.
2109 * - R0 is marked dirty.
2111 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2112 struct arm
*arm
= &armv7a
->arm
;
2115 /* Mark register R1 as dirty, to use for transferring data. */
2116 arm_reg_current(arm
, 1)->dirty
= true;
2118 /* Switch to non-blocking mode if not already in that mode. */
2119 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2120 if (retval
!= ERROR_OK
)
2123 /* Go through the objects. */
2125 /* Write the value to store into DTRRX. */
2126 uint32_t data
, opcode
;
2130 data
= target_buffer_get_u16(target
, buffer
);
2132 data
= target_buffer_get_u32(target
, buffer
);
2133 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2134 armv7a
->debug_base
+ CPUDBG_DTRRX
, data
);
2135 if (retval
!= ERROR_OK
)
2138 /* Transfer the value from DTRRX to R1. */
2139 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), dscr
);
2140 if (retval
!= ERROR_OK
)
2143 /* Write the value transferred to R1 into memory. */
2145 opcode
= ARMV4_5_STRB_IP(1, 0);
2147 opcode
= ARMV4_5_STRH_IP(1, 0);
2149 opcode
= ARMV4_5_STRW_IP(1, 0);
2150 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2151 if (retval
!= ERROR_OK
)
2154 /* Check for faults and return early. */
2155 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2156 return ERROR_OK
; /* A data fault is not considered a system failure. */
2158 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture
2159 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2160 * must also check RXfull_l). Most of the time this will be free
2161 * because RXfull_l will be cleared immediately and cached in dscr. */
2162 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, dscr
);
2163 if (retval
!= ERROR_OK
)
2174 static int cortex_a_write_cpu_memory_fast(struct target
*target
,
2175 uint32_t count
, const uint8_t *buffer
, uint32_t *dscr
)
2177 /* Writes count objects of size 4 from *buffer. Old value of DSCR must be
2178 * in *dscr; updated to new value. This is fast but only works for
2179 * word-sized objects at aligned addresses.
2181 * - Address is in R0 and must be a multiple of 4.
2182 * - R0 is marked dirty.
2184 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2187 /* Switch to fast mode if not already in that mode. */
2188 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2189 if (retval
!= ERROR_OK
)
2192 /* Latch STC instruction. */
2193 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2194 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
2195 if (retval
!= ERROR_OK
)
2198 /* Transfer all the data and issue all the instructions. */
2199 return mem_ap_write_buf_noincr(armv7a
->debug_ap
, buffer
,
2200 4, count
, armv7a
->debug_base
+ CPUDBG_DTRRX
);
2203 static int cortex_a_write_cpu_memory(struct target
*target
,
2204 uint32_t address
, uint32_t size
,
2205 uint32_t count
, const uint8_t *buffer
)
2207 /* Write memory through the CPU. */
2208 int retval
, final_retval
;
2209 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2210 struct arm
*arm
= &armv7a
->arm
;
2211 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2213 LOG_DEBUG("Writing CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2214 address
, size
, count
);
2215 if (target
->state
!= TARGET_HALTED
) {
2216 LOG_WARNING("target not halted");
2217 return ERROR_TARGET_NOT_HALTED
;
2223 /* Clear any abort. */
2224 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2225 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2226 if (retval
!= ERROR_OK
)
2230 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2231 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2232 if (retval
!= ERROR_OK
)
2235 /* Switch to non-blocking mode if not already in that mode. */
2236 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2237 if (retval
!= ERROR_OK
)
2240 /* Mark R0 as dirty. */
2241 arm_reg_current(arm
, 0)->dirty
= true;
2243 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2244 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2245 if (retval
!= ERROR_OK
)
2248 /* Get the memory address into R0. */
2249 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2250 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2251 if (retval
!= ERROR_OK
)
2253 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2254 if (retval
!= ERROR_OK
)
2257 if (size
== 4 && (address
% 4) == 0) {
2258 /* We are doing a word-aligned transfer, so use fast mode. */
2259 retval
= cortex_a_write_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2261 /* Use slow path. */
2262 retval
= cortex_a_write_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2266 final_retval
= retval
;
2268 /* Switch to non-blocking mode if not already in that mode. */
2269 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2270 if (final_retval
== ERROR_OK
)
2271 final_retval
= retval
;
2273 /* Wait for last issued instruction to complete. */
2274 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2275 if (final_retval
== ERROR_OK
)
2276 final_retval
= retval
;
2278 /* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
2279 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2280 * check RXfull_l). Most of the time this will be free because RXfull_l
2281 * will be cleared immediately and cached in dscr. However, don't do this
2282 * if there is fault, because then the instruction might not have completed
2284 if (!(dscr
& DSCR_STICKY_ABORT_PRECISE
)) {
2285 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRRX_FULL_LATCHED
, 0, &dscr
);
2286 if (retval
!= ERROR_OK
)
2290 /* If there were any sticky abort flags, clear them. */
2291 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2293 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2294 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2295 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2300 /* Handle synchronous data faults. */
2301 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2302 if (final_retval
== ERROR_OK
) {
2303 /* Final return value will reflect cause of fault. */
2304 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2305 if (retval
== ERROR_OK
) {
2306 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2307 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2309 final_retval
= retval
;
2311 /* Fault destroyed DFAR/DFSR; restore them. */
2312 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2313 if (retval
!= ERROR_OK
)
2314 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2317 /* Handle asynchronous data faults. */
2318 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2319 if (final_retval
== ERROR_OK
)
2320 /* No other error has been recorded so far, so keep this one. */
2321 final_retval
= ERROR_TARGET_DATA_ABORT
;
2324 /* If the DCC is nonempty, clear it. */
2325 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2327 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2328 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2329 if (final_retval
== ERROR_OK
)
2330 final_retval
= retval
;
2332 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2333 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2334 if (final_retval
== ERROR_OK
)
2335 final_retval
= retval
;
2339 return final_retval
;
2342 static int cortex_a_read_cpu_memory_slow(struct target
*target
,
2343 uint32_t size
, uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2345 /* Reads count objects of size size into *buffer. Old value of DSCR must be
2346 * in *dscr; updated to new value. This is slow because it works for
2347 * non-word-sized objects and (maybe) unaligned accesses. If size == 4 and
2348 * the address is aligned, cortex_a_read_cpu_memory_fast should be
2351 * - Address is in R0.
2352 * - R0 is marked dirty.
2354 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2355 struct arm
*arm
= &armv7a
->arm
;
2358 /* Mark register R1 as dirty, to use for transferring data. */
2359 arm_reg_current(arm
, 1)->dirty
= true;
2361 /* Switch to non-blocking mode if not already in that mode. */
2362 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2363 if (retval
!= ERROR_OK
)
2366 /* Go through the objects. */
2368 /* Issue a load of the appropriate size to R1. */
2369 uint32_t opcode
, data
;
2371 opcode
= ARMV4_5_LDRB_IP(1, 0);
2373 opcode
= ARMV4_5_LDRH_IP(1, 0);
2375 opcode
= ARMV4_5_LDRW_IP(1, 0);
2376 retval
= cortex_a_exec_opcode(target
, opcode
, dscr
);
2377 if (retval
!= ERROR_OK
)
2380 /* Issue a write of R1 to DTRTX. */
2381 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MCR(14, 0, 1, 0, 5, 0), dscr
);
2382 if (retval
!= ERROR_OK
)
2385 /* Check for faults and return early. */
2386 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2387 return ERROR_OK
; /* A data fault is not considered a system failure. */
2389 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture
2390 * manual section C8.4.3, checking InstrCmpl_l is not sufficient; one
2391 * must also check TXfull_l). Most of the time this will be free
2392 * because TXfull_l will be set immediately and cached in dscr. */
2393 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2394 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2395 if (retval
!= ERROR_OK
)
2398 /* Read the value transferred to DTRTX into the buffer. */
2399 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2400 armv7a
->debug_base
+ CPUDBG_DTRTX
, &data
);
2401 if (retval
!= ERROR_OK
)
2404 *buffer
= (uint8_t) data
;
2406 target_buffer_set_u16(target
, buffer
, (uint16_t) data
);
2408 target_buffer_set_u32(target
, buffer
, data
);
2418 static int cortex_a_read_cpu_memory_fast(struct target
*target
,
2419 uint32_t count
, uint8_t *buffer
, uint32_t *dscr
)
2421 /* Reads count objects of size 4 into *buffer. Old value of DSCR must be in
2422 * *dscr; updated to new value. This is fast but only works for word-sized
2423 * objects at aligned addresses.
2425 * - Address is in R0 and must be a multiple of 4.
2426 * - R0 is marked dirty.
2428 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2432 /* Switch to non-blocking mode if not already in that mode. */
2433 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2434 if (retval
!= ERROR_OK
)
2437 /* Issue the LDC instruction via a write to ITR. */
2438 retval
= cortex_a_exec_opcode(target
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4), dscr
);
2439 if (retval
!= ERROR_OK
)
2445 /* Switch to fast mode if not already in that mode. */
2446 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_FAST_MODE
, dscr
);
2447 if (retval
!= ERROR_OK
)
2450 /* Latch LDC instruction. */
2451 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2452 armv7a
->debug_base
+ CPUDBG_ITR
, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
2453 if (retval
!= ERROR_OK
)
2456 /* Read the value transferred to DTRTX into the buffer. Due to fast
2457 * mode rules, this blocks until the instruction finishes executing and
2458 * then reissues the read instruction to read the next word from
2459 * memory. The last read of DTRTX in this call reads the second-to-last
2460 * word from memory and issues the read instruction for the last word.
2462 retval
= mem_ap_read_buf_noincr(armv7a
->debug_ap
, buffer
,
2463 4, count
, armv7a
->debug_base
+ CPUDBG_DTRTX
);
2464 if (retval
!= ERROR_OK
)
2468 buffer
+= count
* 4;
2471 /* Wait for last issued instruction to complete. */
2472 retval
= cortex_a_wait_instrcmpl(target
, dscr
, false);
2473 if (retval
!= ERROR_OK
)
2476 /* Switch to non-blocking mode if not already in that mode. */
2477 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, dscr
);
2478 if (retval
!= ERROR_OK
)
2481 /* Check for faults and return early. */
2482 if (*dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
))
2483 return ERROR_OK
; /* A data fault is not considered a system failure. */
2485 /* Wait until DTRTX is full (according to ARMv7-A/-R architecture manual
2486 * section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
2487 * check TXfull_l). Most of the time this will be free because TXfull_l
2488 * will be set immediately and cached in dscr. */
2489 retval
= cortex_a_wait_dscr_bits(target
, DSCR_DTRTX_FULL_LATCHED
,
2490 DSCR_DTRTX_FULL_LATCHED
, dscr
);
2491 if (retval
!= ERROR_OK
)
2494 /* Read the value transferred to DTRTX into the buffer. This is the last
2496 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2497 armv7a
->debug_base
+ CPUDBG_DTRTX
, &u32
);
2498 if (retval
!= ERROR_OK
)
2500 target_buffer_set_u32(target
, buffer
, u32
);
2505 static int cortex_a_read_cpu_memory(struct target
*target
,
2506 uint32_t address
, uint32_t size
,
2507 uint32_t count
, uint8_t *buffer
)
2509 /* Read memory through the CPU. */
2510 int retval
, final_retval
;
2511 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2512 struct arm
*arm
= &armv7a
->arm
;
2513 uint32_t dscr
, orig_dfar
, orig_dfsr
, fault_dscr
, fault_dfar
, fault_dfsr
;
2515 LOG_DEBUG("Reading CPU memory address 0x%" PRIx32
" size %" PRIu32
" count %" PRIu32
,
2516 address
, size
, count
);
2517 if (target
->state
!= TARGET_HALTED
) {
2518 LOG_WARNING("target not halted");
2519 return ERROR_TARGET_NOT_HALTED
;
2525 /* Clear any abort. */
2526 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2527 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2528 if (retval
!= ERROR_OK
)
2532 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2533 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2534 if (retval
!= ERROR_OK
)
2537 /* Switch to non-blocking mode if not already in that mode. */
2538 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2539 if (retval
!= ERROR_OK
)
2542 /* Mark R0 as dirty. */
2543 arm_reg_current(arm
, 0)->dirty
= true;
2545 /* Read DFAR and DFSR, as they will be modified in the event of a fault. */
2546 retval
= cortex_a_read_dfar_dfsr(target
, &orig_dfar
, &orig_dfsr
, &dscr
);
2547 if (retval
!= ERROR_OK
)
2550 /* Get the memory address into R0. */
2551 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2552 armv7a
->debug_base
+ CPUDBG_DTRRX
, address
);
2553 if (retval
!= ERROR_OK
)
2555 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr
);
2556 if (retval
!= ERROR_OK
)
2559 if (size
== 4 && (address
% 4) == 0) {
2560 /* We are doing a word-aligned transfer, so use fast mode. */
2561 retval
= cortex_a_read_cpu_memory_fast(target
, count
, buffer
, &dscr
);
2563 /* Use slow path. */
2564 retval
= cortex_a_read_cpu_memory_slow(target
, size
, count
, buffer
, &dscr
);
2568 final_retval
= retval
;
2570 /* Switch to non-blocking mode if not already in that mode. */
2571 retval
= cortex_a_set_dcc_mode(target
, DSCR_EXT_DCC_NON_BLOCKING
, &dscr
);
2572 if (final_retval
== ERROR_OK
)
2573 final_retval
= retval
;
2575 /* Wait for last issued instruction to complete. */
2576 retval
= cortex_a_wait_instrcmpl(target
, &dscr
, true);
2577 if (final_retval
== ERROR_OK
)
2578 final_retval
= retval
;
2580 /* If there were any sticky abort flags, clear them. */
2581 if (dscr
& (DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
)) {
2583 mem_ap_write_atomic_u32(armv7a
->debug_ap
,
2584 armv7a
->debug_base
+ CPUDBG_DRCR
, DRCR_CLEAR_EXCEPTIONS
);
2585 dscr
&= ~(DSCR_STICKY_ABORT_PRECISE
| DSCR_STICKY_ABORT_IMPRECISE
);
2590 /* Handle synchronous data faults. */
2591 if (fault_dscr
& DSCR_STICKY_ABORT_PRECISE
) {
2592 if (final_retval
== ERROR_OK
) {
2593 /* Final return value will reflect cause of fault. */
2594 retval
= cortex_a_read_dfar_dfsr(target
, &fault_dfar
, &fault_dfsr
, &dscr
);
2595 if (retval
== ERROR_OK
) {
2596 LOG_ERROR("data abort at 0x%08" PRIx32
", dfsr = 0x%08" PRIx32
, fault_dfar
, fault_dfsr
);
2597 final_retval
= cortex_a_dfsr_to_error_code(fault_dfsr
);
2599 final_retval
= retval
;
2601 /* Fault destroyed DFAR/DFSR; restore them. */
2602 retval
= cortex_a_write_dfar_dfsr(target
, orig_dfar
, orig_dfsr
, &dscr
);
2603 if (retval
!= ERROR_OK
)
2604 LOG_ERROR("error restoring dfar/dfsr - dscr = 0x%08" PRIx32
, dscr
);
2607 /* Handle asynchronous data faults. */
2608 if (fault_dscr
& DSCR_STICKY_ABORT_IMPRECISE
) {
2609 if (final_retval
== ERROR_OK
)
2610 /* No other error has been recorded so far, so keep this one. */
2611 final_retval
= ERROR_TARGET_DATA_ABORT
;
2614 /* If the DCC is nonempty, clear it. */
2615 if (dscr
& DSCR_DTRTX_FULL_LATCHED
) {
2617 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2618 armv7a
->debug_base
+ CPUDBG_DTRTX
, &dummy
);
2619 if (final_retval
== ERROR_OK
)
2620 final_retval
= retval
;
2622 if (dscr
& DSCR_DTRRX_FULL_LATCHED
) {
2623 retval
= cortex_a_exec_opcode(target
, ARMV4_5_MRC(14, 0, 1, 0, 5, 0), &dscr
);
2624 if (final_retval
== ERROR_OK
)
2625 final_retval
= retval
;
2629 return final_retval
;
2634 * Cortex-A Memory access
2636 * This is same Cortex-M3 but we must also use the correct
2637 * ap number for every access.
2640 static int cortex_a_read_phys_memory(struct target
*target
,
2641 target_addr_t address
, uint32_t size
,
2642 uint32_t count
, uint8_t *buffer
)
2644 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2645 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2646 uint8_t apsel
= swjdp
->apsel
;
2649 if (!count
|| !buffer
)
2650 return ERROR_COMMAND_SYNTAX_ERROR
;
2652 LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2653 address
, size
, count
);
2655 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2656 return mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2658 /* read memory through the CPU */
2659 cortex_a_prep_memaccess(target
, 1);
2660 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2661 cortex_a_post_memaccess(target
, 1);
2666 static int cortex_a_read_memory(struct target
*target
, target_addr_t address
,
2667 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2671 /* cortex_a handles unaligned memory access */
2672 LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2673 address
, size
, count
);
2675 cortex_a_prep_memaccess(target
, 0);
2676 retval
= cortex_a_read_cpu_memory(target
, address
, size
, count
, buffer
);
2677 cortex_a_post_memaccess(target
, 0);
2682 static int cortex_a_read_memory_ahb(struct target
*target
, target_addr_t address
,
2683 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2685 int mmu_enabled
= 0;
2686 target_addr_t virt
, phys
;
2688 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2689 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2690 uint8_t apsel
= swjdp
->apsel
;
2692 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2693 return target_read_memory(target
, address
, size
, count
, buffer
);
2695 /* cortex_a handles unaligned memory access */
2696 LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2697 address
, size
, count
);
2699 /* determine if MMU was enabled on target stop */
2700 if (!armv7a
->is_armv7r
) {
2701 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2702 if (retval
!= ERROR_OK
)
2708 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2709 if (retval
!= ERROR_OK
)
2712 LOG_DEBUG("Reading at virtual address. "
2713 "Translating v:" TARGET_ADDR_FMT
" to r:" TARGET_ADDR_FMT
,
2718 if (!count
|| !buffer
)
2719 return ERROR_COMMAND_SYNTAX_ERROR
;
2721 retval
= mem_ap_read_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2726 static int cortex_a_write_phys_memory(struct target
*target
,
2727 target_addr_t address
, uint32_t size
,
2728 uint32_t count
, const uint8_t *buffer
)
2730 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2731 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2732 uint8_t apsel
= swjdp
->apsel
;
2735 if (!count
|| !buffer
)
2736 return ERROR_COMMAND_SYNTAX_ERROR
;
2738 LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2739 address
, size
, count
);
2741 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
))
2742 return mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2744 /* write memory through the CPU */
2745 cortex_a_prep_memaccess(target
, 1);
2746 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2747 cortex_a_post_memaccess(target
, 1);
2752 static int cortex_a_write_memory(struct target
*target
, target_addr_t address
,
2753 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2757 /* cortex_a handles unaligned memory access */
2758 LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2759 address
, size
, count
);
2761 /* memory writes bypass the caches, must flush before writing */
2762 armv7a_cache_auto_flush_on_write(target
, address
, size
* count
);
2764 cortex_a_prep_memaccess(target
, 0);
2765 retval
= cortex_a_write_cpu_memory(target
, address
, size
, count
, buffer
);
2766 cortex_a_post_memaccess(target
, 0);
2770 static int cortex_a_write_memory_ahb(struct target
*target
, target_addr_t address
,
2771 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2773 int mmu_enabled
= 0;
2774 target_addr_t virt
, phys
;
2776 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2777 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2778 uint8_t apsel
= swjdp
->apsel
;
2780 if (!armv7a
->memory_ap_available
|| (apsel
!= armv7a
->memory_ap
->ap_num
))
2781 return target_write_memory(target
, address
, size
, count
, buffer
);
2783 /* cortex_a handles unaligned memory access */
2784 LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT
"; size %" PRId32
"; count %" PRId32
,
2785 address
, size
, count
);
2787 /* determine if MMU was enabled on target stop */
2788 if (!armv7a
->is_armv7r
) {
2789 retval
= cortex_a_mmu(target
, &mmu_enabled
);
2790 if (retval
!= ERROR_OK
)
2796 retval
= cortex_a_virt2phys(target
, virt
, &phys
);
2797 if (retval
!= ERROR_OK
)
2800 LOG_DEBUG("Writing to virtual address. "
2801 "Translating v:" TARGET_ADDR_FMT
" to r:" TARGET_ADDR_FMT
,
2807 if (!count
|| !buffer
)
2808 return ERROR_COMMAND_SYNTAX_ERROR
;
2810 retval
= mem_ap_write_buf(armv7a
->memory_ap
, buffer
, size
, count
, address
);
2815 static int cortex_a_read_buffer(struct target
*target
, target_addr_t address
,
2816 uint32_t count
, uint8_t *buffer
)
2820 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2821 * will have something to do with the size we leave to it. */
2822 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2823 if (address
& size
) {
2824 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, 1, buffer
);
2825 if (retval
!= ERROR_OK
)
2833 /* Read the data with as large access size as possible. */
2834 for (; size
> 0; size
/= 2) {
2835 uint32_t aligned
= count
- count
% size
;
2837 int retval
= cortex_a_read_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2838 if (retval
!= ERROR_OK
)
2849 static int cortex_a_write_buffer(struct target
*target
, target_addr_t address
,
2850 uint32_t count
, const uint8_t *buffer
)
2854 /* Align up to maximum 4 bytes. The loop condition makes sure the next pass
2855 * will have something to do with the size we leave to it. */
2856 for (size
= 1; size
< 4 && count
>= size
* 2 + (address
& size
); size
*= 2) {
2857 if (address
& size
) {
2858 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, 1, buffer
);
2859 if (retval
!= ERROR_OK
)
2867 /* Write the data with as large access size as possible. */
2868 for (; size
> 0; size
/= 2) {
2869 uint32_t aligned
= count
- count
% size
;
2871 int retval
= cortex_a_write_memory_ahb(target
, address
, size
, aligned
/ size
, buffer
);
2872 if (retval
!= ERROR_OK
)
2883 static int cortex_a_handle_target_request(void *priv
)
2885 struct target
*target
= priv
;
2886 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
2889 if (!target_was_examined(target
))
2891 if (!target
->dbg_msg_enabled
)
2894 if (target
->state
== TARGET_RUNNING
) {
2897 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2898 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2900 /* check if we have data */
2901 int64_t then
= timeval_ms();
2902 while ((dscr
& DSCR_DTR_TX_FULL
) && (retval
== ERROR_OK
)) {
2903 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2904 armv7a
->debug_base
+ CPUDBG_DTRTX
, &request
);
2905 if (retval
== ERROR_OK
) {
2906 target_request(target
, request
);
2907 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2908 armv7a
->debug_base
+ CPUDBG_DSCR
, &dscr
);
2910 if (timeval_ms() > then
+ 1000) {
2911 LOG_ERROR("Timeout waiting for dtr tx full");
2921 * Cortex-A target information and configuration
2924 static int cortex_a_examine_first(struct target
*target
)
2926 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
2927 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
2928 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
2931 int retval
= ERROR_OK
;
2932 uint32_t didr
, cpuid
, dbg_osreg
;
2934 retval
= dap_dp_init(swjdp
);
2935 if (retval
!= ERROR_OK
) {
2936 LOG_ERROR("Could not initialize the debug port");
2940 /* Search for the APB-AP - it is needed for access to debug registers */
2941 retval
= dap_find_ap(swjdp
, AP_TYPE_APB_AP
, &armv7a
->debug_ap
);
2942 if (retval
!= ERROR_OK
) {
2943 LOG_ERROR("Could not find APB-AP for debug access");
2947 retval
= mem_ap_init(armv7a
->debug_ap
);
2948 if (retval
!= ERROR_OK
) {
2949 LOG_ERROR("Could not initialize the APB-AP");
2953 armv7a
->debug_ap
->memaccess_tck
= 80;
2955 /* Search for the AHB-AB.
2956 * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
2957 * can access system memory. */
2958 armv7a
->memory_ap_available
= false;
2959 retval
= dap_find_ap(swjdp
, AP_TYPE_AHB_AP
, &armv7a
->memory_ap
);
2960 if (retval
== ERROR_OK
) {
2961 retval
= mem_ap_init(armv7a
->memory_ap
);
2962 if (retval
== ERROR_OK
)
2963 armv7a
->memory_ap_available
= true;
2965 if (retval
!= ERROR_OK
) {
2966 /* AHB-AP not found or unavailable - use the CPU */
2967 LOG_DEBUG("No AHB-AP available for memory access");
2970 if (!target
->dbgbase_set
) {
2972 /* Get ROM Table base */
2974 int32_t coreidx
= target
->coreid
;
2975 LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
2977 retval
= dap_get_debugbase(armv7a
->debug_ap
, &dbgbase
, &apid
);
2978 if (retval
!= ERROR_OK
)
2980 /* Lookup 0x15 -- Processor DAP */
2981 retval
= dap_lookup_cs_component(armv7a
->debug_ap
, dbgbase
, 0x15,
2982 &armv7a
->debug_base
, &coreidx
);
2983 if (retval
!= ERROR_OK
) {
2984 LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
2988 LOG_DEBUG("Detected core %" PRId32
" dbgbase: %08" PRIx32
,
2989 target
->coreid
, armv7a
->debug_base
);
2991 armv7a
->debug_base
= target
->dbgbase
;
2993 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
2994 armv7a
->debug_base
+ CPUDBG_DIDR
, &didr
);
2995 if (retval
!= ERROR_OK
) {
2996 LOG_DEBUG("Examine %s failed", "DIDR");
3000 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3001 armv7a
->debug_base
+ CPUDBG_CPUID
, &cpuid
);
3002 if (retval
!= ERROR_OK
) {
3003 LOG_DEBUG("Examine %s failed", "CPUID");
3007 LOG_DEBUG("didr = 0x%08" PRIx32
, didr
);
3008 LOG_DEBUG("cpuid = 0x%08" PRIx32
, cpuid
);
3010 cortex_a
->didr
= didr
;
3011 cortex_a
->cpuid
= cpuid
;
3013 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3014 armv7a
->debug_base
+ CPUDBG_PRSR
, &dbg_osreg
);
3015 if (retval
!= ERROR_OK
)
3017 LOG_DEBUG("target->coreid %" PRId32
" DBGPRSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3019 if ((dbg_osreg
& PRSR_POWERUP_STATUS
) == 0) {
3020 LOG_ERROR("target->coreid %" PRId32
" powered down!", target
->coreid
);
3021 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
3022 return ERROR_TARGET_INIT_FAILED
;
3025 if (dbg_osreg
& PRSR_STICKY_RESET_STATUS
)
3026 LOG_DEBUG("target->coreid %" PRId32
" was reset!", target
->coreid
);
3028 /* Read DBGOSLSR and check if OSLK is implemented */
3029 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3030 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
3031 if (retval
!= ERROR_OK
)
3033 LOG_DEBUG("target->coreid %" PRId32
" DBGOSLSR 0x%" PRIx32
, target
->coreid
, dbg_osreg
);
3035 /* check if OS Lock is implemented */
3036 if ((dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM0
|| (dbg_osreg
& OSLSR_OSLM
) == OSLSR_OSLM1
) {
3037 /* check if OS Lock is set */
3038 if (dbg_osreg
& OSLSR_OSLK
) {
3039 LOG_DEBUG("target->coreid %" PRId32
" OSLock set! Trying to unlock", target
->coreid
);
3041 retval
= mem_ap_write_atomic_u32(armv7a
->debug_ap
,
3042 armv7a
->debug_base
+ CPUDBG_OSLAR
,
3044 if (retval
== ERROR_OK
)
3045 retval
= mem_ap_read_atomic_u32(armv7a
->debug_ap
,
3046 armv7a
->debug_base
+ CPUDBG_OSLSR
, &dbg_osreg
);
3048 /* if we fail to access the register or cannot reset the OSLK bit, bail out */
3049 if (retval
!= ERROR_OK
|| (dbg_osreg
& OSLSR_OSLK
) != 0) {
3050 LOG_ERROR("target->coreid %" PRId32
" OSLock sticky, core not powered?",
3052 target
->state
= TARGET_UNKNOWN
; /* TARGET_NO_POWER? */
3053 return ERROR_TARGET_INIT_FAILED
;
3058 armv7a
->arm
.core_type
= ARM_MODE_MON
;
3060 /* Avoid recreating the registers cache */
3061 if (!target_was_examined(target
)) {
3062 retval
= cortex_a_dpm_setup(cortex_a
, didr
);
3063 if (retval
!= ERROR_OK
)
3067 /* Setup Breakpoint Register Pairs */
3068 cortex_a
->brp_num
= ((didr
>> 24) & 0x0F) + 1;
3069 cortex_a
->brp_num_context
= ((didr
>> 20) & 0x0F) + 1;
3070 cortex_a
->brp_num_available
= cortex_a
->brp_num
;
3071 free(cortex_a
->brp_list
);
3072 cortex_a
->brp_list
= calloc(cortex_a
->brp_num
, sizeof(struct cortex_a_brp
));
3073 /* cortex_a->brb_enabled = ????; */
3074 for (i
= 0; i
< cortex_a
->brp_num
; i
++) {
3075 cortex_a
->brp_list
[i
].used
= 0;
3076 if (i
< (cortex_a
->brp_num
-cortex_a
->brp_num_context
))
3077 cortex_a
->brp_list
[i
].type
= BRP_NORMAL
;
3079 cortex_a
->brp_list
[i
].type
= BRP_CONTEXT
;
3080 cortex_a
->brp_list
[i
].value
= 0;
3081 cortex_a
->brp_list
[i
].control
= 0;
3082 cortex_a
->brp_list
[i
].BRPn
= i
;
3085 LOG_DEBUG("Configured %i hw breakpoints", cortex_a
->brp_num
);
3087 /* select debug_ap as default */
3088 swjdp
->apsel
= armv7a
->debug_ap
->ap_num
;
3090 target_set_examined(target
);
3094 static int cortex_a_examine(struct target
*target
)
3096 int retval
= ERROR_OK
;
3098 /* Reestablish communication after target reset */
3099 retval
= cortex_a_examine_first(target
);
3101 /* Configure core debug access */
3102 if (retval
== ERROR_OK
)
3103 retval
= cortex_a_init_debug_access(target
);
3109 * Cortex-A target creation and initialization
3112 static int cortex_a_init_target(struct command_context
*cmd_ctx
,
3113 struct target
*target
)
3115 /* examine_first() does a bunch of this */
3116 arm_semihosting_init(target
);
3120 static int cortex_a_init_arch_info(struct target
*target
,
3121 struct cortex_a_common
*cortex_a
, struct jtag_tap
*tap
)
3123 struct armv7a_common
*armv7a
= &cortex_a
->armv7a_common
;
3125 /* Setup struct cortex_a_common */
3126 cortex_a
->common_magic
= CORTEX_A_COMMON_MAGIC
;
3128 /* tap has no dap initialized */
3130 tap
->dap
= dap_init();
3132 /* Leave (only) generic DAP stuff for debugport_init() */
3133 tap
->dap
->tap
= tap
;
3136 armv7a
->arm
.dap
= tap
->dap
;
3138 cortex_a
->fast_reg_read
= 0;
3140 /* register arch-specific functions */
3141 armv7a
->examine_debug_reason
= NULL
;
3143 armv7a
->post_debug_entry
= cortex_a_post_debug_entry
;
3145 armv7a
->pre_restore_context
= NULL
;
3147 armv7a
->armv7a_mmu
.read_physical_memory
= cortex_a_read_phys_memory
;
3150 /* arm7_9->handle_target_request = cortex_a_handle_target_request; */
3152 /* REVISIT v7a setup should be in a v7a-specific routine */
3153 armv7a_init_arch_info(target
, armv7a
);
3154 target_register_timer_callback(cortex_a_handle_target_request
, 1, 1, target
);
3159 static int cortex_a_target_create(struct target
*target
, Jim_Interp
*interp
)
3161 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3163 cortex_a
->armv7a_common
.is_armv7r
= false;
3165 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3168 static int cortex_r4_target_create(struct target
*target
, Jim_Interp
*interp
)
3170 struct cortex_a_common
*cortex_a
= calloc(1, sizeof(struct cortex_a_common
));
3172 cortex_a
->armv7a_common
.is_armv7r
= true;
3174 return cortex_a_init_arch_info(target
, cortex_a
, target
->tap
);
3177 static void cortex_a_deinit_target(struct target
*target
)
3179 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3180 struct arm_dpm
*dpm
= &cortex_a
->armv7a_common
.dpm
;
3182 free(cortex_a
->brp_list
);
3188 static int cortex_a_mmu(struct target
*target
, int *enabled
)
3190 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3192 if (target
->state
!= TARGET_HALTED
) {
3193 LOG_ERROR("%s: target not halted", __func__
);
3194 return ERROR_TARGET_INVALID
;
3197 if (armv7a
->is_armv7r
)
3200 *enabled
= target_to_cortex_a(target
)->armv7a_common
.armv7a_mmu
.mmu_enabled
;
3205 static int cortex_a_virt2phys(struct target
*target
,
3206 target_addr_t virt
, target_addr_t
*phys
)
3208 int retval
= ERROR_FAIL
;
3209 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3210 struct adiv5_dap
*swjdp
= armv7a
->arm
.dap
;
3211 uint8_t apsel
= swjdp
->apsel
;
3212 if (armv7a
->memory_ap_available
&& (apsel
== armv7a
->memory_ap
->ap_num
)) {
3214 retval
= armv7a_mmu_translate_va(target
,
3216 if (retval
!= ERROR_OK
)
3219 } else {/* use this method if armv7a->memory_ap not selected
3220 * mmu must be enable in order to get a correct translation */
3221 retval
= cortex_a_mmu_modify(target
, 1);
3222 if (retval
!= ERROR_OK
)
3224 retval
= armv7a_mmu_translate_va_pa(target
, (uint32_t)virt
,
3225 (uint32_t *)phys
, 1);
3231 COMMAND_HANDLER(cortex_a_handle_cache_info_command
)
3233 struct target
*target
= get_current_target(CMD_CTX
);
3234 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
3236 return armv7a_handle_cache_info_command(CMD_CTX
,
3237 &armv7a
->armv7a_mmu
.armv7a_cache
);
3241 COMMAND_HANDLER(cortex_a_handle_dbginit_command
)
3243 struct target
*target
= get_current_target(CMD_CTX
);
3244 if (!target_was_examined(target
)) {
3245 LOG_ERROR("target not examined yet");
3249 return cortex_a_init_debug_access(target
);
3251 COMMAND_HANDLER(cortex_a_handle_smp_off_command
)
3253 struct target
*target
= get_current_target(CMD_CTX
);
3254 /* check target is an smp target */
3255 struct target_list
*head
;
3256 struct target
*curr
;
3257 head
= target
->head
;
3259 if (head
!= (struct target_list
*)NULL
) {
3260 while (head
!= (struct target_list
*)NULL
) {
3261 curr
= head
->target
;
3265 /* fixes the target display to the debugger */
3266 target
->gdb_service
->target
= target
;
3271 COMMAND_HANDLER(cortex_a_handle_smp_on_command
)
3273 struct target
*target
= get_current_target(CMD_CTX
);
3274 struct target_list
*head
;
3275 struct target
*curr
;
3276 head
= target
->head
;
3277 if (head
!= (struct target_list
*)NULL
) {
3279 while (head
!= (struct target_list
*)NULL
) {
3280 curr
= head
->target
;
3288 COMMAND_HANDLER(cortex_a_handle_smp_gdb_command
)
3290 struct target
*target
= get_current_target(CMD_CTX
);
3291 int retval
= ERROR_OK
;
3292 struct target_list
*head
;
3293 head
= target
->head
;
3294 if (head
!= (struct target_list
*)NULL
) {
3295 if (CMD_ARGC
== 1) {
3297 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
3298 if (ERROR_OK
!= retval
)
3300 target
->gdb_service
->core
[1] = coreid
;
3303 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
3304 , target
->gdb_service
->core
[1]);
3309 COMMAND_HANDLER(handle_cortex_a_mask_interrupts_command
)
3311 struct target
*target
= get_current_target(CMD_CTX
);
3312 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3314 static const Jim_Nvp nvp_maskisr_modes
[] = {
3315 { .name
= "off", .value
= CORTEX_A_ISRMASK_OFF
},
3316 { .name
= "on", .value
= CORTEX_A_ISRMASK_ON
},
3317 { .name
= NULL
, .value
= -1 },
3322 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
3323 if (n
->name
== NULL
) {
3324 LOG_ERROR("Unknown parameter: %s - should be off or on", CMD_ARGV
[0]);
3325 return ERROR_COMMAND_SYNTAX_ERROR
;
3328 cortex_a
->isrmasking_mode
= n
->value
;
3331 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_a
->isrmasking_mode
);
3332 command_print(CMD_CTX
, "cortex_a interrupt mask %s", n
->name
);
3337 COMMAND_HANDLER(handle_cortex_a_dacrfixup_command
)
3339 struct target
*target
= get_current_target(CMD_CTX
);
3340 struct cortex_a_common
*cortex_a
= target_to_cortex_a(target
);
3342 static const Jim_Nvp nvp_dacrfixup_modes
[] = {
3343 { .name
= "off", .value
= CORTEX_A_DACRFIXUP_OFF
},
3344 { .name
= "on", .value
= CORTEX_A_DACRFIXUP_ON
},
3345 { .name
= NULL
, .value
= -1 },
3350 n
= Jim_Nvp_name2value_simple(nvp_dacrfixup_modes
, CMD_ARGV
[0]);
3351 if (n
->name
== NULL
)
3352 return ERROR_COMMAND_SYNTAX_ERROR
;
3353 cortex_a
->dacrfixup_mode
= n
->value
;
3357 n
= Jim_Nvp_value2name_simple(nvp_dacrfixup_modes
, cortex_a
->dacrfixup_mode
);
3358 command_print(CMD_CTX
, "cortex_a domain access control fixup %s", n
->name
);
3363 static const struct command_registration cortex_a_exec_command_handlers
[] = {
3365 .name
= "cache_info",
3366 .handler
= cortex_a_handle_cache_info_command
,
3367 .mode
= COMMAND_EXEC
,
3368 .help
= "display information about target caches",
3373 .handler
= cortex_a_handle_dbginit_command
,
3374 .mode
= COMMAND_EXEC
,
3375 .help
= "Initialize core debug",
3378 { .name
= "smp_off",
3379 .handler
= cortex_a_handle_smp_off_command
,
3380 .mode
= COMMAND_EXEC
,
3381 .help
= "Stop smp handling",
3385 .handler
= cortex_a_handle_smp_on_command
,
3386 .mode
= COMMAND_EXEC
,
3387 .help
= "Restart smp handling",
3392 .handler
= cortex_a_handle_smp_gdb_command
,
3393 .mode
= COMMAND_EXEC
,
3394 .help
= "display/fix current core played to gdb",
3399 .handler
= handle_cortex_a_mask_interrupts_command
,
3400 .mode
= COMMAND_ANY
,
3401 .help
= "mask cortex_a interrupts",
3402 .usage
= "['on'|'off']",
3405 .name
= "dacrfixup",
3406 .handler
= handle_cortex_a_dacrfixup_command
,
3407 .mode
= COMMAND_EXEC
,
3408 .help
= "set domain access control (DACR) to all-manager "
3410 .usage
= "['on'|'off']",
3413 COMMAND_REGISTRATION_DONE
3415 static const struct command_registration cortex_a_command_handlers
[] = {
3417 .chain
= arm_command_handlers
,
3420 .chain
= armv7a_command_handlers
,
3424 .mode
= COMMAND_ANY
,
3425 .help
= "Cortex-A command group",
3427 .chain
= cortex_a_exec_command_handlers
,
3429 COMMAND_REGISTRATION_DONE
3432 struct target_type cortexa_target
= {
3434 .deprecated_name
= "cortex_a8",
3436 .poll
= cortex_a_poll
,
3437 .arch_state
= armv7a_arch_state
,
3439 .halt
= cortex_a_halt
,
3440 .resume
= cortex_a_resume
,
3441 .step
= cortex_a_step
,
3443 .assert_reset
= cortex_a_assert_reset
,
3444 .deassert_reset
= cortex_a_deassert_reset
,
3446 /* REVISIT allow exporting VFP3 registers ... */
3447 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3449 .read_memory
= cortex_a_read_memory
,
3450 .write_memory
= cortex_a_write_memory
,
3452 .read_buffer
= cortex_a_read_buffer
,
3453 .write_buffer
= cortex_a_write_buffer
,
3455 .checksum_memory
= arm_checksum_memory
,
3456 .blank_check_memory
= arm_blank_check_memory
,
3458 .run_algorithm
= armv4_5_run_algorithm
,
3460 .add_breakpoint
= cortex_a_add_breakpoint
,
3461 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3462 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3463 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3464 .add_watchpoint
= NULL
,
3465 .remove_watchpoint
= NULL
,
3467 .commands
= cortex_a_command_handlers
,
3468 .target_create
= cortex_a_target_create
,
3469 .init_target
= cortex_a_init_target
,
3470 .examine
= cortex_a_examine
,
3471 .deinit_target
= cortex_a_deinit_target
,
3473 .read_phys_memory
= cortex_a_read_phys_memory
,
3474 .write_phys_memory
= cortex_a_write_phys_memory
,
3475 .mmu
= cortex_a_mmu
,
3476 .virt2phys
= cortex_a_virt2phys
,
3479 static const struct command_registration cortex_r4_exec_command_handlers
[] = {
3481 .name
= "cache_info",
3482 .handler
= cortex_a_handle_cache_info_command
,
3483 .mode
= COMMAND_EXEC
,
3484 .help
= "display information about target caches",
3489 .handler
= cortex_a_handle_dbginit_command
,
3490 .mode
= COMMAND_EXEC
,
3491 .help
= "Initialize core debug",
3496 .handler
= handle_cortex_a_mask_interrupts_command
,
3497 .mode
= COMMAND_EXEC
,
3498 .help
= "mask cortex_r4 interrupts",
3499 .usage
= "['on'|'off']",
3502 COMMAND_REGISTRATION_DONE
3504 static const struct command_registration cortex_r4_command_handlers
[] = {
3506 .chain
= arm_command_handlers
,
3509 .chain
= armv7a_command_handlers
,
3512 .name
= "cortex_r4",
3513 .mode
= COMMAND_ANY
,
3514 .help
= "Cortex-R4 command group",
3516 .chain
= cortex_r4_exec_command_handlers
,
3518 COMMAND_REGISTRATION_DONE
3521 struct target_type cortexr4_target
= {
3522 .name
= "cortex_r4",
3524 .poll
= cortex_a_poll
,
3525 .arch_state
= armv7a_arch_state
,
3527 .halt
= cortex_a_halt
,
3528 .resume
= cortex_a_resume
,
3529 .step
= cortex_a_step
,
3531 .assert_reset
= cortex_a_assert_reset
,
3532 .deassert_reset
= cortex_a_deassert_reset
,
3534 /* REVISIT allow exporting VFP3 registers ... */
3535 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
3537 .read_memory
= cortex_a_read_phys_memory
,
3538 .write_memory
= cortex_a_write_phys_memory
,
3540 .checksum_memory
= arm_checksum_memory
,
3541 .blank_check_memory
= arm_blank_check_memory
,
3543 .run_algorithm
= armv4_5_run_algorithm
,
3545 .add_breakpoint
= cortex_a_add_breakpoint
,
3546 .add_context_breakpoint
= cortex_a_add_context_breakpoint
,
3547 .add_hybrid_breakpoint
= cortex_a_add_hybrid_breakpoint
,
3548 .remove_breakpoint
= cortex_a_remove_breakpoint
,
3549 .add_watchpoint
= NULL
,
3550 .remove_watchpoint
= NULL
,
3552 .commands
= cortex_r4_command_handlers
,
3553 .target_create
= cortex_r4_target_create
,
3554 .init_target
= cortex_a_init_target
,
3555 .examine
= cortex_a_examine
,
3556 .deinit_target
= cortex_a_deinit_target
,