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flash/nor/rp2040: check target halted before flash operation
[openocd.git] / src / target / nds32_disassembler.c
blobeebbfe109dc65b2a4169aac155a457df7730915c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2013 Andes Technology *
5 * Hsiangkai Wang <hkwang@andestech.com> *
6 ***************************************************************************/
7
8 #ifdef HAVE_CONFIG_H
9 #include "config.h"
10 #endif
11
12 #include <helper/log.h>
13 #include <target/target.h>
14 #include "nds32_disassembler.h"
15
16 static const int enable4_bits[] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4};
17
18 int nds32_read_opcode(struct nds32 *nds32, uint32_t address, uint32_t *value)
19 {
20 struct target *target = nds32->target;
21 uint8_t value_buf[4];
22
23 if (!target_was_examined(target)) {
24 LOG_ERROR("Target not examined yet");
25 return ERROR_FAIL;
26 }
27
28 int retval = target_read_buffer(target, address, 4, value_buf);
29
30 if (retval == ERROR_OK) {
31 /* instructions are always big-endian */
32 *value = be_to_h_u32(value_buf);
33
34 LOG_DEBUG("address: 0x%8.8" PRIx32 ", value: 0x%8.8" PRIx32 "",
35 address,
36 *value);
37 } else {
38 *value = 0x0;
39 LOG_DEBUG("address: 0x%8.8" PRIx32 " failed",
40 address);
41 }
42
43 return retval;
44 }
45
46 static int nds32_parse_type_0(uint32_t opcode, int32_t *imm)
47 {
48 *imm = opcode & 0x1FFFFFF;
49
50 return ERROR_OK;
51 }
52
53 static int nds32_parse_type_1(uint32_t opcode, uint8_t *rt, int32_t *imm)
54 {
55 *rt = (opcode >> 20) & 0x1F;
56 *imm = opcode & 0xFFFFF;
57
58 return ERROR_OK;
59 }
60
61 static int nds32_parse_type_2(uint32_t opcode, uint8_t *rt, uint8_t *ra, int32_t *imm)
62 {
63 *rt = (opcode >> 20) & 0x1F;
64 *ra = (opcode >> 15) & 0x1F;
65 *imm = opcode & 0x7FFF;
66
67 return ERROR_OK;
68 }
69
70 static int nds32_parse_type_3(uint32_t opcode, uint8_t *rt, uint8_t *ra,
71 uint8_t *rb, int32_t *imm)
72 {
73 *rt = (opcode >> 20) & 0x1F;
74 *ra = (opcode >> 15) & 0x1F;
75 *rb = (opcode >> 10) & 0x1F;
76 *imm = opcode & 0x3FF;
77
78 return ERROR_OK;
79 }
80
81 static int nds32_parse_type_4(uint32_t opcode, uint8_t *rt, uint8_t *ra,
82 uint8_t *rb, uint8_t *rd, uint8_t *sub_opc)
83 {
84 *rt = (opcode >> 20) & 0x1F;
85 *ra = (opcode >> 15) & 0x1F;
86 *rb = (opcode >> 10) & 0x1F;
87 *rd = (opcode >> 5) & 0x1F;
88 *sub_opc = opcode & 0x1F;
89
90 return ERROR_OK;
91 }
92
93 /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
94 static int nds32_parse_group_0_insn(struct nds32 *nds32, uint32_t opcode,
95 uint32_t address,
96 struct nds32_instruction *instruction)
97 {
98 uint8_t opc_6;
99
100 opc_6 = instruction->info.opc_6;
101
102 switch (opc_6 & 0x7) {
103 case 0: /* LBI */
104 nds32_parse_type_2(opcode, &(instruction->info.rt),
105 &(instruction->info.ra), &(instruction->info.imm));
106 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
107 instruction->type = NDS32_INSN_LOAD_STORE;
108 nds32_get_mapped_reg(nds32, instruction->info.ra,
109 &(instruction->access_start));
110 instruction->access_start += instruction->info.imm;
111 instruction->access_end = instruction->access_start + 1;
112 snprintf(instruction->text,
113 128,
114 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
115 "\tLBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
116 address,
117 opcode, instruction->info.rt, instruction->info.ra,
118 instruction->info.imm);
119 break;
120 case 1: /* LHI */
121 nds32_parse_type_2(opcode, &(instruction->info.rt),
122 &(instruction->info.ra), &(instruction->info.imm));
123 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
124 instruction->type = NDS32_INSN_LOAD_STORE;
125 nds32_get_mapped_reg(nds32, instruction->info.ra,
126 &(instruction->access_start));
127 instruction->access_start += instruction->info.imm;
128 instruction->access_end = instruction->access_start + 2;
129 snprintf(instruction->text,
130 128,
131 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
132 "\tLHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
133 address,
134 opcode, instruction->info.rt, instruction->info.ra,
135 instruction->info.imm);
136 break;
137 case 2: /* LWI */
138 nds32_parse_type_2(opcode, &(instruction->info.rt),
139 &(instruction->info.ra), &(instruction->info.imm));
140 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
141 instruction->type = NDS32_INSN_LOAD_STORE;
142 nds32_get_mapped_reg(nds32, instruction->info.ra,
143 &(instruction->access_start));
144 instruction->access_start += instruction->info.imm;
145 instruction->access_end = instruction->access_start + 4;
146 snprintf(instruction->text,
147 128,
148 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
149 "\tLWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
150 address,
151 opcode, instruction->info.rt, instruction->info.ra,
152 instruction->info.imm);
153 break;
154 case 4: /* LBI.bi */
155 nds32_parse_type_2(opcode, &(instruction->info.rt),
156 &(instruction->info.ra), &(instruction->info.imm));
157 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
158 instruction->type = NDS32_INSN_LOAD_STORE;
159 nds32_get_mapped_reg(nds32, instruction->info.ra,
160 &(instruction->access_start));
161 instruction->access_end = instruction->access_start + 1;
162 snprintf(instruction->text,
163 128,
164 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
165 "\tLBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
166 address,
167 opcode, instruction->info.rt, instruction->info.ra,
168 instruction->info.imm);
169 break;
170 case 5: /* LHI.bi */
171 nds32_parse_type_2(opcode, &(instruction->info.rt),
172 &(instruction->info.ra), &(instruction->info.imm));
173 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
174 instruction->type = NDS32_INSN_LOAD_STORE;
175 nds32_get_mapped_reg(nds32, instruction->info.ra,
176 &(instruction->access_start));
177 instruction->access_end = instruction->access_start + 2;
178 snprintf(instruction->text,
179 128,
180 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
181 "\tLHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
182 address,
183 opcode, instruction->info.rt, instruction->info.ra,
184 instruction->info.imm);
185 break;
186 case 6: /* LWI.bi */
187 nds32_parse_type_2(opcode, &(instruction->info.rt),
188 &(instruction->info.ra), &(instruction->info.imm));
189 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
190 instruction->type = NDS32_INSN_LOAD_STORE;
191 nds32_get_mapped_reg(nds32, instruction->info.ra,
192 &(instruction->access_start));
193 instruction->access_end = instruction->access_start + 4;
194 snprintf(instruction->text,
195 128,
196 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
197 "\tLWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32 "",
198 address,
199 opcode, instruction->info.rt, instruction->info.ra,
200 instruction->info.imm);
201 break;
202 default:
203 snprintf(instruction->text,
204 128,
205 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
206 address,
207 opcode);
208 return ERROR_FAIL;
209 }
210
211 return ERROR_OK;
212 }
213
214 static int nds32_parse_group_1_insn(struct nds32 *nds32, uint32_t opcode,
215 uint32_t address, struct nds32_instruction *instruction)
216 {
217 uint8_t opc_6;
218
219 opc_6 = instruction->info.opc_6;
220
221 switch (opc_6 & 0x7) {
222 case 0: /* SBI */
223 nds32_parse_type_2(opcode, &(instruction->info.rt),
224 &(instruction->info.ra), &(instruction->info.imm));
225 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
226 instruction->type = NDS32_INSN_LOAD_STORE;
227 nds32_get_mapped_reg(nds32, instruction->info.ra,
228 &(instruction->access_start));
229 instruction->access_start += instruction->info.imm;
230 instruction->access_end = instruction->access_start + 1;
231 snprintf(instruction->text,
232 128,
233 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
234 "\tSBI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
235 address,
236 opcode, instruction->info.rt, instruction->info.ra,
237 instruction->info.imm);
238 break;
239 case 1: /* SHI */
240 nds32_parse_type_2(opcode, &(instruction->info.rt),
241 &(instruction->info.ra), &(instruction->info.imm));
242 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
243 instruction->type = NDS32_INSN_LOAD_STORE;
244 nds32_get_mapped_reg(nds32, instruction->info.ra,
245 &(instruction->access_start));
246 instruction->access_start += instruction->info.imm;
247 instruction->access_end = instruction->access_start + 2;
248 snprintf(instruction->text,
249 128,
250 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
251 "\tSHI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
252 address,
253 opcode, instruction->info.rt, instruction->info.ra,
254 instruction->info.imm);
255 break;
256 case 2: /* SWI */
257 nds32_parse_type_2(opcode, &(instruction->info.rt),
258 &(instruction->info.ra), &(instruction->info.imm));
259 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
260 instruction->type = NDS32_INSN_LOAD_STORE;
261 nds32_get_mapped_reg(nds32, instruction->info.ra,
262 &(instruction->access_start));
263 instruction->access_start += instruction->info.imm;
264 instruction->access_end = instruction->access_start + 4;
265 snprintf(instruction->text,
266 128,
267 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
268 "\tSWI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
269 address,
270 opcode, instruction->info.rt, instruction->info.ra,
271 instruction->info.imm);
272 break;
273 case 4: /* SBI.bi */
274 nds32_parse_type_2(opcode, &(instruction->info.rt),
275 &(instruction->info.ra), &(instruction->info.imm));
276 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
277 instruction->type = NDS32_INSN_LOAD_STORE;
278 nds32_get_mapped_reg(nds32, instruction->info.ra,
279 &(instruction->access_start));
280 instruction->access_end = instruction->access_start + 1;
281 snprintf(instruction->text,
282 128,
283 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
284 "\tSBI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
285 address,
286 opcode, instruction->info.rt, instruction->info.ra,
287 instruction->info.imm);
288 break;
289 case 5: /* SHI.bi */
290 nds32_parse_type_2(opcode, &(instruction->info.rt),
291 &(instruction->info.ra), &(instruction->info.imm));
292 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
293 instruction->type = NDS32_INSN_LOAD_STORE;
294 nds32_get_mapped_reg(nds32, instruction->info.ra,
295 &(instruction->access_start));
296 instruction->access_end = instruction->access_start + 2;
297 snprintf(instruction->text,
298 128,
299 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
300 "\tSHI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
301 address,
302 opcode, instruction->info.rt, instruction->info.ra,
303 instruction->info.imm);
304 break;
305 case 6: /* SWI.bi */
306 nds32_parse_type_2(opcode, &(instruction->info.rt),
307 &(instruction->info.ra), &(instruction->info.imm));
308 instruction->info.imm = (instruction->info.imm << 17) >> 15; /* sign-extend */
309 instruction->type = NDS32_INSN_LOAD_STORE;
310 nds32_get_mapped_reg(nds32, instruction->info.ra,
311 &(instruction->access_start));
312 instruction->access_end = instruction->access_start + 4;
313 snprintf(instruction->text,
314 128,
315 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
316 "\tSWI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
317 address,
318 opcode, instruction->info.rt, instruction->info.ra,
319 instruction->info.imm);
320 break;
321 default:
322 snprintf(instruction->text,
323 128,
324 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
325 address,
326 opcode);
327 return ERROR_FAIL;
328 }
329
330 return ERROR_OK;
331 }
332
333 static int nds32_parse_group_2_insn(struct nds32 *nds32, uint32_t opcode,
334 uint32_t address, struct nds32_instruction *instruction)
335 {
336 uint8_t opc_6;
337
338 opc_6 = instruction->info.opc_6;
339
340 switch (opc_6 & 0x7) {
341 case 0: /* LBSI */
342 nds32_parse_type_2(opcode, &(instruction->info.rt),
343 &(instruction->info.ra), &(instruction->info.imm));
344 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
345 instruction->type = NDS32_INSN_LOAD_STORE;
346 nds32_get_mapped_reg(nds32, instruction->info.ra,
347 &(instruction->access_start));
348 instruction->access_start += instruction->info.imm;
349 instruction->access_end = instruction->access_start + 1;
350 snprintf(instruction->text,
351 128,
352 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
353 "\tLBSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
354 address,
355 opcode, instruction->info.rt, instruction->info.ra,
356 instruction->info.imm);
357 break;
358 case 1: /* LHSI */
359 nds32_parse_type_2(opcode, &(instruction->info.rt),
360 &(instruction->info.ra), &(instruction->info.imm));
361 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
362 instruction->type = NDS32_INSN_LOAD_STORE;
363 nds32_get_mapped_reg(nds32, instruction->info.ra,
364 &(instruction->access_start));
365 instruction->access_start += instruction->info.imm;
366 instruction->access_end = instruction->access_start + 2;
367 snprintf(instruction->text,
368 128,
369 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
370 "\tLHSI\t$r%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
371 address,
372 opcode, instruction->info.rt, instruction->info.ra,
373 instruction->info.imm);
374 break;
375 case 3: { /* DPREFI */
376 uint8_t sub_type;
377 nds32_parse_type_2(opcode, &sub_type, &(instruction->info.ra),
378 &(instruction->info.imm));
379 instruction->info.sub_opc = sub_type & 0xF;
380 instruction->type = NDS32_INSN_MISC;
381 if (sub_type & 0x10) { /* DPREFI.d */
382 /* sign-extend */
383 instruction->info.imm = (instruction->info.imm << 17) >> 14;
384 snprintf(instruction->text,
385 128,
386 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
387 "\tDPREFI.d\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
388 address,
389 opcode, instruction->info.sub_opc,
390 instruction->info.ra, instruction->info.imm);
391 } else { /* DPREFI.w */
392 /* sign-extend */
393 instruction->info.imm = (instruction->info.imm << 17) >> 15;
394 snprintf(instruction->text,
395 128,
396 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
397 "\tDPREFI.w\t%" PRIu8 ",[$r%" PRIu8 "+#%" PRId32 "]",
398 address,
399 opcode, instruction->info.sub_opc,
400 instruction->info.ra, instruction->info.imm);
401 }
402 }
403 break;
404 case 4: /* LBSI.bi */
405 nds32_parse_type_2(opcode, &(instruction->info.rt),
406 &(instruction->info.ra), &(instruction->info.imm));
407 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
408 instruction->type = NDS32_INSN_LOAD_STORE;
409 nds32_get_mapped_reg(nds32, instruction->info.ra,
410 &(instruction->access_start));
411 instruction->access_end = instruction->access_start + 1;
412 snprintf(instruction->text,
413 128,
414 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
415 "\tLBSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
416 address,
417 opcode, instruction->info.rt, instruction->info.ra,
418 instruction->info.imm);
419 break;
420 case 5: /* LHSI.bi */
421 nds32_parse_type_2(opcode, &(instruction->info.rt),
422 &(instruction->info.ra), &(instruction->info.imm));
423 instruction->info.imm = (instruction->info.imm << 17) >> 16; /* sign-extend */
424 instruction->type = NDS32_INSN_LOAD_STORE;
425 nds32_get_mapped_reg(nds32, instruction->info.ra,
426 &(instruction->access_start));
427 instruction->access_end = instruction->access_start + 2;
428 snprintf(instruction->text,
429 128,
430 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
431 "\tLHSI.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
432 address,
433 opcode, instruction->info.rt, instruction->info.ra,
434 instruction->info.imm);
435 break;
436 case 6: /* LBGP */
437 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
438 instruction->type = NDS32_INSN_LOAD_STORE;
439 if ((instruction->info.imm >> 19) & 0x1) { /* LBSI.gp */
440 instruction->info.imm = (instruction->info.imm << 13) >> 13;
441 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
442 instruction->access_start += instruction->info.imm;
443 instruction->access_end = instruction->access_start + 1;
444 snprintf(instruction->text,
445 128,
446 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
447 "\tLBSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
448 address,
449 opcode, instruction->info.rt, instruction->info.imm);
450 } else { /* LBI.gp */
451 instruction->info.imm = (instruction->info.imm << 13) >> 13;
452 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
453 instruction->access_start += instruction->info.imm;
454 instruction->access_end = instruction->access_start + 1;
455 snprintf(instruction->text,
456 128,
457 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
458 "\tLBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
459 address,
460 opcode, instruction->info.rt, instruction->info.imm);
461 }
462 break;
463 default:
464 snprintf(instruction->text,
465 128,
466 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
467 address,
468 opcode);
469 return ERROR_FAIL;
470 }
471
472 return ERROR_OK;
473 }
474
475 static int nds32_parse_mem(struct nds32 *nds32, uint32_t opcode, uint32_t address,
476 struct nds32_instruction *instruction)
477 {
478 uint32_t sub_opcode = opcode & 0x3F;
479 uint32_t val_ra, val_rb;
480 switch (sub_opcode >> 3) {
481 case 0:
482 switch (sub_opcode & 0x7) {
483 case 0: /* LB */
484 nds32_parse_type_3(opcode, &(instruction->info.rt),
485 &(instruction->info.ra),
486 &(instruction->info.rb), &(instruction->info.imm));
487 instruction->type = NDS32_INSN_LOAD_STORE;
488 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
489 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
490 instruction->access_start = val_ra +
491 (val_rb << ((instruction->info.imm >> 8) & 0x3));
492 instruction->access_end = instruction->access_start + 1;
493 snprintf(instruction->text,
494 128,
495 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
496 "\tLB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
497 address,
498 opcode, instruction->info.rt, instruction->info.ra,
499 instruction->info.rb,
500 (instruction->info.imm >> 8) & 0x3);
501 break;
502 case 1: /* LH */
503 nds32_parse_type_3(opcode, &(instruction->info.rt),
504 &(instruction->info.ra),
505 &(instruction->info.rb), &(instruction->info.imm));
506 instruction->type = NDS32_INSN_LOAD_STORE;
507 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
508 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
509 instruction->access_start = val_ra +
510 (val_rb << ((instruction->info.imm >> 8) & 0x3));
511 instruction->access_end = instruction->access_start + 2;
512 snprintf(instruction->text,
513 128,
514 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
515 "\tLH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
516 address,
517 opcode, instruction->info.rt, instruction->info.ra,
518 instruction->info.rb,
519 (instruction->info.imm >> 8) & 0x3);
520 break;
521 case 2: /* LW */
522 nds32_parse_type_3(opcode, &(instruction->info.rt),
523 &(instruction->info.ra),
524 &(instruction->info.rb), &(instruction->info.imm));
525 instruction->type = NDS32_INSN_LOAD_STORE;
526 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
527 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
528 instruction->access_start = val_ra +
529 (val_rb << ((instruction->info.imm >> 8) & 0x3));
530 instruction->access_end = instruction->access_start + 4;
531 snprintf(instruction->text,
532 128,
533 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
534 "\tLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
535 address,
536 opcode, instruction->info.rt, instruction->info.ra,
537 instruction->info.rb,
538 (instruction->info.imm >> 8) & 0x3);
539 break;
540 case 4: /* LB.bi */
541 nds32_parse_type_3(opcode, &(instruction->info.rt),
542 &(instruction->info.ra),
543 &(instruction->info.rb), &(instruction->info.imm));
544 instruction->type = NDS32_INSN_LOAD_STORE;
545 nds32_get_mapped_reg(nds32, instruction->info.ra,
546 &(instruction->access_start));
547 instruction->access_end = instruction->access_start + 1;
548 snprintf(instruction->text,
549 128,
550 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
551 "\tLB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
552 address,
553 opcode, instruction->info.rt,
554 instruction->info.ra, instruction->info.rb,
555 (instruction->info.imm >> 8) & 0x3);
556 break;
557 case 5: /* LH.bi */
558 nds32_parse_type_3(opcode, &(instruction->info.rt),
559 &(instruction->info.ra),
560 &(instruction->info.rb), &(instruction->info.imm));
561 instruction->type = NDS32_INSN_LOAD_STORE;
562 nds32_get_mapped_reg(nds32, instruction->info.ra,
563 &(instruction->access_start));
564 instruction->access_end = instruction->access_start + 2;
565 snprintf(instruction->text,
566 128,
567 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
568 "\tLH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
569 address,
570 opcode, instruction->info.rt, instruction->info.ra,
571 instruction->info.rb,
572 (instruction->info.imm >> 8) & 0x3);
573 break;
574 case 6: /* LW.bi */
575 nds32_parse_type_3(opcode, &(instruction->info.rt),
576 &(instruction->info.ra),
577 &(instruction->info.rb), &(instruction->info.imm));
578 instruction->type = NDS32_INSN_LOAD_STORE;
579 nds32_get_mapped_reg(nds32, instruction->info.ra,
580 &(instruction->access_start));
581 instruction->access_end = instruction->access_start + 4;
582 snprintf(instruction->text,
583 128,
584 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
585 "\tLW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
586 address,
587 opcode, instruction->info.rt, instruction->info.ra,
588 instruction->info.rb,
589 (instruction->info.imm >> 8) & 0x3);
590 break;
591 }
592 break;
593 case 1:
594 switch (sub_opcode & 0x7) {
595 case 0: /* SB */
596 nds32_parse_type_3(opcode, &(instruction->info.rt),
597 &(instruction->info.ra),
598 &(instruction->info.rb), &(instruction->info.imm));
599 instruction->type = NDS32_INSN_LOAD_STORE;
600 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
601 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
602 instruction->access_start = val_ra +
603 (val_rb << ((instruction->info.imm >> 8) & 0x3));
604 instruction->access_end = instruction->access_start + 1;
605 snprintf(instruction->text,
606 128,
607 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
608 "\tSB\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
609 address,
610 opcode, instruction->info.rt,
611 instruction->info.ra, instruction->info.rb,
612 (instruction->info.imm >> 8) & 0x3);
613 break;
614 case 1: /* SH */
615 nds32_parse_type_3(opcode, &(instruction->info.rt),
616 &(instruction->info.ra),
617 &(instruction->info.rb), &(instruction->info.imm));
618 instruction->type = NDS32_INSN_LOAD_STORE;
619 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
620 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
621 instruction->access_start = val_ra +
622 (val_rb << ((instruction->info.imm >> 8) & 0x3));
623 instruction->access_end = instruction->access_start + 2;
624 snprintf(instruction->text,
625 128,
626 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
627 "\tSH\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
628 address,
629 opcode, instruction->info.rt, instruction->info.ra,
630 instruction->info.rb,
631 (instruction->info.imm >> 8) & 0x3);
632 break;
633 case 2: /* SW */
634 nds32_parse_type_3(opcode, &(instruction->info.rt),
635 &(instruction->info.ra),
636 &(instruction->info.rb), &(instruction->info.imm));
637 instruction->type = NDS32_INSN_LOAD_STORE;
638 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
639 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
640 instruction->access_start = val_ra +
641 (val_rb << ((instruction->info.imm >> 8) & 0x3));
642 instruction->access_end = instruction->access_start + 4;
643 snprintf(instruction->text,
644 128,
645 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
646 "\tSW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
647 address,
648 opcode, instruction->info.rt,
649 instruction->info.ra, instruction->info.rb,
650 (instruction->info.imm >> 8) & 0x3);
651 break;
652 case 4: /* SB.bi */
653 nds32_parse_type_3(opcode, &(instruction->info.rt),
654 &(instruction->info.ra),
655 &(instruction->info.rb), &(instruction->info.imm));
656 instruction->type = NDS32_INSN_LOAD_STORE;
657 nds32_get_mapped_reg(nds32, instruction->info.ra,
658 &(instruction->access_start));
659 instruction->access_end = instruction->access_start + 1;
660 snprintf(instruction->text,
661 128,
662 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
663 "\tSB.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
664 address,
665 opcode, instruction->info.rt, instruction->info.ra,
666 instruction->info.rb,
667 (instruction->info.imm >> 8) & 0x3);
668 break;
669 case 5: /* SH.bi */
670 nds32_parse_type_3(opcode, &(instruction->info.rt),
671 &(instruction->info.ra),
672 &(instruction->info.rb), &(instruction->info.imm));
673 instruction->type = NDS32_INSN_LOAD_STORE;
674 nds32_get_mapped_reg(nds32, instruction->info.ra,
675 &(instruction->access_start));
676 instruction->access_end = instruction->access_start + 2;
677 snprintf(instruction->text,
678 128,
679 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
680 "\tSH.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
681 address,
682 opcode, instruction->info.rt, instruction->info.ra,
683 instruction->info.rb,
684 (instruction->info.imm >> 8) & 0x3);
685 break;
686 case 6: /* SW.bi */
687 nds32_parse_type_3(opcode, &(instruction->info.rt),
688 &(instruction->info.ra),
689 &(instruction->info.rb), &(instruction->info.imm));
690 instruction->type = NDS32_INSN_LOAD_STORE;
691 nds32_get_mapped_reg(nds32, instruction->info.ra,
692 &(instruction->access_start));
693 instruction->access_end = instruction->access_start + 4;
694 snprintf(instruction->text,
695 128,
696 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
697 "\tSW.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
698 address,
699 opcode, instruction->info.rt, instruction->info.ra,
700 instruction->info.rb,
701 (instruction->info.imm >> 8) & 0x3);
702 break;
703 }
704 break;
705 case 2:
706 switch (sub_opcode & 0x7) {
707 case 0: /* LBS */
708 nds32_parse_type_3(opcode, &(instruction->info.rt),
709 &(instruction->info.ra),
710 &(instruction->info.rb), &(instruction->info.imm));
711 instruction->type = NDS32_INSN_LOAD_STORE;
712 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
713 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
714 instruction->access_start = val_ra +
715 (val_rb << ((instruction->info.imm >> 8) & 0x3));
716 instruction->access_end = instruction->access_start + 1;
717 snprintf(instruction->text,
718 128,
719 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
720 "\tLBS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
721 address,
722 opcode, instruction->info.rt,
723 instruction->info.ra, instruction->info.rb,
724 (instruction->info.imm >> 8) & 0x3);
725 break;
726 case 1: /* LHS */
727 nds32_parse_type_3(opcode, &(instruction->info.rt),
728 &(instruction->info.ra),
729 &(instruction->info.rb), &(instruction->info.imm));
730 instruction->type = NDS32_INSN_LOAD_STORE;
731 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
732 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
733 instruction->access_start = val_ra +
734 (val_rb << ((instruction->info.imm >> 8) & 0x3));
735 instruction->access_end = instruction->access_start + 2;
736 snprintf(instruction->text,
737 128,
738 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
739 "\tLHS\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
740 address,
741 opcode, instruction->info.rt, instruction->info.ra,
742 instruction->info.rb,
743 (instruction->info.imm >> 8) & 0x3);
744 break;
745 case 3: /* DPREF */
746 nds32_parse_type_3(opcode, &(instruction->info.sub_opc),
747 &(instruction->info.ra),
748 &(instruction->info.rb), &(instruction->info.imm));
749 instruction->type = NDS32_INSN_MISC;
750 snprintf(instruction->text,
751 128,
752 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
753 "\tDPREF\t#%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<#%" PRId32 ")]",
754 address,
755 opcode, instruction->info.sub_opc,
756 instruction->info.ra, instruction->info.rb,
757 (instruction->info.imm >> 8) & 0x3);
758 break;
759 case 4: /* LBS.bi */
760 nds32_parse_type_3(opcode, &(instruction->info.rt),
761 &(instruction->info.ra),
762 &(instruction->info.rb), &(instruction->info.imm));
763 instruction->type = NDS32_INSN_LOAD_STORE;
764 nds32_get_mapped_reg(nds32, instruction->info.ra,
765 &(instruction->access_start));
766 instruction->access_end = instruction->access_start + 1;
767 snprintf(instruction->text,
768 128,
769 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
770 "\tLBS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
771 address,
772 opcode, instruction->info.rt, instruction->info.ra,
773 instruction->info.rb,
774 (instruction->info.imm >> 8) & 0x3);
775 break;
776 case 5: /* LHS.bi */
777 nds32_parse_type_3(opcode, &(instruction->info.rt),
778 &(instruction->info.ra),
779 &(instruction->info.rb), &(instruction->info.imm));
780 instruction->type = NDS32_INSN_LOAD_STORE;
781 nds32_get_mapped_reg(nds32, instruction->info.ra,
782 &(instruction->access_start));
783 instruction->access_end = instruction->access_start + 2;
784 snprintf(instruction->text,
785 128,
786 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
787 "\tLHS.bi\t$r%" PRIu8 ",[$r%" PRIu8 "],($r%" PRIu8 "<<%" PRId32 ")",
788 address,
789 opcode, instruction->info.rt, instruction->info.ra,
790 instruction->info.rb,
791 (instruction->info.imm >> 8) & 0x3);
792 break;
793 }
794 break;
795 case 3:
796 switch (sub_opcode & 0x7) {
797 case 0: /* LLW */
798 nds32_parse_type_3(opcode, &(instruction->info.rt),
799 &(instruction->info.ra),
800 &(instruction->info.rb), &(instruction->info.imm));
801 instruction->type = NDS32_INSN_LOAD_STORE;
802 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
803 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
804 instruction->access_start = val_ra +
805 (val_rb << ((instruction->info.imm >> 8) & 0x3));
806 instruction->access_end = instruction->access_start + 4;
807 snprintf(instruction->text,
808 128,
809 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
810 "\tLLW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
811 address,
812 opcode, instruction->info.rt, instruction->info.ra,
813 instruction->info.rb,
814 (instruction->info.imm >> 8) & 0x3);
815 break;
816 case 1: /* SCW */
817 nds32_parse_type_3(opcode, &(instruction->info.rt),
818 &(instruction->info.ra),
819 &(instruction->info.rb), &(instruction->info.imm));
820 instruction->type = NDS32_INSN_LOAD_STORE;
821 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
822 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
823 instruction->access_start = val_ra +
824 (val_rb << ((instruction->info.imm >> 8) & 0x3));
825 instruction->access_end = instruction->access_start + 4;
826 snprintf(instruction->text,
827 128,
828 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
829 "\tSCW\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
830 address,
831 opcode, instruction->info.rt, instruction->info.ra,
832 instruction->info.rb,
833 (instruction->info.imm >> 8) & 0x3);
834 break;
835 }
836 break;
837 case 4:
838 switch (sub_opcode & 0x7) {
839 case 0: /* LBUP */
840 nds32_parse_type_3(opcode, &(instruction->info.rt),
841 &(instruction->info.ra),
842 &(instruction->info.rb), &(instruction->info.imm));
843 instruction->type = NDS32_INSN_LOAD_STORE;
844 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
845 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
846 instruction->access_start = val_ra +
847 (val_rb << ((instruction->info.imm >> 8) & 0x3));
848 instruction->access_end = instruction->access_start + 1;
849 snprintf(instruction->text,
850 128,
851 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
852 "\tLBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
853 address,
854 opcode, instruction->info.rt, instruction->info.ra,
855 instruction->info.rb,
856 (instruction->info.imm >> 8) & 0x3);
857 break;
858 case 2: /* LWUP */
859 nds32_parse_type_3(opcode, &(instruction->info.rt),
860 &(instruction->info.ra),
861 &(instruction->info.rb), &(instruction->info.imm));
862 instruction->type = NDS32_INSN_LOAD_STORE;
863 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
864 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
865 instruction->access_start = val_ra +
866 (val_rb << ((instruction->info.imm >> 8) & 0x3));
867 instruction->access_end = instruction->access_start + 4;
868 snprintf(instruction->text,
869 128,
870 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
871 "\tLWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
872 address,
873 opcode, instruction->info.rt, instruction->info.ra,
874 instruction->info.rb,
875 (instruction->info.imm >> 8) & 0x3);
876 break;
877 }
878 break;
879 case 5:
880 switch (sub_opcode & 0x7) {
881 case 0: /* SBUP */
882 nds32_parse_type_3(opcode, &(instruction->info.rt),
883 &(instruction->info.ra),
884 &(instruction->info.rb), &(instruction->info.imm));
885 instruction->type = NDS32_INSN_LOAD_STORE;
886 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
887 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
888 instruction->access_start = val_ra +
889 (val_rb << ((instruction->info.imm >> 8) & 0x3));
890 instruction->access_end = instruction->access_start + 1;
891 snprintf(instruction->text,
892 128,
893 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
894 "\tSBUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
895 address,
896 opcode, instruction->info.rt, instruction->info.ra,
897 instruction->info.rb,
898 (instruction->info.imm >> 8) & 0x3);
899 break;
900 case 2: /* SWUP */
901 nds32_parse_type_3(opcode, &(instruction->info.rt),
902 &(instruction->info.ra),
903 &(instruction->info.rb), &(instruction->info.imm));
904 instruction->type = NDS32_INSN_LOAD_STORE;
905 nds32_get_mapped_reg(nds32, instruction->info.ra, &val_ra);
906 nds32_get_mapped_reg(nds32, instruction->info.rb, &val_rb);
907 instruction->access_start = val_ra +
908 (val_rb << ((instruction->info.imm >> 8) & 0x3));
909 instruction->access_end = instruction->access_start + 4;
910 snprintf(instruction->text,
911 128,
912 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
913 "\tSWUP\t$r%" PRIu8 ",[$r%" PRIu8 "+($r%" PRIu8 "<<%" PRId32 ")]",
914 address,
915 opcode, instruction->info.rt, instruction->info.ra,
916 instruction->info.rb,
917 (instruction->info.imm >> 8) & 0x3);
918 break;
919 }
920 break;
921 default:
922 snprintf(instruction->text,
923 128,
924 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
925 address,
926 opcode);
927 return ERROR_FAIL;
928 }
929
930 return ERROR_OK;
931 }
932
933 static int nds32_calculate_lsmw_access_range(struct nds32 *nds32,
934 struct nds32_instruction *instruction)
935 {
936 uint8_t ba;
937 uint8_t id;
938 uint8_t enable4;
939
940 enable4 = (instruction->info.imm >> 6) & 0xF;
941 ba = (instruction->info.imm >> 4) & 0x1;
942 id = (instruction->info.imm >> 3) & 0x1;
943
944 if (ba) {
945 nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start));
946 if (id) { /* decrease */
947 /* access_end is the (last_element+1), so no need to minus 4 */
948 /* instruction->access_end -= 4; */
949 instruction->access_end = instruction->access_start;
950 } else { /* increase */
951 instruction->access_start += 4;
952 }
953 } else {
954 nds32_get_mapped_reg(nds32, instruction->info.ra, &(instruction->access_start));
955 instruction->access_end = instruction->access_start - 4;
956 }
957
958 if (id) { /* decrease */
959 instruction->access_start = instruction->access_end -
960 4 * (instruction->info.rd - instruction->info.rb + 1);
961 instruction->access_start -= (4 * enable4_bits[enable4]);
962 } else { /* increase */
963 instruction->access_end = instruction->access_start +
964 4 * (instruction->info.rd - instruction->info.rb + 1);
965 instruction->access_end += (4 * enable4_bits[enable4]);
966 }
967
968 return ERROR_OK;
969 }
970
971 static int nds32_parse_lsmw(struct nds32 *nds32, uint32_t opcode, uint32_t address,
972 struct nds32_instruction *instruction)
973 {
974 if (opcode & 0x20) { /* SMW, SMWA, SMWZB */
975 switch (opcode & 0x3) {
976 /* TODO */
977 case 0: /* SMW */
978 /* use rd as re */
979 nds32_parse_type_3(opcode, &(instruction->info.rb),
980 &(instruction->info.ra),
981 &(instruction->info.rd), &(instruction->info.imm));
982 instruction->type = NDS32_INSN_LOAD_STORE;
983 nds32_calculate_lsmw_access_range(nds32, instruction);
984 snprintf(instruction->text,
985 128,
986 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
987 "\tSMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
988 address,
989 opcode, instruction->info.rb, instruction->info.ra,
990 instruction->info.rd,
991 (instruction->info.imm >> 6) & 0xF);
992 break;
993 case 1: /* SMWA */
994 nds32_parse_type_3(opcode, &(instruction->info.rb),
995 &(instruction->info.ra),
996 &(instruction->info.rd), &(instruction->info.imm));
997 instruction->type = NDS32_INSN_LOAD_STORE;
998 nds32_calculate_lsmw_access_range(nds32, instruction);
999 snprintf(instruction->text,
1000 128,
1001 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1002 "\tSMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1003 address,
1004 opcode, instruction->info.rb, instruction->info.ra,
1005 instruction->info.rd,
1006 (instruction->info.imm >> 6) & 0xF);
1007 break;
1008 case 2: /* SMWZB */
1009 nds32_parse_type_3(opcode, &(instruction->info.rb),
1010 &(instruction->info.ra),
1011 &(instruction->info.rd), &(instruction->info.imm));
1012 instruction->type = NDS32_INSN_LOAD_STORE;
1013 /* TODO: calculate access_start/access_end */
1014 snprintf(instruction->text,
1015 128,
1016 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1017 "\tSMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1018 address,
1019 opcode, instruction->info.rb, instruction->info.ra,
1020 instruction->info.rd,
1021 (instruction->info.imm >> 6) & 0xF);
1022 break;
1023 default:
1024 snprintf(instruction->text,
1025 128,
1026 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1027 address,
1028 opcode);
1029 return ERROR_FAIL;
1030 }
1031 } else { /* LMW, LMWA, LMWZB */
1032 switch (opcode & 0x3) {
1033 case 0: /* LMW */
1034 nds32_parse_type_3(opcode, &(instruction->info.rb),
1035 &(instruction->info.ra),
1036 &(instruction->info.rd), &(instruction->info.imm));
1037 instruction->type = NDS32_INSN_LOAD_STORE;
1038 nds32_calculate_lsmw_access_range(nds32, instruction);
1039 snprintf(instruction->text,
1040 128,
1041 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1042 "\tLMW\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1043 address,
1044 opcode, instruction->info.rb, instruction->info.ra,
1045 instruction->info.rd,
1046 (instruction->info.imm >> 6) & 0xF);
1047 break;
1048 case 1: /* LMWA */
1049 nds32_parse_type_3(opcode, &(instruction->info.rb),
1050 &(instruction->info.ra),
1051 &(instruction->info.rd), &(instruction->info.imm));
1052 instruction->type = NDS32_INSN_LOAD_STORE;
1053 nds32_calculate_lsmw_access_range(nds32, instruction);
1054 snprintf(instruction->text,
1055 128,
1056 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1057 "\tLMWA\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1058 address,
1059 opcode, instruction->info.rb, instruction->info.ra,
1060 instruction->info.rd,
1061 (instruction->info.imm >> 6) & 0xF);
1062 break;
1063 case 2: /* LMWZB */
1064 nds32_parse_type_3(opcode, &(instruction->info.rb),
1065 &(instruction->info.ra),
1066 &(instruction->info.rd), &(instruction->info.imm));
1067 instruction->type = NDS32_INSN_LOAD_STORE;
1068 /* TODO: calculate access_start/access_end */
1069 snprintf(instruction->text,
1070 128,
1071 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1072 "\tLMWZB\t$r%" PRIu8 ",[$r%" PRIu8 "],$r%" PRIu8 ",%" PRId32,
1073 address,
1074 opcode, instruction->info.rb, instruction->info.ra,
1075 instruction->info.rd,
1076 (instruction->info.imm >> 6) & 0xF);
1077 break;
1078 default:
1079 snprintf(instruction->text,
1080 128,
1081 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1082 address,
1083 opcode);
1084 return ERROR_FAIL;
1085 }
1086 }
1087
1088 return ERROR_OK;
1089 }
1090
1091 static int nds32_parse_hwgp(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1092 struct nds32_instruction *instruction)
1093 {
1094 switch ((opcode >> 18) & 0x3) {
1095 case 0: /* LHI.gp */
1096 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1097 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1098 instruction->type = NDS32_INSN_LOAD_STORE;
1099 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1100 instruction->access_start += instruction->info.imm;
1101 instruction->access_end = instruction->access_start + 2;
1102 snprintf(instruction->text,
1103 128,
1104 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1105 "\tLHI.gp\t$r%" PRIu8 ",[#%" PRId32"]",
1106 address,
1107 opcode, instruction->info.rt, instruction->info.imm);
1108 break;
1109 case 1: /* LHSI.gp */
1110 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1111 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1112 instruction->type = NDS32_INSN_LOAD_STORE;
1113 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1114 instruction->access_start += instruction->info.imm;
1115 instruction->access_end = instruction->access_start + 2;
1116 snprintf(instruction->text,
1117 128,
1118 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1119 "\tLHSI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1120 address,
1121 opcode, instruction->info.rt, instruction->info.imm);
1122 break;
1123 case 2: /* SHI.gp */
1124 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1125 instruction->info.imm = (instruction->info.imm << 14) >> 13; /* sign-extend */
1126 instruction->type = NDS32_INSN_LOAD_STORE;
1127 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1128 instruction->access_start += instruction->info.imm;
1129 instruction->access_end = instruction->access_start + 2;
1130 snprintf(instruction->text,
1131 128,
1132 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1133 "\tSHI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1134 address,
1135 opcode, instruction->info.rt, instruction->info.imm);
1136 break;
1137 case 3:
1138 instruction->type = NDS32_INSN_LOAD_STORE;
1139 if ((opcode >> 17) & 0x1) { /* SWI.gp */
1140 nds32_parse_type_1(opcode, &(instruction->info.rt),
1141 &(instruction->info.imm));
1142 /* sign-extend */
1143 instruction->info.imm = (instruction->info.imm << 15) >> 13;
1144 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1145 instruction->access_start += instruction->info.imm;
1146 instruction->access_end = instruction->access_start + 4;
1147 snprintf(instruction->text,
1148 128,
1149 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1150 "\tSWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1151 address,
1152 opcode, instruction->info.rt, instruction->info.imm);
1153 } else { /* LWI.gp */
1154 nds32_parse_type_1(opcode, &(instruction->info.rt),
1155 &(instruction->info.imm));
1156 /* sign-extend */
1157 instruction->info.imm = (instruction->info.imm << 15) >> 13;
1158 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1159 instruction->access_start += instruction->info.imm;
1160 instruction->access_end = instruction->access_start + 4;
1161 snprintf(instruction->text,
1162 128,
1163 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1164 "\tLWI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1165 address,
1166 opcode, instruction->info.rt, instruction->info.imm);
1167 }
1168
1169 break;
1170 default:
1171 snprintf(instruction->text,
1172 128,
1173 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1174 address,
1175 opcode);
1176 return ERROR_FAIL;
1177 }
1178
1179 return ERROR_OK;
1180 }
1181
1182 static int nds32_parse_sbgp(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1183 struct nds32_instruction *instruction)
1184 {
1185 switch ((opcode >> 19) & 0x1) {
1186 case 0: /* SBI.gp */
1187 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1188 instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */
1189 instruction->type = NDS32_INSN_LOAD_STORE;
1190 nds32_get_mapped_reg(nds32, R29, &(instruction->access_start));
1191 instruction->access_start += instruction->info.imm;
1192 instruction->access_end = instruction->access_start + 1;
1193 snprintf(instruction->text,
1194 128,
1195 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1196 "\tSBI.gp\t$r%" PRIu8 ",[#%" PRId32 "]",
1197 address,
1198 opcode, instruction->info.rt, instruction->info.imm);
1199 break;
1200 case 1: /* ADDI.gp */
1201 nds32_parse_type_1(opcode, &(instruction->info.rt), &(instruction->info.imm));
1202 instruction->info.imm = (instruction->info.imm << 13) >> 13; /* sign-extend */
1203 instruction->type = NDS32_INSN_DATA_PROC;
1204 snprintf(instruction->text,
1205 128,
1206 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1207 "\tADDI.gp\t$r%" PRIu8 ",#%" PRId32 "",
1208 address,
1209 opcode, instruction->info.rt, instruction->info.imm);
1210 break;
1211 default:
1212 snprintf(instruction->text,
1213 128,
1214 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1215 address,
1216 opcode);
1217 return ERROR_FAIL;
1218 }
1219
1220 return ERROR_OK;
1221 }
1222
1223 static int nds32_parse_group_3_insn(struct nds32 *nds32, uint32_t opcode, uint32_t address,
1224 struct nds32_instruction *instruction)
1225 {
1226 uint8_t opc_6;
1227
1228 opc_6 = instruction->info.opc_6;
1229
1230 switch (opc_6 & 0x7) {
1231 case 4: /* MEM */
1232 nds32_parse_mem(nds32, opcode, address, instruction);
1233 break;
1234 case 5: /* LSMW */
1235 nds32_parse_lsmw(nds32, opcode, address, instruction);
1236 break;
1237 case 6: /* HWGP */
1238 nds32_parse_hwgp(nds32, opcode, address, instruction);
1239 break;
1240 case 7: /* SBGP */
1241 nds32_parse_sbgp(nds32, opcode, address, instruction);
1242 break;
1243 default:
1244 snprintf(instruction->text,
1245 128,
1246 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1247 address,
1248 opcode);
1249 return ERROR_FAIL;
1250 }
1251
1252 return ERROR_OK;
1253 }
1254
1255 static int nds32_parse_alu_1(uint32_t opcode, uint32_t address,
1256 struct nds32_instruction *instruction)
1257 {
1258 switch (opcode & 0x1F) {
1259 case 0: /* ADD */
1260 nds32_parse_type_3(opcode, &(instruction->info.rt), &(instruction->info.ra),
1261 &(instruction->info.rb), &(instruction->info.imm));
1262 instruction->type = NDS32_INSN_DATA_PROC;
1263 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1264 if (instruction->info.imm)
1265 snprintf(instruction->text,
1266 128,
1267 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1268 "\tADD_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1269 address,
1270 opcode, instruction->info.rt, instruction->info.ra,
1271 instruction->info.rb,
1272 instruction->info.imm);
1273 else
1274 snprintf(instruction->text,
1275 128,
1276 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1277 "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1278 address,
1279 opcode, instruction->info.rt, instruction->info.ra,
1280 instruction->info.rb);
1281 break;
1282 case 1: /* SUB */
1283 nds32_parse_type_3(opcode, &(instruction->info.rt),
1284 &(instruction->info.ra),
1285 &(instruction->info.rb), &(instruction->info.imm));
1286 instruction->type = NDS32_INSN_DATA_PROC;
1287 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1288 if (instruction->info.imm)
1289 snprintf(instruction->text,
1290 128,
1291 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1292 "\tSUB_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1293 address,
1294 opcode, instruction->info.rt, instruction->info.ra,
1295 instruction->info.rb,
1296 instruction->info.imm);
1297 else
1298 snprintf(instruction->text,
1299 128,
1300 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1301 "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "",
1302 address,
1303 opcode, instruction->info.rt, instruction->info.ra,
1304 instruction->info.rb);
1305 break;
1306 case 2: /* AND */
1307 nds32_parse_type_3(opcode, &(instruction->info.rt),
1308 &(instruction->info.ra),
1309 &(instruction->info.rb), &(instruction->info.imm));
1310 instruction->type = NDS32_INSN_DATA_PROC;
1311 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1312 if (instruction->info.imm)
1313 snprintf(instruction->text,
1314 128,
1315 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1316 "\tAND_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1317 address,
1318 opcode, instruction->info.rt, instruction->info.ra,
1319 instruction->info.rb,
1320 instruction->info.imm);
1321 else
1322 snprintf(instruction->text,
1323 128,
1324 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1325 "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 "",
1326 address,
1327 opcode, instruction->info.rt, instruction->info.ra,
1328 instruction->info.rb);
1329 break;
1330 case 3: /* XOR */
1331 nds32_parse_type_3(opcode, &(instruction->info.rt),
1332 &(instruction->info.ra),
1333 &(instruction->info.rb), &(instruction->info.imm));
1334 instruction->type = NDS32_INSN_DATA_PROC;
1335 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1336 if (instruction->info.imm)
1337 snprintf(instruction->text,
1338 128,
1339 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1340 "\tXOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1341 address,
1342 opcode, instruction->info.rt, instruction->info.ra,
1343 instruction->info.rb,
1344 instruction->info.imm);
1345 else
1346 snprintf(instruction->text,
1347 128,
1348 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1349 "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1350 address,
1351 opcode, instruction->info.rt, instruction->info.ra,
1352 instruction->info.rb);
1353 break;
1354 case 4: /* OR */
1355 nds32_parse_type_3(opcode, &(instruction->info.rt),
1356 &(instruction->info.ra),
1357 &(instruction->info.rb), &(instruction->info.imm));
1358 instruction->type = NDS32_INSN_DATA_PROC;
1359 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1360 if (instruction->info.imm)
1361 snprintf(instruction->text,
1362 128,
1363 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1364 "\tOR_SLLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1365 address,
1366 opcode, instruction->info.rt, instruction->info.ra,
1367 instruction->info.rb,
1368 instruction->info.imm);
1369 else
1370 snprintf(instruction->text,
1371 128,
1372 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1373 "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1374 address,
1375 opcode, instruction->info.rt, instruction->info.ra,
1376 instruction->info.rb);
1377 break;
1378 case 5: /* NOR */
1379 nds32_parse_type_3(opcode, &(instruction->info.rt),
1380 &(instruction->info.ra),
1381 &(instruction->info.rb), &(instruction->info.imm));
1382 instruction->type = NDS32_INSN_DATA_PROC;
1383 snprintf(instruction->text,
1384 128,
1385 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1386 "\tNOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1387 address,
1388 opcode, instruction->info.rt, instruction->info.ra,
1389 instruction->info.rb);
1390 break;
1391 case 6: /* SLT */
1392 nds32_parse_type_3(opcode, &(instruction->info.rt),
1393 &(instruction->info.ra),
1394 &(instruction->info.rb), &(instruction->info.imm));
1395 instruction->type = NDS32_INSN_DATA_PROC;
1396 snprintf(instruction->text,
1397 128,
1398 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1399 "\tSLT\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1400 address,
1401 opcode, instruction->info.rt, instruction->info.ra,
1402 instruction->info.rb);
1403 break;
1404 case 7: /* SLTS */
1405 nds32_parse_type_3(opcode, &(instruction->info.rt),
1406 &(instruction->info.ra),
1407 &(instruction->info.rb), &(instruction->info.imm));
1408 instruction->type = NDS32_INSN_DATA_PROC;
1409 snprintf(instruction->text,
1410 128,
1411 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1412 "\tSLTS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1413 address,
1414 opcode, instruction->info.rt, instruction->info.ra,
1415 instruction->info.rb);
1416 break;
1417 case 8: { /* SLLI */
1418 uint8_t imm;
1419 int32_t sub_op;
1420 nds32_parse_type_3(opcode, &(instruction->info.rt),
1421 &(instruction->info.ra),
1422 &imm, &sub_op);
1423 instruction->info.imm = imm;
1424 instruction->type = NDS32_INSN_DATA_PROC;
1425 snprintf(instruction->text,
1426 128,
1427 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1428 "\tSLLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1429 address,
1430 opcode, instruction->info.rt, instruction->info.ra,
1431 instruction->info.imm);
1432 }
1433 break;
1434 case 9: { /* SRLI */
1435 uint8_t imm;
1436 int32_t sub_op;
1437 nds32_parse_type_3(opcode, &(instruction->info.rt),
1438 &(instruction->info.ra),
1439 &imm, &sub_op);
1440 instruction->info.imm = imm;
1441 instruction->type = NDS32_INSN_DATA_PROC;
1442 snprintf(instruction->text,
1443 128,
1444 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1445 "\tSRLI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1446 address,
1447 opcode, instruction->info.rt, instruction->info.ra,
1448 instruction->info.imm);
1449 }
1450 break;
1451 case 10: { /* SRAI */
1452 uint8_t imm;
1453 int32_t sub_op;
1454 nds32_parse_type_3(opcode, &(instruction->info.rt),
1455 &(instruction->info.ra),
1456 &imm, &sub_op);
1457 instruction->info.imm = imm;
1458 instruction->type = NDS32_INSN_DATA_PROC;
1459 snprintf(instruction->text,
1460 128,
1461 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1462 "\tSRAI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1463 address,
1464 opcode, instruction->info.rt, instruction->info.ra,
1465 instruction->info.imm);
1466 }
1467 break;
1468 case 11: { /* ROTRI */
1469 uint8_t imm;
1470 int32_t sub_op;
1471 nds32_parse_type_3(opcode, &(instruction->info.rt),
1472 &(instruction->info.ra),
1473 &imm, &sub_op);
1474 instruction->info.imm = imm;
1475 instruction->type = NDS32_INSN_DATA_PROC;
1476 snprintf(instruction->text,
1477 128,
1478 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1479 "\tROTRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1480 address,
1481 opcode, instruction->info.rt, instruction->info.ra,
1482 instruction->info.imm);
1483 }
1484 break;
1485 case 12: { /* SLL */
1486 nds32_parse_type_3(opcode, &(instruction->info.rt),
1487 &(instruction->info.ra),
1488 &(instruction->info.rb), &(instruction->info.imm));
1489 instruction->type = NDS32_INSN_DATA_PROC;
1490 snprintf(instruction->text,
1491 128,
1492 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1493 "\tSLL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1494 address,
1495 opcode, instruction->info.rt, instruction->info.ra,
1496 instruction->info.rb);
1497 }
1498 break;
1499 case 13: { /* SRL */
1500 nds32_parse_type_3(opcode, &(instruction->info.rt),
1501 &(instruction->info.ra),
1502 &(instruction->info.rb), &(instruction->info.imm));
1503 instruction->type = NDS32_INSN_DATA_PROC;
1504 snprintf(instruction->text,
1505 128,
1506 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1507 "\tSRL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1508 address,
1509 opcode, instruction->info.rt, instruction->info.ra,
1510 instruction->info.rb);
1511 }
1512 break;
1513 case 14: { /* SRA */
1514 nds32_parse_type_3(opcode, &(instruction->info.rt),
1515 &(instruction->info.ra),
1516 &(instruction->info.rb), &(instruction->info.imm));
1517 instruction->type = NDS32_INSN_DATA_PROC;
1518 snprintf(instruction->text,
1519 128,
1520 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1521 "\tSRA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1522 address,
1523 opcode, instruction->info.rt, instruction->info.ra,
1524 instruction->info.rb);
1525 }
1526 break;
1527 case 15: { /* ROTR */
1528 nds32_parse_type_3(opcode, &(instruction->info.rt),
1529 &(instruction->info.ra),
1530 &(instruction->info.rb), &(instruction->info.imm));
1531 instruction->type = NDS32_INSN_DATA_PROC;
1532 snprintf(instruction->text,
1533 128,
1534 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1535 "\tROTR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1536 address,
1537 opcode, instruction->info.rt, instruction->info.ra,
1538 instruction->info.rb);
1539 }
1540 break;
1541 case 16: { /* SEB */
1542 nds32_parse_type_2(opcode, &(instruction->info.rt),
1543 &(instruction->info.ra),
1544 &(instruction->info.imm));
1545 instruction->type = NDS32_INSN_DATA_PROC;
1546 snprintf(instruction->text,
1547 128,
1548 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1549 "\tSEB\t$r%" PRIu8 ",$r%" PRIu8,
1550 address,
1551 opcode, instruction->info.rt, instruction->info.ra);
1552 }
1553 break;
1554 case 17: { /* SEH */
1555 nds32_parse_type_2(opcode, &(instruction->info.rt),
1556 &(instruction->info.ra),
1557 &(instruction->info.imm));
1558 instruction->type = NDS32_INSN_DATA_PROC;
1559 snprintf(instruction->text,
1560 128,
1561 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1562 "\tSEH\t$r%" PRIu8 ",$r%" PRIu8,
1563 address,
1564 opcode, instruction->info.rt, instruction->info.ra);
1565 }
1566 break;
1567 case 18: /* BITC */
1568 nds32_parse_type_3(opcode, &(instruction->info.rt),
1569 &(instruction->info.ra),
1570 &(instruction->info.rb), &(instruction->info.imm));
1571 instruction->type = NDS32_INSN_DATA_PROC;
1572 snprintf(instruction->text,
1573 128,
1574 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1575 "\tBITC\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1576 address,
1577 opcode, instruction->info.rt, instruction->info.ra,
1578 instruction->info.rb);
1579 break;
1580 case 19: { /* ZEH */
1581 nds32_parse_type_2(opcode, &(instruction->info.rt),
1582 &(instruction->info.ra),
1583 &(instruction->info.imm));
1584 instruction->type = NDS32_INSN_DATA_PROC;
1585 snprintf(instruction->text,
1586 128,
1587 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1588 "\tZEH\t$r%" PRIu8 ",$r%" PRIu8,
1589 address,
1590 opcode, instruction->info.rt, instruction->info.ra);
1591 }
1592 break;
1593 case 20: { /* WSBH */
1594 nds32_parse_type_2(opcode, &(instruction->info.rt),
1595 &(instruction->info.ra),
1596 &(instruction->info.imm));
1597 instruction->type = NDS32_INSN_DATA_PROC;
1598 snprintf(instruction->text,
1599 128,
1600 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1601 "\tWSBH\t$r%" PRIu8 ",$r%" PRIu8,
1602 address,
1603 opcode, instruction->info.rt, instruction->info.ra);
1604 }
1605 break;
1606 case 21: /* OR_SRLI */
1607 nds32_parse_type_3(opcode, &(instruction->info.rt),
1608 &(instruction->info.ra),
1609 &(instruction->info.rb), &(instruction->info.imm));
1610 instruction->type = NDS32_INSN_DATA_PROC;
1611 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1612 if (instruction->info.imm)
1613 snprintf(instruction->text,
1614 128,
1615 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1616 "\tOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1617 address,
1618 opcode, instruction->info.rt, instruction->info.ra,
1619 instruction->info.rb,
1620 instruction->info.imm);
1621 else
1622 snprintf(instruction->text,
1623 128,
1624 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1625 "\tOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1626 address,
1627 opcode, instruction->info.rt, instruction->info.ra,
1628 instruction->info.rb);
1629 break;
1630 case 22: { /* DIVSR */
1631 nds32_parse_type_4(opcode, &(instruction->info.rt),
1632 &(instruction->info.ra),
1633 &(instruction->info.rb), &(instruction->info.rd),
1634 &(instruction->info.sub_opc));
1635 instruction->type = NDS32_INSN_DATA_PROC;
1636 snprintf(instruction->text,
1637 128,
1638 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1639 "\tDIVSR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1640 address,
1641 opcode, instruction->info.rt, instruction->info.ra,
1642 instruction->info.rb,
1643 instruction->info.rd);
1644 }
1645 break;
1646 case 23: { /* DIVR */
1647 nds32_parse_type_4(opcode, &(instruction->info.rt),
1648 &(instruction->info.ra),
1649 &(instruction->info.rb), &(instruction->info.rd),
1650 &(instruction->info.sub_opc));
1651 instruction->type = NDS32_INSN_DATA_PROC;
1652 snprintf(instruction->text,
1653 128,
1654 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1655 "\tDIVR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1656 address,
1657 opcode, instruction->info.rt, instruction->info.ra,
1658 instruction->info.rb,
1659 instruction->info.rd);
1660 }
1661 break;
1662 case 24: { /* SVA */
1663 nds32_parse_type_3(opcode, &(instruction->info.rt),
1664 &(instruction->info.ra),
1665 &(instruction->info.rb), &(instruction->info.imm));
1666 instruction->type = NDS32_INSN_DATA_PROC;
1667 snprintf(instruction->text,
1668 128,
1669 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1670 "\tSVA\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1671 address,
1672 opcode, instruction->info.rt, instruction->info.ra,
1673 instruction->info.rb);
1674 }
1675 break;
1676 case 25: { /* SVS */
1677 nds32_parse_type_3(opcode, &(instruction->info.rt),
1678 &(instruction->info.ra),
1679 &(instruction->info.rb), &(instruction->info.imm));
1680 instruction->type = NDS32_INSN_DATA_PROC;
1681 snprintf(instruction->text,
1682 128,
1683 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1684 "\tSVS\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1685 address,
1686 opcode, instruction->info.rt, instruction->info.ra,
1687 instruction->info.rb);
1688 }
1689 break;
1690 case 26: { /* CMOVZ */
1691 nds32_parse_type_3(opcode, &(instruction->info.rt),
1692 &(instruction->info.ra),
1693 &(instruction->info.rb), &(instruction->info.imm));
1694 instruction->type = NDS32_INSN_MISC;
1695 snprintf(instruction->text,
1696 128,
1697 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1698 "\tCMOVZ\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1699 address,
1700 opcode, instruction->info.rt, instruction->info.ra,
1701 instruction->info.rb);
1702 }
1703 break;
1704 case 27: { /* CMOVN */
1705 nds32_parse_type_3(opcode, &(instruction->info.rt),
1706 &(instruction->info.ra),
1707 &(instruction->info.rb), &(instruction->info.imm));
1708 instruction->type = NDS32_INSN_MISC;
1709 snprintf(instruction->text,
1710 128,
1711 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1712 "\tCMOVN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1713 address,
1714 opcode, instruction->info.rt, instruction->info.ra,
1715 instruction->info.rb);
1716 }
1717 break;
1718 case 28: /* ADD_SRLI */
1719 nds32_parse_type_3(opcode, &(instruction->info.rt),
1720 &(instruction->info.ra),
1721 &(instruction->info.rb), &(instruction->info.imm));
1722 instruction->type = NDS32_INSN_DATA_PROC;
1723 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1724 if (instruction->info.imm)
1725 snprintf(instruction->text,
1726 128,
1727 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1728 "\tADD_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1729 address,
1730 opcode, instruction->info.rt, instruction->info.ra,
1731 instruction->info.rb,
1732 instruction->info.imm);
1733 else
1734 snprintf(instruction->text,
1735 128,
1736 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1737 "\tADD\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1738 address,
1739 opcode, instruction->info.rt, instruction->info.ra,
1740 instruction->info.rb);
1741 break;
1742 case 29: /* SUB_SRLI */
1743 nds32_parse_type_3(opcode, &(instruction->info.rt),
1744 &(instruction->info.ra),
1745 &(instruction->info.rb), &(instruction->info.imm));
1746 instruction->type = NDS32_INSN_DATA_PROC;
1747 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1748 if (instruction->info.imm)
1749 snprintf(instruction->text,
1750 128,
1751 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1752 "\tSUB_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1753 address,
1754 opcode, instruction->info.rt, instruction->info.ra,
1755 instruction->info.rb,
1756 instruction->info.imm);
1757 else
1758 snprintf(instruction->text,
1759 128,
1760 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1761 "\tSUB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1762 address,
1763 opcode, instruction->info.rt, instruction->info.ra,
1764 instruction->info.rb);
1765 break;
1766 case 30: /* AND_SRLI */
1767 nds32_parse_type_3(opcode, &(instruction->info.rt),
1768 &(instruction->info.ra),
1769 &(instruction->info.rb), &(instruction->info.imm));
1770 instruction->type = NDS32_INSN_DATA_PROC;
1771 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1772 if (instruction->info.imm)
1773 snprintf(instruction->text,
1774 128,
1775 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1776 "\tAND_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1777 address,
1778 opcode, instruction->info.rt, instruction->info.ra,
1779 instruction->info.rb,
1780 instruction->info.imm);
1781 else
1782 snprintf(instruction->text,
1783 128,
1784 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1785 "\tAND\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1786 address,
1787 opcode, instruction->info.rt, instruction->info.ra,
1788 instruction->info.rb);
1789 break;
1790 case 31: /* XOR_SRLI */
1791 nds32_parse_type_3(opcode, &(instruction->info.rt),
1792 &(instruction->info.ra),
1793 &(instruction->info.rb), &(instruction->info.imm));
1794 instruction->type = NDS32_INSN_DATA_PROC;
1795 instruction->info.imm = (instruction->info.imm >> 5) & 0x1F;
1796 if (instruction->info.imm)
1797 snprintf(instruction->text,
1798 128,
1799 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1800 "\tXOR_SRLI\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8 ",%" PRId32,
1801 address,
1802 opcode, instruction->info.rt, instruction->info.ra,
1803 instruction->info.rb,
1804 instruction->info.imm);
1805 else
1806 snprintf(instruction->text,
1807 128,
1808 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1809 "\tXOR\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1810 address,
1811 opcode, instruction->info.rt, instruction->info.ra,
1812 instruction->info.rb);
1813 break;
1814 default:
1815 snprintf(instruction->text,
1816 128,
1817 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
1818 address,
1819 opcode);
1820 return ERROR_FAIL;
1821 }
1822
1823 return ERROR_OK;
1824 }
1825
1826 static int nds32_parse_alu_2(uint32_t opcode, uint32_t address,
1827 struct nds32_instruction *instruction)
1828 {
1829 switch (opcode & 0x3F) {
1830 case 0: /* MAX */
1831 nds32_parse_type_3(opcode, &(instruction->info.rt),
1832 &(instruction->info.ra),
1833 &(instruction->info.rb), &(instruction->info.imm));
1834 instruction->type = NDS32_INSN_DATA_PROC;
1835 snprintf(instruction->text,
1836 128,
1837 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1838 "\tMAX\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1839 address,
1840 opcode, instruction->info.rt, instruction->info.ra,
1841 instruction->info.rb);
1842 break;
1843 case 1: /* MIN */
1844 nds32_parse_type_3(opcode, &(instruction->info.rt),
1845 &(instruction->info.ra),
1846 &(instruction->info.rb), &(instruction->info.imm));
1847 instruction->type = NDS32_INSN_DATA_PROC;
1848 snprintf(instruction->text,
1849 128,
1850 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1851 "\tMIN\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1852 address,
1853 opcode, instruction->info.rt, instruction->info.ra,
1854 instruction->info.rb);
1855 break;
1856 case 2: /* AVE */
1857 nds32_parse_type_3(opcode, &(instruction->info.rt),
1858 &(instruction->info.ra),
1859 &(instruction->info.rb), &(instruction->info.imm));
1860 instruction->type = NDS32_INSN_DATA_PROC;
1861 snprintf(instruction->text,
1862 128,
1863 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1864 "\tAVE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
1865 address,
1866 opcode, instruction->info.rt, instruction->info.ra,
1867 instruction->info.rb);
1868 break;
1869 case 3: /* ABS */
1870 nds32_parse_type_2(opcode, &(instruction->info.rt),
1871 &(instruction->info.ra),
1872 &(instruction->info.imm));
1873 instruction->type = NDS32_INSN_DATA_PROC;
1874 snprintf(instruction->text,
1875 128,
1876 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1877 "\tAVE\t$r%" PRIu8 ",$r%" PRIu8,
1878 address,
1879 opcode, instruction->info.rt, instruction->info.ra);
1880 break;
1881 case 4: { /* CLIPS */
1882 uint8_t imm;
1883 nds32_parse_type_3(opcode, &(instruction->info.rt),
1884 &(instruction->info.ra),
1885 &imm, &(instruction->info.imm));
1886 instruction->info.imm = imm;
1887 instruction->type = NDS32_INSN_DATA_PROC;
1888 snprintf(instruction->text,
1889 128,
1890 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1891 "\tCLIPS\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1892 address,
1893 opcode, instruction->info.rt, instruction->info.ra,
1894 instruction->info.imm);
1895 }
1896 break;
1897 case 5: { /* CLIP */
1898 uint8_t imm;
1899 nds32_parse_type_3(opcode, &(instruction->info.rt),
1900 &(instruction->info.ra),
1901 &imm, &(instruction->info.imm));
1902 instruction->info.imm = imm;
1903 instruction->type = NDS32_INSN_DATA_PROC;
1904 snprintf(instruction->text,
1905 128,
1906 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1907 "\tCLIP\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1908 address,
1909 opcode, instruction->info.rt, instruction->info.ra,
1910 instruction->info.imm);
1911 }
1912 break;
1913 case 6: /* CLO */
1914 nds32_parse_type_2(opcode, &(instruction->info.rt),
1915 &(instruction->info.ra),
1916 &(instruction->info.imm));
1917 instruction->type = NDS32_INSN_DATA_PROC;
1918 snprintf(instruction->text,
1919 128,
1920 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1921 "\tCLO\t$r%" PRIu8 ",$r%" PRIu8,
1922 address,
1923 opcode, instruction->info.rt, instruction->info.ra);
1924 break;
1925 case 7: /* CLZ */
1926 nds32_parse_type_2(opcode, &(instruction->info.rt),
1927 &(instruction->info.ra),
1928 &(instruction->info.imm));
1929 instruction->type = NDS32_INSN_DATA_PROC;
1930 snprintf(instruction->text,
1931 128,
1932 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1933 "\tCLZ\t$r%" PRIu8 ",$r%" PRIu8,
1934 address,
1935 opcode, instruction->info.rt, instruction->info.ra);
1936 break;
1937 case 8: { /* BSET */
1938 uint8_t imm;
1939 nds32_parse_type_3(opcode, &(instruction->info.rt),
1940 &(instruction->info.ra),
1941 &imm, &(instruction->info.imm));
1942 instruction->info.imm = imm;
1943 instruction->type = NDS32_INSN_DATA_PROC;
1944 snprintf(instruction->text,
1945 128,
1946 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1947 "\tBSET\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1948 address,
1949 opcode, instruction->info.rt, instruction->info.ra,
1950 instruction->info.imm);
1951 }
1952 break;
1953 case 9: { /* BCLR */
1954 uint8_t imm;
1955 nds32_parse_type_3(opcode, &(instruction->info.rt),
1956 &(instruction->info.ra),
1957 &imm, &(instruction->info.imm));
1958 instruction->info.imm = imm;
1959 instruction->type = NDS32_INSN_DATA_PROC;
1960 snprintf(instruction->text,
1961 128,
1962 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1963 "\tBCLR\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1964 address,
1965 opcode, instruction->info.rt, instruction->info.ra,
1966 instruction->info.imm);
1967 }
1968 break;
1969 case 10: { /* BTGL */
1970 uint8_t imm;
1971 nds32_parse_type_3(opcode, &(instruction->info.rt),
1972 &(instruction->info.ra),
1973 &imm, &(instruction->info.imm));
1974 instruction->info.imm = imm;
1975 instruction->type = NDS32_INSN_DATA_PROC;
1976 snprintf(instruction->text,
1977 128,
1978 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1979 "\tBTGL\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1980 address,
1981 opcode, instruction->info.rt, instruction->info.ra,
1982 instruction->info.imm);
1983 }
1984 break;
1985 case 11: { /* BTST */
1986 uint8_t imm;
1987 nds32_parse_type_3(opcode, &(instruction->info.rt),
1988 &(instruction->info.ra),
1989 &imm, &(instruction->info.imm));
1990 instruction->info.imm = imm;
1991 instruction->type = NDS32_INSN_DATA_PROC;
1992 snprintf(instruction->text,
1993 128,
1994 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
1995 "\tBTST\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
1996 address,
1997 opcode, instruction->info.rt, instruction->info.ra,
1998 instruction->info.imm);
1999 }
2000 break;
2001 case 12: /* BSE */
2002 nds32_parse_type_3(opcode, &(instruction->info.rt),
2003 &(instruction->info.ra),
2004 &(instruction->info.rb), &(instruction->info.imm));
2005 instruction->type = NDS32_INSN_DATA_PROC;
2006 snprintf(instruction->text,
2007 128,
2008 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2009 "\tBSE\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2010 address,
2011 opcode, instruction->info.rt, instruction->info.ra,
2012 instruction->info.rb);
2013 break;
2014 case 13: /* BSP */
2015 nds32_parse_type_3(opcode, &(instruction->info.rt),
2016 &(instruction->info.ra),
2017 &(instruction->info.rb), &(instruction->info.imm));
2018 instruction->type = NDS32_INSN_DATA_PROC;
2019 snprintf(instruction->text,
2020 128,
2021 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2022 "\tBSP\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2023 address,
2024 opcode, instruction->info.rt, instruction->info.ra,
2025 instruction->info.rb);
2026 break;
2027 case 14: /* FFB */
2028 nds32_parse_type_3(opcode, &(instruction->info.rt),
2029 &(instruction->info.ra),
2030 &(instruction->info.rb), &(instruction->info.imm));
2031 instruction->type = NDS32_INSN_DATA_PROC;
2032 snprintf(instruction->text,
2033 128,
2034 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2035 "\tFFB\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2036 address,
2037 opcode, instruction->info.rt, instruction->info.ra,
2038 instruction->info.rb);
2039 break;
2040 case 15: /* FFMISM */
2041 nds32_parse_type_3(opcode, &(instruction->info.rt),
2042 &(instruction->info.ra),
2043 &(instruction->info.rb), &(instruction->info.imm));
2044 instruction->type = NDS32_INSN_DATA_PROC;
2045 snprintf(instruction->text,
2046 128,
2047 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2048 "\tFFMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2049 address,
2050 opcode, instruction->info.rt, instruction->info.ra,
2051 instruction->info.rb);
2052 break;
2053 case 23: /* FFZMISM */
2054 nds32_parse_type_3(opcode, &(instruction->info.rt),
2055 &(instruction->info.ra),
2056 &(instruction->info.rb), &(instruction->info.imm));
2057 instruction->type = NDS32_INSN_DATA_PROC;
2058 snprintf(instruction->text,
2059 128,
2060 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2061 "\tFFZMISM\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2062 address,
2063 opcode, instruction->info.rt, instruction->info.ra,
2064 instruction->info.rb);
2065 break;
2066 case 32: /* MFUSR */
2067 nds32_parse_type_1(opcode, &(instruction->info.rt),
2068 &(instruction->info.imm));
2069 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2070 snprintf(instruction->text,
2071 128,
2072 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2073 "\tMFUSR\t$r%" PRIu8 ",#%" PRId32,
2074 address,
2075 opcode, instruction->info.rt,
2076 (instruction->info.imm >> 10) & 0x3FF);
2077 break;
2078 case 33: /* MTUSR */
2079 nds32_parse_type_1(opcode, &(instruction->info.rt),
2080 &(instruction->info.imm));
2081 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2082 snprintf(instruction->text,
2083 128,
2084 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2085 "\tMTUSR\t$r%" PRIu8 ",#%" PRId32,
2086 address,
2087 opcode, instruction->info.rt,
2088 (instruction->info.imm >> 10) & 0x3FF);
2089 break;
2090 case 36: /* MUL */
2091 nds32_parse_type_3(opcode, &(instruction->info.rt),
2092 &(instruction->info.ra),
2093 &(instruction->info.rb), &(instruction->info.imm));
2094 instruction->type = NDS32_INSN_DATA_PROC;
2095 snprintf(instruction->text,
2096 128,
2097 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2098 "\tMUL\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2099 address,
2100 opcode, instruction->info.rt, instruction->info.ra,
2101 instruction->info.rb);
2102 break;
2103 case 40: { /* MULTS64 */
2104 uint8_t dt_val;
2105 nds32_parse_type_3(opcode, &dt_val,
2106 &(instruction->info.ra),
2107 &(instruction->info.rb), &(instruction->info.imm));
2108 instruction->type = NDS32_INSN_DATA_PROC;
2109 snprintf(instruction->text,
2110 128,
2111 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2112 "\tMULTS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2113 address,
2114 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2115 instruction->info.rb);
2116 }
2117 break;
2118 case 41: { /* MULT64 */
2119 uint8_t dt_val;
2120 nds32_parse_type_3(opcode, &dt_val,
2121 &(instruction->info.ra),
2122 &(instruction->info.rb), &(instruction->info.imm));
2123 instruction->type = NDS32_INSN_DATA_PROC;
2124 snprintf(instruction->text,
2125 128,
2126 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2127 "\tMULT64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2128 address,
2129 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2130 instruction->info.rb);
2131 }
2132 break;
2133 case 42: { /* MADDS64 */
2134 uint8_t dt_val;
2135 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2136 &(instruction->info.rb), &(instruction->info.imm));
2137 instruction->type = NDS32_INSN_DATA_PROC;
2138 snprintf(instruction->text,
2139 128,
2140 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2141 "\tMADDS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2142 address,
2143 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2144 instruction->info.rb);
2145 }
2146 break;
2147 case 43: { /* MADD64 */
2148 uint8_t dt_val;
2149 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2150 &(instruction->info.rb), &(instruction->info.imm));
2151 instruction->type = NDS32_INSN_DATA_PROC;
2152 snprintf(instruction->text,
2153 128,
2154 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2155 "\tMADD64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2156 address,
2157 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2158 instruction->info.rb);
2159 }
2160 break;
2161 case 44: { /* MSUBS64 */
2162 uint8_t dt_val;
2163 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2164 &(instruction->info.rb), &(instruction->info.imm));
2165 instruction->type = NDS32_INSN_DATA_PROC;
2166 snprintf(instruction->text,
2167 128,
2168 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2169 "\tMSUBS64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2170 address,
2171 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2172 instruction->info.rb);
2173 }
2174 break;
2175 case 45: { /* MSUB64 */
2176 uint8_t dt_val;
2177 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2178 &(instruction->info.rb), &(instruction->info.imm));
2179 instruction->type = NDS32_INSN_DATA_PROC;
2180 snprintf(instruction->text,
2181 128,
2182 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2183 "\tMSUB64\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2184 address,
2185 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2186 instruction->info.rb);
2187 }
2188 break;
2189 case 46: { /* DIVS */
2190 uint8_t dt_val;
2191 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2192 &(instruction->info.rb), &(instruction->info.imm));
2193 instruction->type = NDS32_INSN_DATA_PROC;
2194 snprintf(instruction->text,
2195 128,
2196 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2197 "\tDIVS\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2198 address,
2199 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2200 instruction->info.rb);
2201 }
2202 break;
2203 case 47: { /* DIV */
2204 uint8_t dt_val;
2205 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2206 &(instruction->info.rb), &(instruction->info.imm));
2207 instruction->type = NDS32_INSN_DATA_PROC;
2208 snprintf(instruction->text,
2209 128,
2210 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2211 "\tDIV\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2212 address,
2213 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2214 instruction->info.rb);
2215 }
2216 break;
2217 case 49: { /* MULT32 */
2218 uint8_t dt_val;
2219 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2220 &(instruction->info.rb), &(instruction->info.imm));
2221 instruction->type = NDS32_INSN_DATA_PROC;
2222 snprintf(instruction->text,
2223 128,
2224 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2225 "\tMULT32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2226 address,
2227 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2228 instruction->info.rb);
2229 }
2230 break;
2231 case 51: { /* MADD32 */
2232 uint8_t dt_val;
2233 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2234 &(instruction->info.rb), &(instruction->info.imm));
2235 instruction->type = NDS32_INSN_DATA_PROC;
2236 snprintf(instruction->text,
2237 128,
2238 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2239 "\tMADD32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2240 address,
2241 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2242 instruction->info.rb);
2243 }
2244 break;
2245 case 53: { /* MSUB32 */
2246 uint8_t dt_val;
2247 nds32_parse_type_3(opcode, &dt_val, &(instruction->info.ra),
2248 &(instruction->info.rb), &(instruction->info.imm));
2249 instruction->type = NDS32_INSN_DATA_PROC;
2250 snprintf(instruction->text,
2251 128,
2252 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2253 "\tMSUB32\t$D%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
2254 address,
2255 opcode, (uint8_t)((dt_val >> 1) & 0x1), instruction->info.ra,
2256 instruction->info.rb);
2257 }
2258 break;
2259 default:
2260 snprintf(instruction->text,
2261 128,
2262 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2263 address,
2264 opcode);
2265 return ERROR_FAIL;
2266 }
2267
2268 return ERROR_OK;
2269 }
2270
2271 static int nds32_parse_group_4_insn(struct nds32 *nds32, uint32_t opcode,
2272 uint32_t address, struct nds32_instruction *instruction)
2273 {
2274 uint8_t opc_6;
2275
2276 opc_6 = instruction->info.opc_6;
2277
2278 switch (opc_6 & 0x7) {
2279 case 0: /* ALU_1 */
2280 nds32_parse_alu_1(opcode, address, instruction);
2281 break;
2282 case 1: /* ALU_2 */
2283 nds32_parse_alu_2(opcode, address, instruction);
2284 break;
2285 case 2: /* MOVI */
2286 nds32_parse_type_1(opcode, &(instruction->info.rt),
2287 &(instruction->info.imm));
2288 /* sign-extend */
2289 instruction->info.imm = (instruction->info.imm << 12) >> 12;
2290 instruction->type = NDS32_INSN_DATA_PROC;
2291 snprintf(instruction->text,
2292 128,
2293 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2294 "\tMOVI\t$r%" PRIu8 ",#%" PRId32,
2295 address,
2296 opcode, instruction->info.rt, instruction->info.imm);
2297 break;
2298 case 3: /* SETHI */
2299 nds32_parse_type_1(opcode, &(instruction->info.rt),
2300 &(instruction->info.imm));
2301 instruction->type = NDS32_INSN_DATA_PROC;
2302 snprintf(instruction->text,
2303 128,
2304 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2305 "\tSETHI\t$r%" PRIu8 ",0x%8.8" PRIx32,
2306 address,
2307 opcode, instruction->info.rt, instruction->info.imm);
2308 break;
2309 case 4: /* JI */
2310 nds32_parse_type_0(opcode, &(instruction->info.imm));
2311 /* sign-extend */
2312 instruction->info.imm = (instruction->info.imm << 8) >> 8;
2313 instruction->type = NDS32_INSN_JUMP_BRANCH;
2314 if ((instruction->info.imm >> 24) & 0x1) { /* JAL */
2315 snprintf(instruction->text,
2316 128,
2317 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2318 "\tJAL\t#%" PRId32,
2319 address,
2320 opcode, instruction->info.imm);
2321 } else { /* J */
2322 snprintf(instruction->text,
2323 128,
2324 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2325 "\tJ\t#%" PRId32,
2326 address,
2327 opcode, instruction->info.imm);
2328 }
2329 break;
2330 case 5: { /* JREG */
2331 int32_t imm;
2332 nds32_parse_type_0(opcode, &imm);
2333 instruction->info.rb = (imm >> 10) & 0x1F;
2334 instruction->type = NDS32_INSN_JUMP_BRANCH;
2335 switch (imm & 0x1F) {
2336 /* TODO */
2337 case 0: /* JR */
2338 if (imm & 0x20) { /* RET */
2339 snprintf(instruction->text,
2340 128,
2341 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2342 "\tRET\t$r%" PRIu8,
2343 address,
2344 opcode, instruction->info.rb);
2345 } else { /* JR */
2346 snprintf(instruction->text,
2347 128,
2348 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2349 "\tJR\t$r%" PRIu8,
2350 address,
2351 opcode, instruction->info.rb);
2352 }
2353 break;
2354 case 1: /* JRAL */
2355 instruction->info.rt = (imm >> 20) & 0x1F;
2356 snprintf(instruction->text,
2357 128,
2358 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2359 "\tJRAL\t$r%" PRIu8 ",$r%" PRIu8,
2360 address,
2361 opcode, instruction->info.rt, instruction->info.rb);
2362 break;
2363 case 2: /* JRNEZ */
2364 snprintf(instruction->text,
2365 128,
2366 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2367 "\tJRNEZ\t$r%" PRIu8,
2368 address,
2369 opcode, instruction->info.rb);
2370 break;
2371 case 3: /* JRALNEZ */
2372 instruction->info.rt = (imm >> 20) & 0x1F;
2373 if (instruction->info.rt == R30)
2374 snprintf(instruction->text,
2375 128,
2376 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2377 "\tJRALNEZ\t$r%" PRIu8,
2378 address,
2379 opcode, instruction->info.rb);
2380 else
2381 snprintf(instruction->text,
2382 128,
2383 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2384 "\tJRALNEZ\t$r%" PRIu8 ",$r%" PRIu8,
2385 address,
2386 opcode,
2387 instruction->info.rt,
2388 instruction->info.rb);
2389 break;
2390 }
2391 }
2392 break;
2393 case 6: { /* BR1 */
2394 int32_t imm;
2395
2396 nds32_parse_type_0(opcode, &imm);
2397 instruction->type = NDS32_INSN_JUMP_BRANCH;
2398 if ((imm >> 14) & 0x1) { /* BNE */
2399 nds32_parse_type_2(opcode, &(instruction->info.rt),
2400 &(instruction->info.ra), &(instruction->info.imm));
2401 /* sign-extend */
2402 instruction->info.imm = (instruction->info.imm << 18) >> 18;
2403 snprintf(instruction->text,
2404 128,
2405 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2406 "\tBNE\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2407 address,
2408 opcode, instruction->info.rt, instruction->info.ra,
2409 instruction->info.imm);
2410 } else { /* BEQ */
2411 nds32_parse_type_2(opcode, &(instruction->info.rt),
2412 &(instruction->info.ra), &(instruction->info.imm));
2413 /* sign-extend */
2414 instruction->info.imm = (instruction->info.imm << 18) >> 18;
2415 snprintf(instruction->text,
2416 128,
2417 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2418 "\tBEQ\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2419 address,
2420 opcode, instruction->info.rt,
2421 instruction->info.ra,
2422 instruction->info.imm);
2423 }
2424 }
2425 break;
2426 case 7: { /* BR2 */
2427 int32_t imm;
2428
2429 nds32_parse_type_0(opcode, &imm);
2430 instruction->type = NDS32_INSN_JUMP_BRANCH;
2431 switch ((imm >> 16) & 0xF) {
2432 case 2: /* BEQZ */
2433 nds32_parse_type_1(opcode, &(instruction->info.rt),
2434 &(instruction->info.imm));
2435 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2436 snprintf(instruction->text,
2437 128,
2438 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2439 "\tBEQZ\t$r%" PRIu8 ",#%" PRId32,
2440 address,
2441 opcode, instruction->info.rt, instruction->info.imm);
2442 break;
2443 case 3: /* BNEZ */
2444 nds32_parse_type_1(opcode, &(instruction->info.rt),
2445 &(instruction->info.imm));
2446 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2447 snprintf(instruction->text,
2448 128,
2449 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2450 "\tBNEZ\t$r%" PRIu8 ",#%" PRId32,
2451 address,
2452 opcode, instruction->info.rt, instruction->info.imm);
2453 break;
2454 case 4: /* BGEZ */
2455 nds32_parse_type_1(opcode, &(instruction->info.rt),
2456 &(instruction->info.imm));
2457 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2458 snprintf(instruction->text,
2459 128,
2460 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2461 "\tBGEZ\t$r%" PRIu8 ",#%" PRId32,
2462 address,
2463 opcode, instruction->info.rt, instruction->info.imm);
2464 break;
2465 case 5: /* BLTZ */
2466 nds32_parse_type_1(opcode, &(instruction->info.rt),
2467 &(instruction->info.imm));
2468 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2469 snprintf(instruction->text,
2470 128,
2471 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2472 "\tBLTZ\t$r%" PRIu8 ",#%" PRId32,
2473 address,
2474 opcode, instruction->info.rt, instruction->info.imm);
2475 break;
2476 case 6: /* BGTZ */
2477 nds32_parse_type_1(opcode, &(instruction->info.rt),
2478 &(instruction->info.imm));
2479 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2480 snprintf(instruction->text,
2481 128,
2482 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2483 "\tBGTZ\t$r%" PRIu8 ",#%" PRId32,
2484 address,
2485 opcode, instruction->info.rt, instruction->info.imm);
2486 break;
2487 case 7: /* BLEZ */
2488 nds32_parse_type_1(opcode, &(instruction->info.rt),
2489 &(instruction->info.imm));
2490 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2491 snprintf(instruction->text,
2492 128,
2493 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2494 "\tBLEZ\t$r%" PRIu8 ",#%" PRId32,
2495 address,
2496 opcode, instruction->info.rt, instruction->info.imm);
2497 break;
2498 case 12: /* BGEZAL */
2499 nds32_parse_type_1(opcode, &(instruction->info.rt),
2500 &(instruction->info.imm));
2501 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2502 snprintf(instruction->text,
2503 128,
2504 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2505 "\tBGEZAL\t$r%" PRIu8 ",#%" PRId32,
2506 address,
2507 opcode, instruction->info.rt, instruction->info.imm);
2508 break;
2509 case 13: /* BLTZAL */
2510 nds32_parse_type_1(opcode, &(instruction->info.rt),
2511 &(instruction->info.imm));
2512 instruction->info.imm = (instruction->info.imm << 16) >> 16;
2513 snprintf(instruction->text,
2514 128,
2515 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2516 "\tBLTZAL\t$r%" PRIu8 ",#%" PRId32,
2517 address,
2518 opcode, instruction->info.rt, instruction->info.imm);
2519 break;
2520 }
2521 }
2522 break;
2523 default:
2524 snprintf(instruction->text,
2525 128,
2526 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2527 address,
2528 opcode);
2529 return ERROR_FAIL;
2530 }
2531
2532 return ERROR_OK;
2533 }
2534
2535 static int nds32_parse_group_5_insn(struct nds32 *nds32, uint32_t opcode,
2536 uint32_t address, struct nds32_instruction *instruction)
2537 {
2538 uint8_t opc_6;
2539
2540 opc_6 = instruction->info.opc_6;
2541
2542 switch (opc_6 & 0x7) {
2543 case 0: /* ADDI */
2544 nds32_parse_type_2(opcode, &(instruction->info.rt),
2545 &(instruction->info.ra), &(instruction->info.imm));
2546 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2547 instruction->type = NDS32_INSN_DATA_PROC;
2548 snprintf(instruction->text,
2549 128,
2550 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2551 "\tADDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2552 address,
2553 opcode, instruction->info.rt, instruction->info.ra,
2554 instruction->info.imm);
2555 break;
2556 case 1: /* SUBRI */
2557 nds32_parse_type_2(opcode, &(instruction->info.rt),
2558 &(instruction->info.ra), &(instruction->info.imm));
2559 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2560 instruction->type = NDS32_INSN_DATA_PROC;
2561 snprintf(instruction->text,
2562 128,
2563 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2564 "\tSUBRI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2565 address,
2566 opcode, instruction->info.rt, instruction->info.ra,
2567 instruction->info.imm);
2568 break;
2569 case 2: /* ANDI */
2570 nds32_parse_type_2(opcode, &(instruction->info.rt),
2571 &(instruction->info.ra), &(instruction->info.imm));
2572 instruction->type = NDS32_INSN_DATA_PROC;
2573 snprintf(instruction->text,
2574 128,
2575 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2576 "\tANDI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2577 address,
2578 opcode, instruction->info.rt, instruction->info.ra,
2579 instruction->info.imm);
2580 break;
2581 case 3: /* XORI */
2582 nds32_parse_type_2(opcode, &(instruction->info.rt),
2583 &(instruction->info.ra), &(instruction->info.imm));
2584 instruction->type = NDS32_INSN_DATA_PROC;
2585 snprintf(instruction->text,
2586 128,
2587 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2588 "\tXORI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2589 address,
2590 opcode, instruction->info.rt, instruction->info.ra,
2591 instruction->info.imm);
2592 break;
2593 case 4: /* ORI */
2594 nds32_parse_type_2(opcode, &(instruction->info.rt),
2595 &(instruction->info.ra), &(instruction->info.imm));
2596 instruction->type = NDS32_INSN_DATA_PROC;
2597 snprintf(instruction->text,
2598 128,
2599 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2600 "\tORI\t$r%" PRIu8 ",$r%" PRIu8 ",0x%8.8" PRIx32,
2601 address,
2602 opcode, instruction->info.rt, instruction->info.ra,
2603 instruction->info.imm);
2604 break;
2605 case 6: /* SLTI */
2606 nds32_parse_type_2(opcode, &(instruction->info.rt),
2607 &(instruction->info.ra), &(instruction->info.imm));
2608 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2609 instruction->type = NDS32_INSN_DATA_PROC;
2610 snprintf(instruction->text,
2611 128,
2612 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2613 "\tSLTI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2614 address,
2615 opcode, instruction->info.rt, instruction->info.ra,
2616 instruction->info.imm);
2617 break;
2618 case 7: /* SLTSI */
2619 nds32_parse_type_2(opcode, &(instruction->info.rt),
2620 &(instruction->info.ra), &(instruction->info.imm));
2621 instruction->info.imm = (instruction->info.imm << 17) >> 17; /* sign-extend */
2622 instruction->type = NDS32_INSN_DATA_PROC;
2623 snprintf(instruction->text,
2624 128,
2625 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2626 "\tSLTSI\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2627 address,
2628 opcode, instruction->info.rt, instruction->info.ra,
2629 instruction->info.imm);
2630 break;
2631 default:
2632 snprintf(instruction->text,
2633 128,
2634 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2635 address,
2636 opcode);
2637 return ERROR_FAIL;
2638 }
2639
2640 return ERROR_OK;
2641 }
2642
2643 static int nds32_parse_group_6_insn(struct nds32 *nds32, uint32_t opcode,
2644 uint32_t address, struct nds32_instruction *instruction)
2645 {
2646 uint8_t opc_6;
2647
2648 opc_6 = instruction->info.opc_6;
2649
2650 switch (opc_6 & 0x7) {
2651 case 2: { /* MISC */
2652 int32_t imm;
2653 uint8_t sub_opc;
2654
2655 nds32_parse_type_0(opcode, &imm);
2656
2657 sub_opc = imm & 0x1F;
2658 switch (sub_opc) {
2659 case 0: /* STANDBY */
2660 instruction->type = NDS32_INSN_MISC;
2661 snprintf(instruction->text,
2662 128,
2663 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2664 "\tSTANDBY\t#%" PRIu32,
2665 address,
2666 opcode, (opcode >> 5) & 0x3);
2667 break;
2668 case 1: /* CCTL */
2669 /* TODO */
2670 nds32_parse_type_2(opcode, &(instruction->info.rt),
2671 &(instruction->info.ra), &(instruction->info.imm));
2672 instruction->type = NDS32_INSN_MISC;
2673 snprintf(instruction->text,
2674 128,
2675 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCCTL",
2676 address,
2677 opcode);
2678 break;
2679 case 2: /* MFSR */
2680 nds32_parse_type_1(opcode, &(instruction->info.rt),
2681 &(instruction->info.imm));
2682 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2683 snprintf(instruction->text,
2684 128,
2685 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2686 "\tMFSR\t$r%" PRIu8 ",#%" PRId32,
2687 address,
2688 opcode, instruction->info.rt,
2689 (instruction->info.imm >> 10) & 0x3FF);
2690 break;
2691 case 3: /* MTSR */
2692 nds32_parse_type_1(opcode, &(instruction->info.ra),
2693 &(instruction->info.imm));
2694 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2695 snprintf(instruction->text,
2696 128,
2697 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2698 "\tMTSR\t$r%" PRIu8 ",#%" PRId32,
2699 address,
2700 opcode, instruction->info.ra,
2701 (instruction->info.imm >> 10) & 0x3FF);
2702 break;
2703 case 4: /* IRET */
2704 instruction->type = NDS32_INSN_MISC;
2705 snprintf(instruction->text,
2706 128,
2707 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tIRET",
2708 address,
2709 opcode);
2710 break;
2711 case 5: /* TRAP */
2712 instruction->type = NDS32_INSN_MISC;
2713 snprintf(instruction->text,
2714 128,
2715 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2716 "\tTRAP\t#%" PRId32,
2717 address,
2718 opcode, (imm >> 5) & 0x7FFF);
2719 break;
2720 case 6: /* TEQZ */
2721 nds32_parse_type_1(opcode, &(instruction->info.ra),
2722 &(instruction->info.imm));
2723 instruction->type = NDS32_INSN_MISC;
2724 snprintf(instruction->text,
2725 128,
2726 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2727 "\tTEQZ\t$r%" PRIu8 ",#%" PRId32,
2728 address,
2729 opcode, instruction->info.ra,
2730 (instruction->info.imm >> 5) & 0x7FFF);
2731 break;
2732 case 7: /* TNEZ */
2733 nds32_parse_type_1(opcode, &(instruction->info.ra),
2734 &(instruction->info.imm));
2735 instruction->type = NDS32_INSN_MISC;
2736 snprintf(instruction->text,
2737 128,
2738 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2739 "\tTNEZ\t$r%" PRIu8 ",#%" PRId32,
2740 address,
2741 opcode, instruction->info.ra,
2742 (instruction->info.imm >> 5) & 0x7FFF);
2743 break;
2744 case 8: /* DSB */
2745 instruction->type = NDS32_INSN_MISC;
2746 snprintf(instruction->text,
2747 128,
2748 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tDSB",
2749 address,
2750 opcode);
2751 break;
2752 case 9: /* ISB */
2753 instruction->type = NDS32_INSN_MISC;
2754 snprintf(instruction->text,
2755 128,
2756 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB",
2757 address,
2758 opcode);
2759 break;
2760 case 10: /* BREAK */
2761 instruction->type = NDS32_INSN_MISC;
2762 instruction->info.sub_opc = imm & 0x1F;
2763 instruction->info.imm = (imm >> 5) & 0x7FFF;
2764 snprintf(instruction->text,
2765 128,
2766 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2767 "\tBREAK\t#%" PRId32,
2768 address,
2769 opcode, instruction->info.imm);
2770 break;
2771 case 11: /* SYSCALL */
2772 instruction->type = NDS32_INSN_MISC;
2773 snprintf(instruction->text,
2774 128,
2775 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2776 "\tSYSCALL\t#%" PRId32,
2777 address,
2778 opcode, (imm >> 5) & 0x7FFF);
2779 break;
2780 case 12: /* MSYNC */
2781 instruction->type = NDS32_INSN_MISC;
2782 snprintf(instruction->text,
2783 128,
2784 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2785 "\tMSYNC\t#%" PRId32,
2786 address,
2787 opcode, (imm >> 5) & 0x7);
2788 break;
2789 case 13: /* ISYNC */
2790 nds32_parse_type_1(opcode, &(instruction->info.ra),
2791 &(instruction->info.imm));
2792 instruction->type = NDS32_INSN_MISC;
2793 snprintf(instruction->text,
2794 128,
2795 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32
2796 "\tISYNC\t$r%" PRIu8,
2797 address,
2798 opcode, instruction->info.ra);
2799 break;
2800 case 14: /* TLBOP */
2801 /* TODO */
2802 nds32_parse_type_2(opcode, &(instruction->info.rt),
2803 &(instruction->info.ra), &(instruction->info.imm));
2804 instruction->type = NDS32_INSN_RESOURCE_ACCESS;
2805 snprintf(instruction->text,
2806 128,
2807 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tTLBOP",
2808 address,
2809 opcode);
2810 break;
2811 }
2812
2813 break;
2814 }
2815 default:
2816 snprintf(instruction->text,
2817 128,
2818 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
2819 address,
2820 opcode);
2821 return ERROR_FAIL;
2822 }
2823
2824 return ERROR_OK;
2825 }
2826
2827 static uint32_t field_mask[9] = {
2828 0x0,
2829 0x1,
2830 0x3,
2831 0x7,
2832 0xF,
2833 0x1F,
2834 0x3F,
2835 0x7F,
2836 0xFF,
2837 };
2838
2839 static uint8_t nds32_extract_field_8u(uint16_t opcode, uint32_t start, uint32_t length)
2840 {
2841 if (length > 0 && length < 9)
2842 return (opcode >> start) & field_mask[length];
2843
2844 return 0;
2845 }
2846
2847 static int nds32_parse_group_0_insn_16(struct nds32 *nds32, uint16_t opcode,
2848 uint32_t address, struct nds32_instruction *instruction)
2849 {
2850 switch ((opcode >> 10) & 0x7) {
2851 case 0: /* MOV55 */
2852 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5);
2853 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
2854 instruction->type = NDS32_INSN_MISC;
2855 snprintf(instruction->text,
2856 128,
2857 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2858 "\t\tMOV55\t$r%" PRIu8 ",$r%" PRIu8,
2859 address,
2860 opcode, instruction->info.rt, instruction->info.ra);
2861 break;
2862 case 1: /* MOVI55 */
2863 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 5);
2864 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2865 instruction->info.imm = (instruction->info.imm << 27) >> 27;
2866 instruction->type = NDS32_INSN_MISC;
2867 snprintf(instruction->text,
2868 128,
2869 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2870 "\t\tMOVI55\t$r%" PRIu8 ",#%" PRId32,
2871 address,
2872 opcode, instruction->info.rt, instruction->info.imm);
2873 break;
2874 case 2: /* ADD45, SUB45 */
2875 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2876 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
2877 instruction->type = NDS32_INSN_DATA_PROC;
2878 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD45 */
2879 snprintf(instruction->text,
2880 128,
2881 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2882 "\t\tADD45\t$r%" PRIu8 ",$r%" PRIu8,
2883 address,
2884 opcode, instruction->info.rt, instruction->info.rb);
2885 } else { /* SUB45 */
2886 snprintf(instruction->text,
2887 128,
2888 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2889 "\t\tSUB45\t$r%" PRIu8 ",$r%" PRIu8,
2890 address,
2891 opcode, instruction->info.rt, instruction->info.rb);
2892 }
2893
2894 break;
2895 case 3: /* ADDI45, SUBI45 */
2896 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2897 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2898 instruction->type = NDS32_INSN_DATA_PROC;
2899 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI45 */
2900 snprintf(instruction->text,
2901 128,
2902 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2903 "\t\tADDI45\t$r%" PRIu8 ",#%" PRId32,
2904 address,
2905 opcode, instruction->info.rt, instruction->info.imm);
2906 } else { /* SUBI45 */
2907 snprintf(instruction->text,
2908 128,
2909 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2910 "\t\tSUBI45\t$r%" PRIu8 ",#%" PRId32,
2911 address,
2912 opcode, instruction->info.rt, instruction->info.imm);
2913 }
2914 break;
2915 case 4: /* SRAI45, SRLI45 */
2916 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
2917 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
2918 instruction->type = NDS32_INSN_DATA_PROC;
2919 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SRAI45 */
2920 snprintf(instruction->text,
2921 128,
2922 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2923 "\t\tSRAI45\t$r%" PRIu8 ",#%" PRId32,
2924 address,
2925 opcode, instruction->info.rt, instruction->info.imm);
2926 } else { /* SRLI45 */
2927 if ((instruction->info.rt == 0) && (instruction->info.imm == 0)) {
2928 snprintf(instruction->text,
2929 128,
2930 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16 "\t\tNOP",
2931 address,
2932 opcode);
2933 } else {
2934 snprintf(instruction->text,
2935 128,
2936 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2937 "\t\tSRLI45\t$r%" PRIu8 ",#%" PRId32,
2938 address,
2939 opcode, instruction->info.rt, instruction->info.imm);
2940 }
2941 }
2942 break;
2943 case 5:
2944 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
2945 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
2946 instruction->type = NDS32_INSN_DATA_PROC;
2947 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* SLLI333 */
2948 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
2949 snprintf(instruction->text,
2950 128,
2951 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2952 "\t\tSLLI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
2953 address,
2954 opcode, instruction->info.rt, instruction->info.ra,
2955 instruction->info.imm);
2956 } else {
2957 instruction->info.sub_opc = nds32_extract_field_8u(opcode, 0, 3);
2958 switch (instruction->info.sub_opc) {
2959 case 0: /* ZEB33 */
2960 snprintf(instruction->text,
2961 128,
2962 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2963 "\t\tZEB33\t$r%" PRIu8 ",$r%" PRIu8,
2964 address,
2965 opcode, instruction->info.rt, instruction->info.ra);
2966 break;
2967 case 1: /* ZEH33 */
2968 snprintf(instruction->text,
2969 128,
2970 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2971 "\t\tZEH33\t$r%" PRIu8 ",$r%" PRIu8,
2972 address,
2973 opcode, instruction->info.rt, instruction->info.ra);
2974 break;
2975 case 2: /* SEB33 */
2976 snprintf(instruction->text,
2977 128,
2978 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2979 "\t\tSEB33\t$r%" PRIu8 ",$r%" PRIu8,
2980 address,
2981 opcode, instruction->info.rt, instruction->info.ra);
2982 break;
2983 case 3: /* SEH33 */
2984 snprintf(instruction->text,
2985 128,
2986 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2987 "\t\tSEH33\t$r%" PRIu8 ",$r%" PRIu8,
2988 address,
2989 opcode, instruction->info.rt, instruction->info.ra);
2990 break;
2991 case 4: /* XLSB33 */
2992 snprintf(instruction->text,
2993 128,
2994 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
2995 "\t\tXLSB33\t$r%" PRIu8 ",$r%" PRIu8,
2996 address,
2997 opcode, instruction->info.rt, instruction->info.ra);
2998 break;
2999 case 5: /* XLLB33 */
3000 snprintf(instruction->text,
3001 128,
3002 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3003 "\t\tXLLB33\t$r%" PRIu8 ",$r%" PRIu8,
3004 address,
3005 opcode, instruction->info.rt, instruction->info.ra);
3006 break;
3007 case 6: /* BMSKI33 */
3008 instruction->info.ra = 0;
3009 instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3);
3010 snprintf(instruction->text,
3011 128,
3012 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3013 "\t\tBMSKI33\t$r%" PRIu8 ",$r%" PRId32,
3014 address,
3015 opcode, instruction->info.rt, instruction->info.imm);
3016 break;
3017 case 7: /* FEXTI33 */
3018 instruction->info.ra = 0;
3019 instruction->info.imm = nds32_extract_field_8u(opcode, 3, 3);
3020 snprintf(instruction->text,
3021 128,
3022 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3023 "\t\tFEXTI33\t$r%" PRIu8 ",$r%" PRId32,
3024 address,
3025 opcode, instruction->info.rt, instruction->info.imm);
3026 break;
3027 default:
3028 snprintf(instruction->text,
3029 128,
3030 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16
3031 "\tUNDEFINED INSTRUCTION",
3032 address,
3033 opcode);
3034 return ERROR_FAIL;
3035 }
3036 }
3037 break;
3038 case 6: /* ADD333, SUB333 */
3039 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3040 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3041 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 3);
3042 instruction->type = NDS32_INSN_DATA_PROC;
3043 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADD333 */
3044 snprintf(instruction->text,
3045 128,
3046 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3047 "\t\tADD333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
3048 address,
3049 opcode, instruction->info.rt, instruction->info.ra,
3050 instruction->info.rb);
3051 } else { /* SUB333 */
3052 snprintf(instruction->text,
3053 128,
3054 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3055 "\t\tSUB333\t$r%" PRIu8 ",$r%" PRIu8 ",$r%" PRIu8,
3056 address,
3057 opcode, instruction->info.rt, instruction->info.ra,
3058 instruction->info.rb);
3059 }
3060 break;
3061 case 7: /* ADDI333, SUBI333 */
3062 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3063 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3064 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3065 instruction->type = NDS32_INSN_DATA_PROC;
3066 if (nds32_extract_field_8u(opcode, 9, 1) == 0) { /* ADDI333 */
3067 snprintf(instruction->text,
3068 128,
3069 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3070 "\t\tADDI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
3071 address,
3072 opcode, instruction->info.rt, instruction->info.ra,
3073 instruction->info.imm);
3074 } else { /* SUBI333 */
3075 snprintf(instruction->text,
3076 128,
3077 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3078 "\t\tSUBI333\t$r%" PRIu8 ",$r%" PRIu8 ",#%" PRId32,
3079 address,
3080 opcode, instruction->info.rt, instruction->info.ra,
3081 instruction->info.imm);
3082 }
3083 break;
3084 default:
3085 snprintf(instruction->text,
3086 128,
3087 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3088 address,
3089 opcode);
3090 return ERROR_FAIL;
3091 }
3092
3093 return ERROR_OK;
3094 }
3095
3096 static int nds32_parse_group_1_insn_16(struct nds32 *nds32, uint16_t opcode,
3097 uint32_t address, struct nds32_instruction *instruction)
3098 {
3099 switch ((opcode >> 9) & 0xF) {
3100 case 0: /* LWI333 */
3101 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3102 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3103 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3104 instruction->type = NDS32_INSN_LOAD_STORE;
3105 nds32_get_mapped_reg(nds32, instruction->info.ra,
3106 &(instruction->access_start));
3107 instruction->access_start += instruction->info.imm;
3108 instruction->access_end = instruction->access_start + 4;
3109 snprintf(instruction->text,
3110 128,
3111 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3112 "\t\tLWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3113 address,
3114 opcode, instruction->info.rt, instruction->info.ra,
3115 instruction->info.imm);
3116 break;
3117 case 1: /* LWI333.BI */
3118 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3119 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3120 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3121 instruction->type = NDS32_INSN_LOAD_STORE;
3122 nds32_get_mapped_reg(nds32, instruction->info.ra,
3123 &(instruction->access_start));
3124 instruction->access_end = instruction->access_start + 4;
3125 snprintf(instruction->text,
3126 128,
3127 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3128 "\t\tLWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
3129 address,
3130 opcode, instruction->info.rt, instruction->info.ra,
3131 instruction->info.imm << 2);
3132 break;
3133 case 2: /* LHI333 */
3134 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3135 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3136 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1;
3137 instruction->type = NDS32_INSN_LOAD_STORE;
3138 nds32_get_mapped_reg(nds32, instruction->info.ra,
3139 &(instruction->access_start));
3140 instruction->access_start += instruction->info.imm;
3141 instruction->access_end = instruction->access_start + 2;
3142 snprintf(instruction->text,
3143 128,
3144 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3145 "\t\tLHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3146 address,
3147 opcode, instruction->info.rt, instruction->info.ra,
3148 instruction->info.imm);
3149 break;
3150 case 3: /* LBI333 */
3151 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3152 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3153 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3154 instruction->type = NDS32_INSN_LOAD_STORE;
3155 nds32_get_mapped_reg(nds32, instruction->info.ra,
3156 &(instruction->access_start));
3157 instruction->access_start += instruction->info.imm;
3158 instruction->access_end = instruction->access_start + 1;
3159 snprintf(instruction->text,
3160 128,
3161 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3162 "\t\tLBI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3163 address,
3164 opcode, instruction->info.rt, instruction->info.ra,
3165 instruction->info.imm);
3166 break;
3167 case 4: /* SWI333 */
3168 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3169 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3170 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3171 instruction->type = NDS32_INSN_LOAD_STORE;
3172 nds32_get_mapped_reg(nds32, instruction->info.ra,
3173 &(instruction->access_start));
3174 instruction->access_start += instruction->info.imm;
3175 instruction->access_end = instruction->access_start + 4;
3176 snprintf(instruction->text,
3177 128,
3178 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3179 "\t\tSWI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3180 address,
3181 opcode, instruction->info.rt, instruction->info.ra,
3182 instruction->info.imm);
3183 break;
3184 case 5: /* SWI333.BI */
3185 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3186 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3187 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 2;
3188 instruction->type = NDS32_INSN_LOAD_STORE;
3189 nds32_get_mapped_reg(nds32, instruction->info.ra,
3190 &(instruction->access_start));
3191 instruction->access_end = instruction->access_start + 4;
3192 snprintf(instruction->text,
3193 128,
3194 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3195 "\t\tSWI333.BI\t$r%" PRIu8 ",[$r%" PRIu8 "],#%" PRId32,
3196 address,
3197 opcode, instruction->info.rt, instruction->info.ra,
3198 instruction->info.imm);
3199 break;
3200 case 6: /* SHI333 */
3201 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3202 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3203 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3) << 1;
3204 instruction->type = NDS32_INSN_LOAD_STORE;
3205 nds32_get_mapped_reg(nds32, instruction->info.ra,
3206 &(instruction->access_start));
3207 instruction->access_start += instruction->info.imm;
3208 instruction->access_end = instruction->access_start + 2;
3209 snprintf(instruction->text,
3210 128,
3211 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3212 "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3213 address,
3214 opcode, instruction->info.rt, instruction->info.ra,
3215 instruction->info.imm);
3216 break;
3217 case 7: /* SBI333 */
3218 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3219 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3220 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 3);
3221 instruction->type = NDS32_INSN_LOAD_STORE;
3222 nds32_get_mapped_reg(nds32, instruction->info.ra,
3223 &(instruction->access_start));
3224 instruction->access_start += instruction->info.imm;
3225 instruction->access_end = instruction->access_start + 1;
3226 snprintf(instruction->text,
3227 128,
3228 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3229 "\t\tSHI333\t$r%" PRIu8 ",[$r%" PRIu8 "+(#%" PRId32 ")]",
3230 address,
3231 opcode, instruction->info.rt, instruction->info.ra,
3232 instruction->info.imm);
3233 break;
3234 case 8: /* ADDRI36.SP */
3235 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3236 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 6) << 2;
3237 instruction->type = NDS32_INSN_DATA_PROC;
3238 snprintf(instruction->text,
3239 128,
3240 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3241 "\t\tADDRI36.SP\t$r%" PRIu8 ",#%" PRId32,
3242 address,
3243 opcode, instruction->info.rt, instruction->info.imm);
3244 break;
3245 case 9: /* LWI45.FE */
3246 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3247 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3248 instruction->info.imm -= 32;
3249 instruction->info.imm <<= 2;
3250 instruction->type = NDS32_INSN_LOAD_STORE;
3251 nds32_get_mapped_reg(nds32, R8, &(instruction->access_start));
3252 instruction->access_start += instruction->info.imm;
3253 instruction->access_end = instruction->access_start + 4;
3254 snprintf(instruction->text,
3255 128,
3256 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3257 "\t\tLWI45.FE\t$r%" PRIu8 ",[#%" PRId32 "]",
3258 address,
3259 opcode, instruction->info.rt, instruction->info.imm);
3260 break;
3261 case 10: /* LWI450 */
3262 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3263 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
3264 instruction->type = NDS32_INSN_LOAD_STORE;
3265 nds32_get_mapped_reg(nds32, instruction->info.ra,
3266 &(instruction->access_start));
3267 instruction->access_end = instruction->access_start + 4;
3268 snprintf(instruction->text,
3269 128,
3270 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3271 "\t\tLWI450\t$r%" PRIu8 ",$r%" PRIu8,
3272 address,
3273 opcode, instruction->info.rt, instruction->info.ra);
3274 break;
3275 case 11: /* SWI450 */
3276 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3277 instruction->info.ra = nds32_extract_field_8u(opcode, 0, 5);
3278 instruction->type = NDS32_INSN_LOAD_STORE;
3279 nds32_get_mapped_reg(nds32, instruction->info.ra,
3280 &(instruction->access_start));
3281 instruction->access_end = instruction->access_start + 4;
3282 snprintf(instruction->text,
3283 128,
3284 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3285 "\t\tSWI450\t$r%" PRIu8 ",$r%" PRIu8,
3286 address,
3287 opcode, instruction->info.rt, instruction->info.ra);
3288 break;
3289 case 12:
3290 case 13:
3291 case 14:
3292 case 15: /* LWI37, SWI37 */
3293 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3294 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2;
3295 instruction->type = NDS32_INSN_LOAD_STORE;
3296 nds32_get_mapped_reg(nds32, R28, &(instruction->access_start));
3297 instruction->access_start += instruction->info.imm;
3298 instruction->access_end = instruction->access_start + 4;
3299 if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37 */
3300 snprintf(instruction->text,
3301 128,
3302 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3303 "\t\tLWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]",
3304 address,
3305 opcode, instruction->info.rt, instruction->info.imm);
3306 } else { /* SWI37 */
3307 snprintf(instruction->text,
3308 128,
3309 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3310 "\t\tSWI37\t$r%" PRIu8 ",[fp+#%" PRId32 "]",
3311 address,
3312 opcode, instruction->info.rt, instruction->info.imm);
3313 }
3314 break;
3315 default: /* ERROR */
3316 snprintf(instruction->text,
3317 128,
3318 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3319 address,
3320 opcode);
3321 return ERROR_FAIL;
3322 }
3323
3324 return ERROR_OK;
3325 }
3326
3327 static int nds32_parse_group_2_insn_16(struct nds32 *nds32, uint16_t opcode,
3328 uint32_t address, struct nds32_instruction *instruction)
3329 {
3330 switch ((opcode >> 11) & 0x3) {
3331 case 0: /* BEQZ38 */
3332 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3333 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3334 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3335 instruction->type = NDS32_INSN_JUMP_BRANCH;
3336 snprintf(instruction->text,
3337 128,
3338 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3339 "\t\tBEQZ38\t$r%" PRIu8 ",#%" PRId32,
3340 address,
3341 opcode, instruction->info.rt, instruction->info.imm);
3342 break;
3343 case 1: /* BNEZ38 */
3344 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3345 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3346 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3347 instruction->type = NDS32_INSN_JUMP_BRANCH;
3348 snprintf(instruction->text,
3349 128,
3350 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3351 "\t\tBNEZ38\t$r%" PRIu8 ",#%" PRId32,
3352 address,
3353 opcode, instruction->info.rt, instruction->info.imm);
3354 break;
3355 case 2: /* BEQS38,J8 */
3356 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3357 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3358 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3359 instruction->type = NDS32_INSN_JUMP_BRANCH;
3360 if (instruction->info.rt == 5) { /* J8 */
3361 snprintf(instruction->text,
3362 128,
3363 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3364 "\t\tJ8\t#%" PRId32,
3365 address,
3366 opcode, instruction->info.imm);
3367 } else { /* BEQS38 */
3368 snprintf(instruction->text,
3369 128,
3370 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3371 "\t\tBEQS38\t$r%" PRIu8 ",#%" PRId32,
3372 address,
3373 opcode, instruction->info.rt, instruction->info.imm);
3374 }
3375 break;
3376 case 3: /* BNES38, JR5, RET5, JRAL5 */
3377 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3378 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3379 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3380 instruction->type = NDS32_INSN_JUMP_BRANCH;
3381 if (instruction->info.rt == 5) {
3382 instruction->info.imm = 0;
3383 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3384 switch (nds32_extract_field_8u(opcode, 5, 3)) {
3385 case 0: /* JR5 */
3386 snprintf(instruction->text,
3387 128,
3388 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3389 "\t\tJR5\t$r%" PRIu8,
3390 address,
3391 opcode, instruction->info.rb);
3392 break;
3393 case 1: /* JRAL5 */
3394 snprintf(instruction->text,
3395 128,
3396 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3397 "\t\tJRAL5\t$r%" PRIu8,
3398 address,
3399 opcode, instruction->info.rb);
3400 break;
3401 case 2: /* EX9.IT */
3402 instruction->info.rb = 0;
3403 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3404 /* TODO: implement real instruction semantics */
3405 snprintf(instruction->text,
3406 128,
3407 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3408 "\t\tEX9.IT\t#%" PRId32,
3409 address,
3410 opcode, instruction->info.imm);
3411 break;
3412 case 4: /* RET5 */
3413 snprintf(instruction->text,
3414 128,
3415 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3416 "\t\tRET5\t$r%" PRIu8,
3417 address,
3418 opcode, instruction->info.rb);
3419 break;
3420 case 5: /* ADD5.PC */
3421 instruction->info.rt = 0;
3422 instruction->info.rt = nds32_extract_field_8u(opcode, 0, 5);
3423 instruction->type = NDS32_INSN_DATA_PROC;
3424 snprintf(instruction->text,
3425 128,
3426 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3427 "\t\tADD5.PC\t$r%" PRIu8,
3428 address,
3429 opcode, instruction->info.rt);
3430 break;
3431 default:
3432 snprintf(instruction->text,
3433 128,
3434 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16
3435 "\tUNDEFINED INSTRUCTION",
3436 address,
3437 opcode);
3438 return ERROR_FAIL;
3439 }
3440 } else { /* BNES38 */
3441 snprintf(instruction->text,
3442 128,
3443 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3444 "\t\tBNES38\t$r%" PRIu8 ",#%" PRId32,
3445 address,
3446 opcode, instruction->info.rt, instruction->info.imm);
3447 }
3448 break;
3449 }
3450
3451 return ERROR_OK;
3452 }
3453
3454 static int nds32_parse_group_3_insn_16(struct nds32 *nds32, uint16_t opcode,
3455 uint32_t address, struct nds32_instruction *instruction)
3456 {
3457 switch ((opcode >> 11) & 0x3) {
3458 case 0:
3459 switch ((opcode >> 9) & 0x3) {
3460 case 0: /* SLTS45 */
3461 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3462 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3463 instruction->type = NDS32_INSN_DATA_PROC;
3464 snprintf(instruction->text,
3465 128,
3466 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3467 "\t\tSLTS45\t$r%" PRIu8 ",$r%" PRIu8,
3468 address,
3469 opcode, instruction->info.ra, instruction->info.rb);
3470 break;
3471 case 1: /* SLT45 */
3472 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3473 instruction->info.rb = nds32_extract_field_8u(opcode, 0, 5);
3474 instruction->type = NDS32_INSN_DATA_PROC;
3475 snprintf(instruction->text,
3476 128,
3477 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3478 "\t\tSLT45\t$r%" PRIu8 ",$r%" PRIu8,
3479 address,
3480 opcode, instruction->info.ra, instruction->info.rb);
3481 break;
3482 case 2: /* SLTSI45 */
3483 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3484 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3485 instruction->type = NDS32_INSN_DATA_PROC;
3486 snprintf(instruction->text,
3487 128,
3488 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3489 "\t\tSLTSI45\t$r%" PRIu8 ",#%" PRId32,
3490 address,
3491 opcode, instruction->info.ra, instruction->info.imm);
3492 break;
3493 case 3: /* SLTI45 */
3494 instruction->info.ra = nds32_extract_field_8u(opcode, 5, 4);
3495 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5);
3496 instruction->type = NDS32_INSN_DATA_PROC;
3497 snprintf(instruction->text,
3498 128,
3499 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3500 "\t\tSLTI45\t$r%" PRIu8 ",#%" PRId32,
3501 address,
3502 opcode, instruction->info.ra, instruction->info.imm);
3503 break;
3504 }
3505 break;
3506 case 1:
3507 switch ((opcode >> 9) & 0x3) {
3508 case 0:
3509 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 8);
3510 instruction->info.imm = (instruction->info.imm << 24) >> 24;
3511 instruction->type = NDS32_INSN_JUMP_BRANCH;
3512 if (nds32_extract_field_8u(opcode, 8, 1) == 0) { /* BEQZS8 */
3513 snprintf(instruction->text,
3514 128,
3515 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3516 "\t\tBEQZS8\t#%" PRId32,
3517 address,
3518 opcode, instruction->info.imm);
3519 } else { /* BNEZS8 */
3520 snprintf(instruction->text,
3521 128,
3522 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3523 "\t\tBNEZS8\t#%" PRId32,
3524 address,
3525 opcode, instruction->info.imm);
3526 }
3527 break;
3528 case 1: /* BREAK16 */
3529 if (((opcode >> 5) & 0xF) == 0) {
3530 instruction->type = NDS32_INSN_MISC;
3531 snprintf(instruction->text,
3532 128,
3533 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3534 "\t\tBREAK16\t#%" PRId16,
3535 address,
3536 opcode, (int16_t)(opcode & 0x1F));
3537 } else { /* EX9.IT */
3538 instruction->type = NDS32_INSN_MISC;
3539 /* TODO: implement real instruction semantics */
3540 snprintf(instruction->text,
3541 128,
3542 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3543 "\t\tEX9.IT\t#%" PRId16,
3544 address,
3545 opcode, (int16_t)(opcode & 0x1FF));
3546 }
3547 break;
3548 case 2: /* ADDI10S */
3549 case 3:
3550 instruction->info.imm = opcode & 0x3FF;
3551 instruction->info.imm = (instruction->info.imm << 22) >> 22;
3552 instruction->type = NDS32_INSN_DATA_PROC;
3553 snprintf(instruction->text,
3554 128,
3555 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3556 "\t\tADDI10.SP\t#%" PRId32,
3557 address,
3558 opcode, instruction->info.imm);
3559 break;
3560 }
3561 break;
3562 case 2:
3563 instruction->info.rt = nds32_extract_field_8u(opcode, 8, 3);
3564 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 7) << 2;
3565 instruction->type = NDS32_INSN_LOAD_STORE;
3566 nds32_get_mapped_reg(nds32, R31, &(instruction->access_start));
3567 instruction->access_start += instruction->info.imm;
3568 instruction->access_end = instruction->access_start + 4;
3569 if (nds32_extract_field_8u(opcode, 7, 1) == 0) { /* LWI37.SP */
3570 snprintf(instruction->text,
3571 128,
3572 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3573 "\t\tLWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]",
3574 address,
3575 opcode, instruction->info.rt, instruction->info.imm);
3576 } else { /* SWI37.SP */
3577 snprintf(instruction->text,
3578 128,
3579 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3580 "\t\tSWI37.SP\t$r%" PRIu8 ",[+#%" PRId32 "]",
3581 address,
3582 opcode, instruction->info.rt, instruction->info.imm);
3583 }
3584 break;
3585 case 3:
3586 switch ((opcode >> 9) & 0x3) {
3587 case 0: /* IFCALL9 */
3588 instruction->info.imm = opcode & 0x1FF;
3589 instruction->type = NDS32_INSN_JUMP_BRANCH;
3590 snprintf(instruction->text,
3591 128,
3592 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3593 "\t\tIFCALL9\t#%" PRId32 "",
3594 address,
3595 opcode, instruction->info.imm);
3596 break;
3597 case 1: /* MOVPI45 */
3598 instruction->info.imm = nds32_extract_field_8u(opcode, 0, 5) + 16;
3599 instruction->info.rt = nds32_extract_field_8u(opcode, 5, 4);
3600 instruction->type = NDS32_INSN_MISC;
3601 snprintf(instruction->text,
3602 128,
3603 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3604 "\t\tMOVPI45\t$r%" PRIu8 ",#%" PRId32 "",
3605 address,
3606 opcode, instruction->info.rt, instruction->info.imm);
3607 break;
3608 case 2: /* PUSH25, POP25, MOVD44 */
3609 switch ((opcode >> 7) & 0x3) {
3610 case 0: /* PUSH25 */
3611 {
3612 uint8_t re;
3613 uint8_t gpr_count;
3614
3615 instruction->type = NDS32_INSN_LOAD_STORE;
3616 instruction->info.imm =
3617 nds32_extract_field_8u(opcode, 0, 5) << 3;
3618 re = nds32_extract_field_8u(opcode, 5, 2);
3619
3620 if (re == 0)
3621 re = 6;
3622 else if (re == 1)
3623 re = 8;
3624 else if (re == 2)
3625 re = 10;
3626 else if (re == 3)
3627 re = 14;
3628
3629 instruction->info.rd = re;
3630 /* GPRs list: R6 ~ Re and fp, gp, lp */
3631 gpr_count = 3 + (re - 5);
3632
3633 nds32_get_mapped_reg(nds32, R31,
3634 &(instruction->access_end));
3635 instruction->access_start =
3636 instruction->access_end - (gpr_count * 4);
3637
3638 snprintf(instruction->text,
3639 128,
3640 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3641 "\t\tPUSH25\t$r%" PRIu8 ",#%" PRId32,
3642 address,
3643 opcode, instruction->info.rd,
3644 instruction->info.imm);
3645 }
3646 break;
3647 case 1: /* POP25 */
3648 {
3649 uint8_t re;
3650 uint8_t gpr_count;
3651
3652 instruction->type = NDS32_INSN_LOAD_STORE;
3653 instruction->info.imm =
3654 nds32_extract_field_8u(opcode, 0, 5) << 3;
3655 re = nds32_extract_field_8u(opcode, 5, 2);
3656
3657 if (re == 0)
3658 re = 6;
3659 else if (re == 1)
3660 re = 8;
3661 else if (re == 2)
3662 re = 10;
3663 else if (re == 3)
3664 re = 14;
3665
3666 instruction->info.rd = re;
3667 /* GPRs list: R6 ~ Re and fp, gp, lp */
3668 gpr_count = 3 + (re - 5);
3669
3670 nds32_get_mapped_reg(nds32, R31,
3671 &(instruction->access_start));
3672 instruction->access_start += instruction->info.imm;
3673 instruction->access_end =
3674 instruction->access_start + (gpr_count * 4);
3675
3676 snprintf(instruction->text,
3677 128,
3678 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3679 "\t\tPOP25\t$r%" PRIu8 ",#%" PRId32,
3680 address,
3681 opcode, instruction->info.rd,
3682 instruction->info.imm);
3683 }
3684 break;
3685 case 2: /* MOVD44 */
3686 case 3:
3687 instruction->info.ra =
3688 nds32_extract_field_8u(opcode, 0, 4) * 2;
3689 instruction->info.rt =
3690 nds32_extract_field_8u(opcode, 4, 4) * 2;
3691 instruction->type = NDS32_INSN_MISC;
3692 snprintf(instruction->text,
3693 128,
3694 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3695 "\t\tMOVD44\t$r%" PRIu8 ",$r%" PRIu8,
3696 address,
3697 opcode, instruction->info.rt, instruction->info.ra);
3698 break;
3699 }
3700 break;
3701 case 3: /* NEG33, NOT33, MUL33, XOR33, AND33, OR33 */
3702 instruction->info.ra = nds32_extract_field_8u(opcode, 3, 3);
3703 instruction->info.rt = nds32_extract_field_8u(opcode, 6, 3);
3704 instruction->type = NDS32_INSN_DATA_PROC;
3705 switch (opcode & 0x7) {
3706 case 2: /* NEG33 */
3707 snprintf(instruction->text,
3708 128,
3709 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3710 "\t\tNEG33\t$r%" PRIu8 ",$r%" PRIu8,
3711 address,
3712 opcode, instruction->info.rt, instruction->info.ra);
3713 break;
3714 case 3: /* NOT33 */
3715 snprintf(instruction->text,
3716 128,
3717 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3718 "\t\tNOT33\t$r%" PRIu8 ",$r%" PRIu8,
3719 address,
3720 opcode, instruction->info.rt, instruction->info.ra);
3721 break;
3722 case 4: /* MUL33 */
3723 snprintf(instruction->text,
3724 128,
3725 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3726 "\t\tMUL33\t$r%" PRIu8 ",$r%" PRIu8,
3727 address,
3728 opcode, instruction->info.rt, instruction->info.ra);
3729 break;
3730 case 5: /* XOR33 */
3731 snprintf(instruction->text,
3732 128,
3733 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3734 "\t\tXOR33\t$r%" PRIu8 ",$r%" PRIu8,
3735 address,
3736 opcode, instruction->info.rt, instruction->info.ra);
3737 break;
3738 case 6: /* AND33 */
3739 snprintf(instruction->text,
3740 128,
3741 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3742 "\t\tAND33\t$r%" PRIu8 ",$r%" PRIu8,
3743 address,
3744 opcode, instruction->info.rt, instruction->info.ra);
3745 break;
3746 case 7: /* OR33 */
3747 snprintf(instruction->text,
3748 128,
3749 "0x%8.8" PRIx32 "\t0x%4.4" PRIx16
3750 "\t\tOR33\t$r%" PRIu8 ",$r%" PRIu8,
3751 address,
3752 opcode, instruction->info.rt, instruction->info.ra);
3753 break;
3754 }
3755 break;
3756 }
3757 break;
3758 default:
3759 snprintf(instruction->text,
3760 128,
3761 "0x%8.8" PRIx32 "\t0x%8.8" PRIx16 "\tUNDEFINED INSTRUCTION",
3762 address,
3763 opcode);
3764 return ERROR_FAIL;
3765 }
3766
3767 return ERROR_OK;
3768 }
3769
3770 int nds32_evaluate_opcode(struct nds32 *nds32, uint32_t opcode, uint32_t address,
3771 struct nds32_instruction *instruction)
3772 {
3773 int retval = ERROR_OK;
3774
3775 /* clear fields, to avoid confusion */
3776 memset(instruction, 0, sizeof(struct nds32_instruction));
3777
3778 if (opcode >> 31) {
3779 /* 16 bits instruction */
3780 instruction->instruction_size = 2;
3781 opcode = (opcode >> 16) & 0xFFFF;
3782 instruction->opcode = opcode;
3783
3784 switch ((opcode >> 13) & 0x3) {
3785 case 0:
3786 retval = nds32_parse_group_0_insn_16(nds32, opcode, address, instruction);
3787 break;
3788 case 1:
3789 retval = nds32_parse_group_1_insn_16(nds32, opcode, address, instruction);
3790 break;
3791 case 2:
3792 retval = nds32_parse_group_2_insn_16(nds32, opcode, address, instruction);
3793 break;
3794 case 3:
3795 retval = nds32_parse_group_3_insn_16(nds32, opcode, address, instruction);
3796 break;
3797 default:
3798 snprintf(instruction->text,
3799 128,
3800 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
3801 address,
3802 opcode);
3803 return ERROR_FAIL;
3804 }
3805 } else {
3806 /* 32 bits instruction */
3807 instruction->instruction_size = 4;
3808 instruction->opcode = opcode;
3809
3810 uint8_t opc_6;
3811 opc_6 = opcode >> 25;
3812 instruction->info.opc_6 = opc_6;
3813
3814 switch ((opc_6 >> 3) & 0x7) {
3815 case 0: /* LBI, LHI, LWI, LBI.bi, LHI.bi, LWI.bi */
3816 retval = nds32_parse_group_0_insn(nds32, opcode, address, instruction);
3817 break;
3818 case 1: /* SBI, SHI, SWI, SBI.bi, SHI.bi, SWI.bi */
3819 retval = nds32_parse_group_1_insn(nds32, opcode, address, instruction);
3820 break;
3821 case 2: /* LBSI, LHSI, DPREFI, LBSI.bi, LHSI.bi, LBGP */
3822 retval = nds32_parse_group_2_insn(nds32, opcode, address, instruction);
3823 break;
3824 case 3: /* MEM, LSMW, HWGP, SBGP */
3825 retval = nds32_parse_group_3_insn(nds32, opcode, address, instruction);
3826 break;
3827 case 4: /* ALU_1, ALU_2, MOVI, SETHI, JI, JREG, BR1, BR2 */
3828 retval = nds32_parse_group_4_insn(nds32, opcode, address, instruction);
3829 break;
3830 case 5: /* ADDI, SUBRI, ANDI, XORI, ORI, SLTI, SLTSI */
3831 retval = nds32_parse_group_5_insn(nds32, opcode, address, instruction);
3832 break;
3833 case 6: /* MISC */
3834 retval = nds32_parse_group_6_insn(nds32, opcode, address, instruction);
3835 break;
3836 default: /* ERROR */
3837 snprintf(instruction->text,
3838 128,
3839 "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION",
3840 address,
3841 opcode);
3842 return ERROR_FAIL;
3843 }
3844 }
3845
3846 return retval;
3847 }
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