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target/armv7m: Use 'bool' data type
[openocd.git] / src / target / armv7m.c
blob3d73b295441c44890baeb5ea65e282c0b9a75d7c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
13 * *
14 * Copyright (C) 2018 by Liviu Ionescu *
15 * <ilg@livius.net> *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 * *
30 * ARMv7-M Architecture, Application Level Reference Manual *
31 * ARM DDI 0405C (September 2008) *
32 * *
33 ***************************************************************************/
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "breakpoints.h"
40 #include "armv7m.h"
41 #include "algorithm.h"
42 #include "register.h"
43 #include "semihosting_common.h"
44
45 #if 0
46 #define _DEBUG_INSTRUCTION_EXECUTION_
47 #endif
48
49 static const char * const armv7m_exception_strings[] = {
50 "", "Reset", "NMI", "HardFault",
51 "MemManage", "BusFault", "UsageFault", "RESERVED",
52 "RESERVED", "RESERVED", "RESERVED", "SVCall",
53 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
54 };
55
56 /* PSP is used in some thread modes */
57 const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
58 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
59 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
60 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
61 ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
62 ARMV7M_xPSR,
63 };
64
65 /* MSP is used in handler and some thread modes */
66 const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
67 ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
68 ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
69 ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
70 ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
71 ARMV7M_xPSR,
72 };
73
74 /*
75 * These registers are not memory-mapped. The ARMv7-M profile includes
76 * memory mapped registers too, such as for the NVIC (interrupt controller)
77 * and SysTick (timer) modules; those can mostly be treated as peripherals.
78 *
79 * The ARMv6-M profile is almost identical in this respect, except that it
80 * doesn't include basepri or faultmask registers.
81 */
82 static const struct {
83 unsigned id;
84 const char *name;
85 unsigned bits;
86 enum reg_type type;
87 const char *group;
88 const char *feature;
89 } armv7m_regs[] = {
90 { ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
91 { ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
92 { ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
93 { ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
94 { ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
95 { ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
96 { ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
97 { ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
98 { ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
99 { ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
100 { ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
101 { ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
102 { ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
103 { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
104 { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
105 { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
106 { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
107
108 { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
109 { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
110
111 { ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
112 { ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
113 { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
114 { ARMV7M_CONTROL, "control", 2, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
115
116 { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
117 { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
118 { ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
119 { ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
120 { ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
121 { ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
122 { ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
123 { ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
124 { ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
125 { ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
126 { ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
127 { ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
128 { ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
129 { ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
130 { ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
131 { ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
132
133 { ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp" },
134 };
135
136 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
137
138 /**
139 * Restores target context using the cache of core registers set up
140 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
141 */
142 int armv7m_restore_context(struct target *target)
143 {
144 int i;
145 struct armv7m_common *armv7m = target_to_armv7m(target);
146 struct reg_cache *cache = armv7m->arm.core_cache;
147
148 LOG_DEBUG(" ");
149
150 if (armv7m->pre_restore_context)
151 armv7m->pre_restore_context(target);
152
153 for (i = cache->num_regs - 1; i >= 0; i--) {
154 if (cache->reg_list[i].dirty) {
155 armv7m->arm.write_core_reg(target, &cache->reg_list[i], i,
156 ARM_MODE_ANY, cache->reg_list[i].value);
157 }
158 }
159
160 return ERROR_OK;
161 }
162
163 /* Core state functions */
164
165 /**
166 * Maps ISR number (from xPSR) to name.
167 * Note that while names and meanings for the first sixteen are standardized
168 * (with zero not a true exception), external interrupts are only numbered.
169 * They are assigned by vendors, which generally assign different numbers to
170 * peripherals (such as UART0 or a USB peripheral controller).
171 */
172 const char *armv7m_exception_string(int number)
173 {
174 static char enamebuf[32];
175
176 if ((number < 0) | (number > 511))
177 return "Invalid exception";
178 if (number < 16)
179 return armv7m_exception_strings[number];
180 sprintf(enamebuf, "External Interrupt(%i)", number - 16);
181 return enamebuf;
182 }
183
184 static int armv7m_get_core_reg(struct reg *reg)
185 {
186 int retval;
187 struct arm_reg *armv7m_reg = reg->arch_info;
188 struct target *target = armv7m_reg->target;
189 struct arm *arm = target_to_arm(target);
190
191 if (target->state != TARGET_HALTED)
192 return ERROR_TARGET_NOT_HALTED;
193
194 retval = arm->read_core_reg(target, reg, armv7m_reg->num, arm->core_mode);
195
196 return retval;
197 }
198
199 static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
200 {
201 struct arm_reg *armv7m_reg = reg->arch_info;
202 struct target *target = armv7m_reg->target;
203
204 if (target->state != TARGET_HALTED)
205 return ERROR_TARGET_NOT_HALTED;
206
207 buf_cpy(buf, reg->value, reg->size);
208 reg->dirty = true;
209 reg->valid = true;
210
211 return ERROR_OK;
212 }
213
214 static int armv7m_read_core_reg(struct target *target, struct reg *r,
215 int num, enum arm_mode mode)
216 {
217 uint32_t reg_value;
218 int retval;
219 struct arm_reg *armv7m_core_reg;
220 struct armv7m_common *armv7m = target_to_armv7m(target);
221
222 assert(num < (int)armv7m->arm.core_cache->num_regs);
223
224 armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
225
226 if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
227 /* map D0..D15 to S0..S31 */
228 size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
229 retval = armv7m->load_core_reg_u32(target, regidx, &reg_value);
230 if (retval != ERROR_OK)
231 return retval;
232 buf_set_u32(armv7m->arm.core_cache->reg_list[num].value,
233 0, 32, reg_value);
234 retval = armv7m->load_core_reg_u32(target, regidx + 1, &reg_value);
235 if (retval != ERROR_OK)
236 return retval;
237 buf_set_u32(armv7m->arm.core_cache->reg_list[num].value + 4,
238 0, 32, reg_value);
239 } else {
240 retval = armv7m->load_core_reg_u32(target,
241 armv7m_core_reg->num, &reg_value);
242 if (retval != ERROR_OK)
243 return retval;
244 buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
245 }
246
247 armv7m->arm.core_cache->reg_list[num].valid = true;
248 armv7m->arm.core_cache->reg_list[num].dirty = false;
249
250 return retval;
251 }
252
253 static int armv7m_write_core_reg(struct target *target, struct reg *r,
254 int num, enum arm_mode mode, uint8_t *value)
255 {
256 int retval;
257 struct arm_reg *armv7m_core_reg;
258 struct armv7m_common *armv7m = target_to_armv7m(target);
259
260 assert(num < (int)armv7m->arm.core_cache->num_regs);
261
262 armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
263
264 if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
265 /* map D0..D15 to S0..S31 */
266 size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
267
268 uint32_t t = buf_get_u32(value, 0, 32);
269 retval = armv7m->store_core_reg_u32(target, regidx, t);
270 if (retval != ERROR_OK)
271 goto out_error;
272
273 t = buf_get_u32(value + 4, 0, 32);
274 retval = armv7m->store_core_reg_u32(target, regidx + 1, t);
275 if (retval != ERROR_OK)
276 goto out_error;
277 } else {
278 uint32_t t = buf_get_u32(value, 0, 32);
279
280 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, t);
281 retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->num, t);
282 if (retval != ERROR_OK)
283 goto out_error;
284 }
285
286 armv7m->arm.core_cache->reg_list[num].valid = true;
287 armv7m->arm.core_cache->reg_list[num].dirty = false;
288
289 return ERROR_OK;
290
291 out_error:
292 LOG_ERROR("Error setting register");
293 armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
294 return ERROR_JTAG_DEVICE_ERROR;
295 }
296
297 /**
298 * Returns generic ARM userspace registers to GDB.
299 */
300 int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
301 int *reg_list_size, enum target_register_class reg_class)
302 {
303 struct armv7m_common *armv7m = target_to_armv7m(target);
304 int i;
305
306 if (reg_class == REG_CLASS_ALL)
307 *reg_list_size = armv7m->arm.core_cache->num_regs;
308 else
309 *reg_list_size = ARMV7M_NUM_CORE_REGS;
310
311 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
312 if (*reg_list == NULL)
313 return ERROR_FAIL;
314
315 for (i = 0; i < *reg_list_size; i++)
316 (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
317
318 return ERROR_OK;
319 }
320
321 /** Runs a Thumb algorithm in the target. */
322 int armv7m_run_algorithm(struct target *target,
323 int num_mem_params, struct mem_param *mem_params,
324 int num_reg_params, struct reg_param *reg_params,
325 target_addr_t entry_point, target_addr_t exit_point,
326 int timeout_ms, void *arch_info)
327 {
328 int retval;
329
330 retval = armv7m_start_algorithm(target,
331 num_mem_params, mem_params,
332 num_reg_params, reg_params,
333 entry_point, exit_point,
334 arch_info);
335
336 if (retval == ERROR_OK)
337 retval = armv7m_wait_algorithm(target,
338 num_mem_params, mem_params,
339 num_reg_params, reg_params,
340 exit_point, timeout_ms,
341 arch_info);
342
343 return retval;
344 }
345
346 /** Starts a Thumb algorithm in the target. */
347 int armv7m_start_algorithm(struct target *target,
348 int num_mem_params, struct mem_param *mem_params,
349 int num_reg_params, struct reg_param *reg_params,
350 target_addr_t entry_point, target_addr_t exit_point,
351 void *arch_info)
352 {
353 struct armv7m_common *armv7m = target_to_armv7m(target);
354 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
355 enum arm_mode core_mode = armv7m->arm.core_mode;
356 int retval = ERROR_OK;
357
358 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
359 * at the exit point */
360
361 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
362 LOG_ERROR("current target isn't an ARMV7M target");
363 return ERROR_TARGET_INVALID;
364 }
365
366 if (target->state != TARGET_HALTED) {
367 LOG_WARNING("target not halted");
368 return ERROR_TARGET_NOT_HALTED;
369 }
370
371 /* refresh core register cache
372 * Not needed if core register cache is always consistent with target process state */
373 for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
374
375 armv7m_algorithm_info->context[i] = buf_get_u32(
376 armv7m->arm.core_cache->reg_list[i].value,
377 0,
378 32);
379 }
380
381 for (int i = 0; i < num_mem_params; i++) {
382 if (mem_params[i].direction == PARAM_IN)
383 continue;
384 retval = target_write_buffer(target, mem_params[i].address,
385 mem_params[i].size,
386 mem_params[i].value);
387 if (retval != ERROR_OK)
388 return retval;
389 }
390
391 for (int i = 0; i < num_reg_params; i++) {
392 if (reg_params[i].direction == PARAM_IN)
393 continue;
394
395 struct reg *reg =
396 register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
397 /* uint32_t regvalue; */
398
399 if (!reg) {
400 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
401 return ERROR_COMMAND_SYNTAX_ERROR;
402 }
403
404 if (reg->size != reg_params[i].size) {
405 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
406 reg_params[i].reg_name);
407 return ERROR_COMMAND_SYNTAX_ERROR;
408 }
409
410 /* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
411 armv7m_set_core_reg(reg, reg_params[i].value);
412 }
413
414 {
415 /*
416 * Ensure xPSR.T is set to avoid trying to run things in arm
417 * (non-thumb) mode, which armv7m does not support.
418 *
419 * We do this by setting the entirety of xPSR, which should
420 * remove all the unknowns about xPSR state.
421 *
422 * Because xPSR.T is populated on reset from the vector table,
423 * it might be 0 if the vector table has "bad" data in it.
424 */
425 struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
426 buf_set_u32(reg->value, 0, 32, 0x01000000);
427 reg->valid = true;
428 reg->dirty = true;
429 }
430
431 if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
432 armv7m_algorithm_info->core_mode != core_mode) {
433
434 /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
435 if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
436 armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
437 LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
438 }
439
440 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
441 buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
442 0, 1, armv7m_algorithm_info->core_mode);
443 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
444 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
445 }
446
447 /* save previous core mode */
448 armv7m_algorithm_info->core_mode = core_mode;
449
450 retval = target_resume(target, 0, entry_point, 1, 1);
451
452 return retval;
453 }
454
455 /** Waits for an algorithm in the target. */
456 int armv7m_wait_algorithm(struct target *target,
457 int num_mem_params, struct mem_param *mem_params,
458 int num_reg_params, struct reg_param *reg_params,
459 target_addr_t exit_point, int timeout_ms,
460 void *arch_info)
461 {
462 struct armv7m_common *armv7m = target_to_armv7m(target);
463 struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
464 int retval = ERROR_OK;
465 uint32_t pc;
466
467 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
468 * at the exit point */
469
470 if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
471 LOG_ERROR("current target isn't an ARMV7M target");
472 return ERROR_TARGET_INVALID;
473 }
474
475 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
476 /* If the target fails to halt due to the breakpoint, force a halt */
477 if (retval != ERROR_OK || target->state != TARGET_HALTED) {
478 retval = target_halt(target);
479 if (retval != ERROR_OK)
480 return retval;
481 retval = target_wait_state(target, TARGET_HALTED, 500);
482 if (retval != ERROR_OK)
483 return retval;
484 return ERROR_TARGET_TIMEOUT;
485 }
486
487 armv7m->load_core_reg_u32(target, 15, &pc);
488 if (exit_point && (pc != exit_point)) {
489 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
490 pc,
491 exit_point);
492 return ERROR_TARGET_TIMEOUT;
493 }
494
495 /* Read memory values to mem_params[] */
496 for (int i = 0; i < num_mem_params; i++) {
497 if (mem_params[i].direction != PARAM_OUT) {
498 retval = target_read_buffer(target, mem_params[i].address,
499 mem_params[i].size,
500 mem_params[i].value);
501 if (retval != ERROR_OK)
502 return retval;
503 }
504 }
505
506 /* Copy core register values to reg_params[] */
507 for (int i = 0; i < num_reg_params; i++) {
508 if (reg_params[i].direction != PARAM_OUT) {
509 struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
510 reg_params[i].reg_name,
511 0);
512
513 if (!reg) {
514 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
515 return ERROR_COMMAND_SYNTAX_ERROR;
516 }
517
518 if (reg->size != reg_params[i].size) {
519 LOG_ERROR(
520 "BUG: register '%s' size doesn't match reg_params[i].size",
521 reg_params[i].reg_name);
522 return ERROR_COMMAND_SYNTAX_ERROR;
523 }
524
525 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
526 }
527 }
528
529 for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
530 uint32_t regvalue;
531 regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
532 if (regvalue != armv7m_algorithm_info->context[i]) {
533 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
534 armv7m->arm.core_cache->reg_list[i].name,
535 armv7m_algorithm_info->context[i]);
536 buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
537 0, 32, armv7m_algorithm_info->context[i]);
538 armv7m->arm.core_cache->reg_list[i].valid = true;
539 armv7m->arm.core_cache->reg_list[i].dirty = true;
540 }
541 }
542
543 /* restore previous core mode */
544 if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
545 LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
546 buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
547 0, 1, armv7m_algorithm_info->core_mode);
548 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
549 armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
550 }
551
552 armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
553
554 return retval;
555 }
556
557 /** Logs summary of ARMv7-M state for a halted target. */
558 int armv7m_arch_state(struct target *target)
559 {
560 struct armv7m_common *armv7m = target_to_armv7m(target);
561 struct arm *arm = &armv7m->arm;
562 uint32_t ctrl, sp;
563
564 /* avoid filling log waiting for fileio reply */
565 if (target->semihosting && target->semihosting->hit_fileio)
566 return ERROR_OK;
567
568 ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
569 sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
570
571 LOG_USER("target halted due to %s, current mode: %s %s\n"
572 "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
573 debug_reason_name(target),
574 arm_mode_name(arm->core_mode),
575 armv7m_exception_string(armv7m->exception_number),
576 buf_get_u32(arm->cpsr->value, 0, 32),
577 buf_get_u32(arm->pc->value, 0, 32),
578 (ctrl & 0x02) ? 'p' : 'm',
579 sp,
580 (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
581 (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
582
583 return ERROR_OK;
584 }
585
586 static const struct reg_arch_type armv7m_reg_type = {
587 .get = armv7m_get_core_reg,
588 .set = armv7m_set_core_reg,
589 };
590
591 /** Builds cache of architecturally defined registers. */
592 struct reg_cache *armv7m_build_reg_cache(struct target *target)
593 {
594 struct armv7m_common *armv7m = target_to_armv7m(target);
595 struct arm *arm = &armv7m->arm;
596 int num_regs = ARMV7M_NUM_REGS;
597 struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
598 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
599 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
600 struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
601 struct reg_feature *feature;
602 int i;
603
604 /* Build the process context cache */
605 cache->name = "arm v7m registers";
606 cache->next = NULL;
607 cache->reg_list = reg_list;
608 cache->num_regs = num_regs;
609 (*cache_p) = cache;
610
611 for (i = 0; i < num_regs; i++) {
612 arch_info[i].num = armv7m_regs[i].id;
613 arch_info[i].target = target;
614 arch_info[i].arm = arm;
615
616 reg_list[i].name = armv7m_regs[i].name;
617 reg_list[i].size = armv7m_regs[i].bits;
618 size_t storage_size = DIV_ROUND_UP(armv7m_regs[i].bits, 8);
619 if (storage_size < 4)
620 storage_size = 4;
621 reg_list[i].value = calloc(1, storage_size);
622 reg_list[i].dirty = false;
623 reg_list[i].valid = false;
624 reg_list[i].type = &armv7m_reg_type;
625 reg_list[i].arch_info = &arch_info[i];
626
627 reg_list[i].group = armv7m_regs[i].group;
628 reg_list[i].number = i;
629 reg_list[i].exist = true;
630 reg_list[i].caller_save = true; /* gdb defaults to true */
631
632 feature = calloc(1, sizeof(struct reg_feature));
633 if (feature) {
634 feature->name = armv7m_regs[i].feature;
635 reg_list[i].feature = feature;
636 } else
637 LOG_ERROR("unable to allocate feature list");
638
639 reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
640 if (reg_list[i].reg_data_type)
641 reg_list[i].reg_data_type->type = armv7m_regs[i].type;
642 else
643 LOG_ERROR("unable to allocate reg type list");
644 }
645
646 arm->cpsr = reg_list + ARMV7M_xPSR;
647 arm->pc = reg_list + ARMV7M_PC;
648 arm->core_cache = cache;
649
650 return cache;
651 }
652
653 void armv7m_free_reg_cache(struct target *target)
654 {
655 struct armv7m_common *armv7m = target_to_armv7m(target);
656 struct arm *arm = &armv7m->arm;
657 struct reg_cache *cache;
658 struct reg *reg;
659 unsigned int i;
660
661 cache = arm->core_cache;
662
663 if (!cache)
664 return;
665
666 for (i = 0; i < cache->num_regs; i++) {
667 reg = &cache->reg_list[i];
668
669 free(reg->feature);
670 free(reg->reg_data_type);
671 free(reg->value);
672 }
673
674 free(cache->reg_list[0].arch_info);
675 free(cache->reg_list);
676 free(cache);
677
678 arm->core_cache = NULL;
679 }
680
681 static int armv7m_setup_semihosting(struct target *target, int enable)
682 {
683 /* nothing todo for armv7m */
684 return ERROR_OK;
685 }
686
687 /** Sets up target as a generic ARMv7-M core */
688 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
689 {
690 struct arm *arm = &armv7m->arm;
691
692 armv7m->common_magic = ARMV7M_COMMON_MAGIC;
693 armv7m->fp_feature = FP_NONE;
694 armv7m->trace_config.trace_bus_id = 1;
695 /* Enable stimulus port #0 by default */
696 armv7m->trace_config.itm_ter[0] = 1;
697
698 arm->core_type = ARM_MODE_THREAD;
699 arm->arch_info = armv7m;
700 arm->setup_semihosting = armv7m_setup_semihosting;
701
702 arm->read_core_reg = armv7m_read_core_reg;
703 arm->write_core_reg = armv7m_write_core_reg;
704
705 return arm_init_arch_info(target, arm);
706 }
707
708 /** Generates a CRC32 checksum of a memory region. */
709 int armv7m_checksum_memory(struct target *target,
710 target_addr_t address, uint32_t count, uint32_t *checksum)
711 {
712 struct working_area *crc_algorithm;
713 struct armv7m_algorithm armv7m_info;
714 struct reg_param reg_params[2];
715 int retval;
716
717 static const uint8_t cortex_m_crc_code[] = {
718 #include "../../contrib/loaders/checksum/armv7m_crc.inc"
719 };
720
721 retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
722 if (retval != ERROR_OK)
723 return retval;
724
725 retval = target_write_buffer(target, crc_algorithm->address,
726 sizeof(cortex_m_crc_code), (uint8_t *)cortex_m_crc_code);
727 if (retval != ERROR_OK)
728 goto cleanup;
729
730 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
731 armv7m_info.core_mode = ARM_MODE_THREAD;
732
733 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
734 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
735
736 buf_set_u32(reg_params[0].value, 0, 32, address);
737 buf_set_u32(reg_params[1].value, 0, 32, count);
738
739 int timeout = 20000 * (1 + (count / (1024 * 1024)));
740
741 retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
742 crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6),
743 timeout, &armv7m_info);
744
745 if (retval == ERROR_OK)
746 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
747 else
748 LOG_ERROR("error executing cortex_m crc algorithm");
749
750 destroy_reg_param(&reg_params[0]);
751 destroy_reg_param(&reg_params[1]);
752
753 cleanup:
754 target_free_working_area(target, crc_algorithm);
755
756 return retval;
757 }
758
759 /** Checks an array of memory regions whether they are erased. */
760 int armv7m_blank_check_memory(struct target *target,
761 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
762 {
763 struct working_area *erase_check_algorithm;
764 struct working_area *erase_check_params;
765 struct reg_param reg_params[2];
766 struct armv7m_algorithm armv7m_info;
767 int retval;
768
769 static bool timed_out;
770
771 static const uint8_t erase_check_code[] = {
772 #include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
773 };
774
775 const uint32_t code_size = sizeof(erase_check_code);
776
777 /* make sure we have a working area */
778 if (target_alloc_working_area(target, code_size,
779 &erase_check_algorithm) != ERROR_OK)
780 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
781
782 retval = target_write_buffer(target, erase_check_algorithm->address,
783 code_size, erase_check_code);
784 if (retval != ERROR_OK)
785 goto cleanup1;
786
787 /* prepare blocks array for algo */
788 struct algo_block {
789 union {
790 uint32_t size;
791 uint32_t result;
792 };
793 uint32_t address;
794 };
795
796 uint32_t avail = target_get_working_area_avail(target);
797 int blocks_to_check = avail / sizeof(struct algo_block) - 1;
798 if (num_blocks < blocks_to_check)
799 blocks_to_check = num_blocks;
800
801 struct algo_block *params = malloc((blocks_to_check+1)*sizeof(struct algo_block));
802 if (params == NULL) {
803 retval = ERROR_FAIL;
804 goto cleanup1;
805 }
806
807 int i;
808 uint32_t total_size = 0;
809 for (i = 0; i < blocks_to_check; i++) {
810 total_size += blocks[i].size;
811 target_buffer_set_u32(target, (uint8_t *)&(params[i].size),
812 blocks[i].size / sizeof(uint32_t));
813 target_buffer_set_u32(target, (uint8_t *)&(params[i].address),
814 blocks[i].address);
815 }
816 target_buffer_set_u32(target, (uint8_t *)&(params[blocks_to_check].size), 0);
817
818 uint32_t param_size = (blocks_to_check + 1) * sizeof(struct algo_block);
819 if (target_alloc_working_area(target, param_size,
820 &erase_check_params) != ERROR_OK) {
821 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
822 goto cleanup2;
823 }
824
825 retval = target_write_buffer(target, erase_check_params->address,
826 param_size, (uint8_t *)params);
827 if (retval != ERROR_OK)
828 goto cleanup3;
829
830 uint32_t erased_word = erased_value | (erased_value << 8)
831 | (erased_value << 16) | (erased_value << 24);
832
833 LOG_DEBUG("Starting erase check of %d blocks, parameters@"
834 TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
835
836 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
837 armv7m_info.core_mode = ARM_MODE_THREAD;
838
839 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
840 buf_set_u32(reg_params[0].value, 0, 32, erase_check_params->address);
841
842 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
843 buf_set_u32(reg_params[1].value, 0, 32, erased_word);
844
845 /* assume CPU clk at least 1 MHz */
846 int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
847
848 retval = target_run_algorithm(target,
849 0, NULL,
850 ARRAY_SIZE(reg_params), reg_params,
851 erase_check_algorithm->address,
852 erase_check_algorithm->address + (code_size - 2),
853 timeout,
854 &armv7m_info);
855
856 timed_out = retval == ERROR_TARGET_TIMEOUT;
857 if (retval != ERROR_OK && !timed_out)
858 goto cleanup4;
859
860 retval = target_read_buffer(target, erase_check_params->address,
861 param_size, (uint8_t *)params);
862 if (retval != ERROR_OK)
863 goto cleanup4;
864
865 for (i = 0; i < blocks_to_check; i++) {
866 uint32_t result = target_buffer_get_u32(target,
867 (uint8_t *)&(params[i].result));
868 if (result != 0 && result != 1)
869 break;
870
871 blocks[i].result = result;
872 }
873 if (i && timed_out)
874 LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
875
876 retval = i; /* return number of blocks really checked */
877
878 cleanup4:
879 destroy_reg_param(&reg_params[0]);
880 destroy_reg_param(&reg_params[1]);
881
882 cleanup3:
883 target_free_working_area(target, erase_check_params);
884 cleanup2:
885 free(params);
886 cleanup1:
887 target_free_working_area(target, erase_check_algorithm);
888
889 return retval;
890 }
891
892 int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
893 {
894 struct armv7m_common *armv7m = target_to_armv7m(target);
895 struct reg *r = armv7m->arm.pc;
896 bool result = false;
897
898
899 /* if we halted last time due to a bkpt instruction
900 * then we have to manually step over it, otherwise
901 * the core will break again */
902
903 if (target->debug_reason == DBG_REASON_BREAKPOINT) {
904 uint16_t op;
905 uint32_t pc = buf_get_u32(r->value, 0, 32);
906
907 pc &= ~1;
908 if (target_read_u16(target, pc, &op) == ERROR_OK) {
909 if ((op & 0xFF00) == 0xBE00) {
910 pc = buf_get_u32(r->value, 0, 32) + 2;
911 buf_set_u32(r->value, 0, 32, pc);
912 r->dirty = true;
913 r->valid = true;
914 result = true;
915 LOG_DEBUG("Skipping over BKPT instruction");
916 }
917 }
918 }
919
920 if (inst_found)
921 *inst_found = result;
922
923 return ERROR_OK;
924 }
925
926 const struct command_registration armv7m_command_handlers[] = {
927 {
928 .chain = arm_command_handlers,
929 },
930 COMMAND_REGISTRATION_DONE
931 };
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