src/target/embeddedice.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                      *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "embeddedice.h"
  28
  29 #include "armv4_5.h"
  30 #include "arm7_9_common.h"
  31
  32 #include "log.h"
  33 #include "arm_jtag.h"
  34 #include "types.h"
  35 #include "binarybuffer.h"
  36 #include "target.h"
  37 #include "register.h"
  38 #include "jtag.h"
  39
  40 #include <stdlib.h>
  41
  42 bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
  43 {
  44         {"R", 1},
  45         {"W", 1},
  46         {"reserved", 26},
  47         {"version", 4}
  48 };
  49
  50 int embeddedice_reg_arch_info[] =
  51 {
  52         0x0, 0x1, 0x4, 0x5,
  53         0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
  54         0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
  55         0x2
  56 };
  57
  58 char* embeddedice_reg_list[] =
  59 {
  60         "debug_ctrl",
  61         "debug_status",
  62
  63         "comms_ctrl",
  64         "comms_data",
  65
  66         "watch 0 addr value",
  67         "watch 0 addr mask",
  68         "watch 0 data value",
  69         "watch 0 data mask",
  70         "watch 0 control value",
  71         "watch 0 control mask",
  72
  73         "watch 1 addr value",
  74         "watch 1 addr mask",
  75         "watch 1 data value",
  76         "watch 1 data mask",
  77         "watch 1 control value",
  78         "watch 1 control mask",
  79
  80         "vector catch"
  81 };
  82
  83 int embeddedice_reg_arch_type = -1;
  84
  85 int embeddedice_get_reg(reg_t *reg);
  86 int embeddedice_set_reg(reg_t *reg, u32 value);
  87 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
  88
  89 int embeddedice_write_reg(reg_t *reg, u32 value);
  90 int embeddedice_read_reg(reg_t *reg);
  91
  92 reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
  93 {
  94         int retval;
  95         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
  96         reg_t *reg_list = NULL;
  97         embeddedice_reg_t *arch_info = NULL;
  98         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  99         int num_regs;
 100         int i;
 101         int eice_version = 0;
 102
 103         /* register a register arch-type for EmbeddedICE registers only once */
 104         if (embeddedice_reg_arch_type == -1)
 105                 embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
 106
 107         if (arm7_9->has_vector_catch)
 108                 num_regs = 17;
 109         else
 110                 num_regs = 16;
 111
 112         /* the actual registers are kept in two arrays */
 113         reg_list = calloc(num_regs, sizeof(reg_t));
 114         arch_info = calloc(num_regs, sizeof(embeddedice_reg_t));
 115
 116         /* fill in values for the reg cache */
 117         reg_cache->name = "EmbeddedICE registers";
 118         reg_cache->next = NULL;
 119         reg_cache->reg_list = reg_list;
 120         reg_cache->num_regs = num_regs;
 121
 122         /* set up registers */
 123         for (i = 0; i < num_regs; i++)
 124         {
 125                 reg_list[i].name = embeddedice_reg_list[i];
 126                 reg_list[i].size = 32;
 127                 reg_list[i].dirty = 0;
 128                 reg_list[i].valid = 0;
 129                 reg_list[i].bitfield_desc = NULL;
 130                 reg_list[i].num_bitfields = 0;
 131                 reg_list[i].value = calloc(1, 4);
 132                 reg_list[i].arch_info = &arch_info[i];
 133                 reg_list[i].arch_type = embeddedice_reg_arch_type;
 134                 arch_info[i].addr = embeddedice_reg_arch_info[i];
 135                 arch_info[i].jtag_info = jtag_info;
 136         }
 137
 138         /* identify EmbeddedICE version by reading DCC control register */
 139         embeddedice_read_reg(&reg_list[EICE_COMMS_CTRL]);
 140         if ((retval=jtag_execute_queue())!=ERROR_OK)
 141         {
 142                 for (i = 0; i < num_regs; i++)
 143                 {
 144                         free(reg_list[i].value);
 145                 }
 146                 free(reg_list);
 147                 free(arch_info);
 148                 return NULL;
 149         }
 150
 151         eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
 152
 153         switch (eice_version)
 154         {
 155                 case 1:
 156                         reg_list[EICE_DBG_CTRL].size = 3;
 157                         reg_list[EICE_DBG_STAT].size = 5;
 158                         break;
 159                 case 2:
 160                         reg_list[EICE_DBG_CTRL].size = 4;
 161                         reg_list[EICE_DBG_STAT].size = 5;
 162                         arm7_9->has_single_step = 1;
 163                         break;
 164                 case 3:
 165                         LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
 166                         reg_list[EICE_DBG_CTRL].size = 6;
 167                         reg_list[EICE_DBG_STAT].size = 5;
 168                         arm7_9->has_single_step = 1;
 169                         arm7_9->has_monitor_mode = 1;
 170                         break;
 171                 case 4:
 172                         reg_list[EICE_DBG_CTRL].size = 6;
 173                         reg_list[EICE_DBG_STAT].size = 5;
 174                         arm7_9->has_monitor_mode = 1;
 175                         break;
 176                 case 5:
 177                         reg_list[EICE_DBG_CTRL].size = 6;
 178                         reg_list[EICE_DBG_STAT].size = 5;
 179                         arm7_9->has_single_step = 1;
 180                         arm7_9->has_monitor_mode = 1;
 181                         break;
 182                 case 6:
 183                         reg_list[EICE_DBG_CTRL].size = 6;
 184                         reg_list[EICE_DBG_STAT].size = 10;
 185                         arm7_9->has_monitor_mode = 1;
 186                         break;
 187                 case 7:
 188                         LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
 189                         reg_list[EICE_DBG_CTRL].size = 6;
 190                         reg_list[EICE_DBG_STAT].size = 5;
 191                         arm7_9->has_monitor_mode = 1;
 192                         break;
 193                 default:
 194                         LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 195         }
 196
 197         return reg_cache;
 198 }
 199
 200 int embeddedice_setup(target_t *target)
 201 {
 202         int retval;
 203         armv4_5_common_t *armv4_5 = target->arch_info;
 204         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 205
 206         /* explicitly disable monitor mode */
 207         if (arm7_9->has_monitor_mode)
 208         {
 209                 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 210
 211                 embeddedice_read_reg(dbg_ctrl);
 212                 if ((retval=jtag_execute_queue())!=ERROR_OK)
 213                         return retval;
 214                 buf_set_u32(dbg_ctrl->value, 4, 1, 0);
 215                 embeddedice_set_reg_w_exec(dbg_ctrl, dbg_ctrl->value);
 216         }
 217         return jtag_execute_queue();
 218 }
 219
 220 int embeddedice_get_reg(reg_t *reg)
 221 {
 222         if (embeddedice_read_reg(reg) != ERROR_OK)
 223         {
 224                 LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
 225                 exit(-1);
 226         }
 227
 228         if (jtag_execute_queue() != ERROR_OK)
 229         {
 230                 LOG_ERROR("register read failed");
 231         }
 232
 233         return ERROR_OK;
 234 }
 235
 236 int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
 237 {
 238         embeddedice_reg_t *ice_reg = reg->arch_info;
 239         u8 reg_addr = ice_reg->addr & 0x1f;
 240         scan_field_t fields[3];
 241         u8 field1_out[1];
 242         u8 field2_out[1];
 243
 244         jtag_add_end_state(TAP_RTI);
 245         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 246
 247         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 248
 249         fields[0].device = ice_reg->jtag_info->chain_pos;
 250         fields[0].num_bits = 32;
 251         fields[0].out_value = reg->value;
 252         fields[0].out_mask = NULL;
 253         fields[0].in_value = NULL;
 254         fields[0].in_check_value = NULL;
 255         fields[0].in_check_mask = NULL;
 256         fields[0].in_handler = NULL;
 257         fields[0].in_handler_priv = NULL;
 258
 259         fields[1].device = ice_reg->jtag_info->chain_pos;
 260         fields[1].num_bits = 5;
 261         fields[1].out_value = field1_out;
 262         buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
 263         fields[1].out_mask = NULL;
 264         fields[1].in_value = NULL;
 265         fields[1].in_check_value = NULL;
 266         fields[1].in_check_mask = NULL;
 267         fields[1].in_handler = NULL;
 268         fields[1].in_handler_priv = NULL;
 269
 270         fields[2].device = ice_reg->jtag_info->chain_pos;
 271         fields[2].num_bits = 1;
 272         fields[2].out_value = field2_out;
 273         buf_set_u32(fields[2].out_value, 0, 1, 0);
 274         fields[2].out_mask = NULL;
 275         fields[2].in_value = NULL;
 276         fields[2].in_check_value = NULL;
 277         fields[2].in_check_mask = NULL;
 278         fields[2].in_handler = NULL;
 279         fields[2].in_handler_priv = NULL;
 280
 281         jtag_add_dr_scan(3, fields, -1);
 282
 283         fields[0].in_value = reg->value;
 284         jtag_set_check_value(fields+0, check_value, check_mask, NULL);
 285
 286         /* when reading the DCC data register, leaving the address field set to
 287          * EICE_COMMS_DATA would read the register twice
 288          * reading the control register is safe
 289          */
 290         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 291
 292         jtag_add_dr_scan(3, fields, -1);
 293
 294         return ERROR_OK;
 295 }
 296
 297 /* receive <size> words of 32 bit from the DCC
 298  * we pretend the target is always going to be fast enough
 299  * (relative to the JTAG clock), so we don't need to handshake
 300  */
 301 int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
 302 {
 303         scan_field_t fields[3];
 304         u8 field1_out[1];
 305         u8 field2_out[1];
 306
 307         jtag_add_end_state(TAP_RTI);
 308         arm_jtag_scann(jtag_info, 0x2);
 309         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 310
 311         fields[0].device = jtag_info->chain_pos;
 312         fields[0].num_bits = 32;
 313         fields[0].out_value = NULL;
 314         fields[0].out_mask = NULL;
 315         fields[0].in_value = NULL;
 316         fields[0].in_check_value = NULL;
 317         fields[0].in_check_mask = NULL;
 318         fields[0].in_handler = NULL;
 319         fields[0].in_handler_priv = NULL;
 320
 321         fields[1].device = jtag_info->chain_pos;
 322         fields[1].num_bits = 5;
 323         fields[1].out_value = field1_out;
 324         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 325         fields[1].out_mask = NULL;
 326         fields[1].in_value = NULL;
 327         fields[1].in_check_value = NULL;
 328         fields[1].in_check_mask = NULL;
 329         fields[1].in_handler = NULL;
 330         fields[1].in_handler_priv = NULL;
 331
 332         fields[2].device = jtag_info->chain_pos;
 333         fields[2].num_bits = 1;
 334         fields[2].out_value = field2_out;
 335         buf_set_u32(fields[2].out_value, 0, 1, 0);
 336         fields[2].out_mask = NULL;
 337         fields[2].in_value = NULL;
 338         fields[2].in_check_value = NULL;
 339         fields[2].in_check_mask = NULL;
 340         fields[2].in_handler = NULL;
 341         fields[2].in_handler_priv = NULL;
 342
 343         jtag_add_dr_scan(3, fields, -1);
 344
 345         while (size > 0)
 346         {
 347                 /* when reading the last item, set the register address to the DCC control reg,
 348                  * to avoid reading additional data from the DCC data reg
 349                  */
 350                 if (size == 1)
 351                         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 352
 353                 fields[0].in_handler = arm_jtag_buf_to_u32;
 354                 fields[0].in_handler_priv = data;
 355                 jtag_add_dr_scan(3, fields, -1);
 356
 357                 data++;
 358                 size--;
 359         }
 360
 361         return jtag_execute_queue();
 362 }
 363
 364 int embeddedice_read_reg(reg_t *reg)
 365 {
 366         return embeddedice_read_reg_w_check(reg, NULL, NULL);
 367 }
 368
 369 int embeddedice_set_reg(reg_t *reg, u32 value)
 370 {
 371         if (embeddedice_write_reg(reg, value) != ERROR_OK)
 372         {
 373                 LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
 374                 exit(-1);
 375         }
 376
 377         buf_set_u32(reg->value, 0, reg->size, value);
 378         reg->valid = 1;
 379         reg->dirty = 0;
 380
 381         return ERROR_OK;
 382 }
 383
 384 int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
 385 {
 386         embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
 387
 388         if (jtag_execute_queue() != ERROR_OK)
 389         {
 390                 LOG_ERROR("register write failed");
 391                 exit(-1);
 392         }
 393         return ERROR_OK;
 394 }
 395
 396 int embeddedice_write_reg(reg_t *reg, u32 value)
 397 {
 398         embeddedice_reg_t *ice_reg = reg->arch_info;
 399
 400         LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
 401
 402         jtag_add_end_state(TAP_RTI);
 403         arm_jtag_scann(ice_reg->jtag_info, 0x2);
 404
 405         arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
 406
 407         u8 reg_addr = ice_reg->addr & 0x1f;
 408         embeddedice_write_reg_inner(ice_reg->jtag_info->chain_pos, reg_addr, value);
 409
 410         return ERROR_OK;
 411 }
 412
 413 int embeddedice_store_reg(reg_t *reg)
 414 {
 415         return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
 416 }
 417
 418 /* send <size> words of 32 bit to the DCC
 419  * we pretend the target is always going to be fast enough
 420  * (relative to the JTAG clock), so we don't need to handshake
 421  */
 422 int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
 423 {
 424         scan_field_t fields[3];
 425         u8 field0_out[4];
 426         u8 field1_out[1];
 427         u8 field2_out[1];
 428
 429         jtag_add_end_state(TAP_RTI);
 430         arm_jtag_scann(jtag_info, 0x2);
 431         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 432
 433         fields[0].device = jtag_info->chain_pos;
 434         fields[0].num_bits = 32;
 435         fields[0].out_value = field0_out;
 436         fields[0].out_mask = NULL;
 437         fields[0].in_value = NULL;
 438         fields[0].in_check_value = NULL;
 439         fields[0].in_check_mask = NULL;
 440         fields[0].in_handler = NULL;
 441         fields[0].in_handler_priv = NULL;
 442
 443         fields[1].device = jtag_info->chain_pos;
 444         fields[1].num_bits = 5;
 445         fields[1].out_value = field1_out;
 446         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
 447         fields[1].out_mask = NULL;
 448         fields[1].in_value = NULL;
 449         fields[1].in_check_value = NULL;
 450         fields[1].in_check_mask = NULL;
 451         fields[1].in_handler = NULL;
 452         fields[1].in_handler_priv = NULL;
 453
 454         fields[2].device = jtag_info->chain_pos;
 455         fields[2].num_bits = 1;
 456         fields[2].out_value = field2_out;
 457         buf_set_u32(fields[2].out_value, 0, 1, 1);
 458         fields[2].out_mask = NULL;
 459         fields[2].in_value = NULL;
 460         fields[2].in_check_value = NULL;
 461         fields[2].in_check_mask = NULL;
 462         fields[2].in_handler = NULL;
 463         fields[2].in_handler_priv = NULL;
 464
 465         while (size > 0)
 466         {
 467                 buf_set_u32(fields[0].out_value, 0, 32, *data);
 468                 jtag_add_dr_scan(3, fields, -1);
 469
 470                 data++;
 471                 size--;
 472         }
 473
 474         /* call to jtag_execute_queue() intentionally omitted */
 475         return ERROR_OK;
 476 }
 477
 478 /* wait for DCC control register R/W handshake bit to become active
 479  */
 480 int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
 481 {
 482         scan_field_t fields[3];
 483         u8 field0_in[4];
 484         u8 field1_out[1];
 485         u8 field2_out[1];
 486         int retval;
 487         int hsact;
 488         struct timeval lap;
 489         struct timeval now;
 490
 491         if (hsbit == EICE_COMM_CTRL_WBIT)
 492                 hsact = 1;
 493         else if (hsbit == EICE_COMM_CTRL_RBIT)
 494                 hsact = 0;
 495         else
 496                 return ERROR_INVALID_ARGUMENTS;
 497
 498         jtag_add_end_state(TAP_RTI);
 499         arm_jtag_scann(jtag_info, 0x2);
 500         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 501
 502         fields[0].device = jtag_info->chain_pos;
 503         fields[0].num_bits = 32;
 504         fields[0].out_value = NULL;
 505         fields[0].out_mask = NULL;
 506         fields[0].in_value = field0_in;
 507         fields[0].in_check_value = NULL;
 508         fields[0].in_check_mask = NULL;
 509         fields[0].in_handler = NULL;
 510         fields[0].in_handler_priv = NULL;
 511
 512         fields[1].device = jtag_info->chain_pos;
 513         fields[1].num_bits = 5;
 514         fields[1].out_value = field1_out;
 515         buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
 516         fields[1].out_mask = NULL;
 517         fields[1].in_value = NULL;
 518         fields[1].in_check_value = NULL;
 519         fields[1].in_check_mask = NULL;
 520         fields[1].in_handler = NULL;
 521         fields[1].in_handler_priv = NULL;
 522
 523         fields[2].device = jtag_info->chain_pos;
 524         fields[2].num_bits = 1;
 525         fields[2].out_value = field2_out;
 526         buf_set_u32(fields[2].out_value, 0, 1, 0);
 527         fields[2].out_mask = NULL;
 528         fields[2].in_value = NULL;
 529         fields[2].in_check_value = NULL;
 530         fields[2].in_check_mask = NULL;
 531         fields[2].in_handler = NULL;
 532         fields[2].in_handler_priv = NULL;
 533
 534         jtag_add_dr_scan(3, fields, -1);
 535         gettimeofday(&lap, NULL);
 536         do
 537         {
 538                 jtag_add_dr_scan(3, fields, -1);
 539                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 540                         return retval;
 541
 542                 if (buf_get_u32(field0_in, hsbit, 1) == hsact)
 543                         return ERROR_OK;
 544
 545                 gettimeofday(&now, NULL);
 546         }
 547         while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
 548
 549         return ERROR_TARGET_TIMEOUT;
 550 }
 551
 552 /* this is the inner loop of the open loop DCC write of data to target */
 553 void MINIDRIVER(embeddedice_write_dcc)(int chain_pos, int reg_addr, u8 *buffer, int little, int count)
 554 {
 555         int i;
 556         for (i = 0; i < count; i++)
 557         {
 558                 embeddedice_write_reg_inner(chain_pos, reg_addr, fast_target_buffer_get_u32(buffer, little));
 559                 buffer += 4;
 560         }
 561 }