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configure: use consistent help text
[openocd.git] / src / flash / nand / lpc3180.c
bloba44f3c21e23e2282a71ee6dd6aaaf031c93112c3
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 *
5 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
6 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "imp.h"
29 #include "lpc3180.h"
30 #include <target/target.h>
31
32 static int lpc3180_reset(struct nand_device *nand);
33 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
34 static int lpc3180_tc_ready(struct nand_device *nand, int timeout);
35
36 #define ECC_OFFS 0x120
37 #define SPARE_OFFS 0x140
38 #define DATA_OFFS 0x200
39
40 /* nand device lpc3180 <target#> <oscillator_frequency>
41 */
42 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command)
43 {
44 if (CMD_ARGC < 3)
45 return ERROR_COMMAND_SYNTAX_ERROR;
46
47 uint32_t osc_freq;
48 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
49
50 struct lpc3180_nand_controller *lpc3180_info;
51 lpc3180_info = malloc(sizeof(struct lpc3180_nand_controller));
52 nand->controller_priv = lpc3180_info;
53
54 lpc3180_info->osc_freq = osc_freq;
55
56 if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
57 LOG_WARNING(
58 "LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i",
59 lpc3180_info->osc_freq);
60 lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
61 lpc3180_info->sw_write_protection = 0;
62 lpc3180_info->sw_wp_lower_bound = 0x0;
63 lpc3180_info->sw_wp_upper_bound = 0x0;
64
65 return ERROR_OK;
66 }
67
68 static int lpc3180_pll(int fclkin, uint32_t pll_ctrl)
69 {
70 int bypass = (pll_ctrl & 0x8000) >> 15;
71 int direct = (pll_ctrl & 0x4000) >> 14;
72 int feedback = (pll_ctrl & 0x2000) >> 13;
73 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
74 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
75 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
76 int lock = (pll_ctrl & 0x1);
77
78 if (!lock)
79 LOG_WARNING("PLL is not locked");
80
81 if (!bypass && direct) /* direct mode */
82 return (m * fclkin) / n;
83
84 if (bypass && !direct) /* bypass mode */
85 return fclkin / (2 * p);
86
87 if (bypass & direct) /* direct bypass mode */
88 return fclkin;
89
90 if (feedback) /* integer mode */
91 return m * (fclkin / n);
92 else /* non-integer mode */
93 return (m / (2 * p)) * (fclkin / n);
94 }
95
96 static float lpc3180_cycle_time(struct nand_device *nand)
97 {
98 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
99 struct target *target = nand->target;
100 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
101 int sysclk;
102 int hclk;
103 int hclk_pll;
104 float cycle;
105
106 /* calculate timings */
107
108 /* determine current SYSCLK (13'MHz or main oscillator) */
109 target_read_u32(target, 0x40004050, &sysclk_ctrl);
110
111 if ((sysclk_ctrl & 1) == 0)
112 sysclk = lpc3180_info->osc_freq;
113 else
114 sysclk = 13000;
115
116 /* determine selected HCLK source */
117 target_read_u32(target, 0x40004044, &pwr_ctrl);
118
119 if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
120 hclk = sysclk;
121 else {
122 target_read_u32(target, 0x40004058, &hclkpll_ctrl);
123 hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
124
125 target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
126
127 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
128 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
129 else /* HCLK uses HCLK_PLL */
130 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
131 }
132
133 LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
134
135 cycle = (1.0 / hclk) * 1000000.0;
136
137 return cycle;
138 }
139
140 static int lpc3180_init(struct nand_device *nand)
141 {
142 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
143 struct target *target = nand->target;
144 int bus_width = nand->bus_width ? : 8;
145 int address_cycles = nand->address_cycles ? : 3;
146 int page_size = nand->page_size ? : 512;
147
148 if (target->state != TARGET_HALTED) {
149 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
150 return ERROR_NAND_OPERATION_FAILED;
151 }
152
153 /* sanitize arguments */
154 if ((bus_width != 8) && (bus_width != 16)) {
155 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
156 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
157 }
158
159 /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
160 * would support 16 bit, too, so we just warn about this for now
161 */
162 if (bus_width == 16)
163 LOG_WARNING("LPC3180 only supports 8 bit bus width");
164
165 /* inform calling code about selected bus width */
166 nand->bus_width = bus_width;
167
168 if ((address_cycles != 3) && (address_cycles != 4)) {
169 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
170 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
171 }
172
173 if ((page_size != 512) && (page_size != 2048)) {
174 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
175 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
176 }
177
178 /* select MLC controller if none is currently selected */
179 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
180 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
181 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
182 }
183
184 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
185 uint32_t mlc_icr_value = 0x0;
186 float cycle;
187 int twp, twh, trp, treh, trhz, trbwb, tcea;
188
189 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
190 target_write_u32(target, 0x400040c8, 0x22);
191
192 /* MLC_CEH = 0x0 (Force nCE assert) */
193 target_write_u32(target, 0x200b804c, 0x0);
194
195 /* MLC_LOCK = 0xa25e (unlock protected registers) */
196 target_write_u32(target, 0x200b8044, 0xa25e);
197
198 /* MLC_ICR = configuration */
199 if (lpc3180_info->sw_write_protection)
200 mlc_icr_value |= 0x8;
201 if (page_size == 2048)
202 mlc_icr_value |= 0x4;
203 if (address_cycles == 4)
204 mlc_icr_value |= 0x2;
205 if (bus_width == 16)
206 mlc_icr_value |= 0x1;
207 target_write_u32(target, 0x200b8030, mlc_icr_value);
208
209 /* calculate NAND controller timings */
210 cycle = lpc3180_cycle_time(nand);
211
212 twp = ((40 / cycle) + 1);
213 twh = ((20 / cycle) + 1);
214 trp = ((30 / cycle) + 1);
215 treh = ((15 / cycle) + 1);
216 trhz = ((30 / cycle) + 1);
217 trbwb = ((100 / cycle) + 1);
218 tcea = ((45 / cycle) + 1);
219
220 /* MLC_LOCK = 0xa25e (unlock protected registers) */
221 target_write_u32(target, 0x200b8044, 0xa25e);
222
223 /* MLC_TIME_REG */
224 target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
225 ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
226 ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
227
228 lpc3180_reset(nand);
229 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
230 float cycle;
231 int r_setup, r_hold, r_width, r_rdy;
232 int w_setup, w_hold, w_width, w_rdy;
233
234 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
235 target_write_u32(target, 0x400040c8, 0x05);
236
237 /* after reset set other registers of SLC so reset calling is here at the begining*/
238 lpc3180_reset(nand);
239
240 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
241 *DMA read from SLC, WIDTH = bus_width) */
242 target_write_u32(target, 0x20020014, 0x3e | (bus_width == 16) ? 1 : 0);
243
244 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
245 target_write_u32(target, 0x20020020, 0x03);
246
247 /* DMA configuration
248 * DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
249 target_write_u32(target, 0x400040e8, 0x01);
250 /* DMACConfig = DMA enabled*/
251 target_write_u32(target, 0x31000030, 0x01);
252
253
254 /* calculate NAND controller timings */
255 cycle = lpc3180_cycle_time(nand);
256
257 r_setup = w_setup = 0;
258 r_hold = w_hold = 10 / cycle;
259 r_width = 30 / cycle;
260 w_width = 40 / cycle;
261 r_rdy = w_rdy = 100 / cycle;
262
263 /* SLC_TAC: SLC timing arcs register */
264 target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
265 ((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
266 ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
267
268 }
269
270 return ERROR_OK;
271 }
272
273 static int lpc3180_reset(struct nand_device *nand)
274 {
275 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
276 struct target *target = nand->target;
277
278 if (target->state != TARGET_HALTED) {
279 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
280 return ERROR_NAND_OPERATION_FAILED;
281 }
282
283 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
284 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
285 return ERROR_NAND_OPERATION_FAILED;
286 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
287 /* MLC_CMD = 0xff (reset controller and NAND device) */
288 target_write_u32(target, 0x200b8000, 0xff);
289
290 if (!lpc3180_controller_ready(nand, 100)) {
291 LOG_ERROR("LPC3180 NAND controller timed out after reset");
292 return ERROR_NAND_OPERATION_TIMEOUT;
293 }
294 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
295 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
296 target_write_u32(target, 0x20020010, 0x6);
297
298 if (!lpc3180_controller_ready(nand, 100)) {
299 LOG_ERROR("LPC3180 NAND controller timed out after reset");
300 return ERROR_NAND_OPERATION_TIMEOUT;
301 }
302 }
303
304 return ERROR_OK;
305 }
306
307 static int lpc3180_command(struct nand_device *nand, uint8_t command)
308 {
309 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
310 struct target *target = nand->target;
311
312 if (target->state != TARGET_HALTED) {
313 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
314 return ERROR_NAND_OPERATION_FAILED;
315 }
316
317 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
318 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
319 return ERROR_NAND_OPERATION_FAILED;
320 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
321 /* MLC_CMD = command */
322 target_write_u32(target, 0x200b8000, command);
323 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
324 /* SLC_CMD = command */
325 target_write_u32(target, 0x20020008, command);
326 }
327
328 return ERROR_OK;
329 }
330
331 static int lpc3180_address(struct nand_device *nand, uint8_t address)
332 {
333 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
334 struct target *target = nand->target;
335
336 if (target->state != TARGET_HALTED) {
337 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
338 return ERROR_NAND_OPERATION_FAILED;
339 }
340
341 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
342 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
343 return ERROR_NAND_OPERATION_FAILED;
344 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
345 /* MLC_ADDR = address */
346 target_write_u32(target, 0x200b8004, address);
347 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
348 /* SLC_ADDR = address */
349 target_write_u32(target, 0x20020004, address);
350 }
351
352 return ERROR_OK;
353 }
354
355 static int lpc3180_write_data(struct nand_device *nand, uint16_t data)
356 {
357 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
358 struct target *target = nand->target;
359
360 if (target->state != TARGET_HALTED) {
361 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
362 return ERROR_NAND_OPERATION_FAILED;
363 }
364
365 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
366 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
367 return ERROR_NAND_OPERATION_FAILED;
368 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
369 /* MLC_DATA = data */
370 target_write_u32(target, 0x200b0000, data);
371 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
372 /* SLC_DATA = data */
373 target_write_u32(target, 0x20020000, data);
374 }
375
376 return ERROR_OK;
377 }
378
379 static int lpc3180_read_data(struct nand_device *nand, void *data)
380 {
381 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
382 struct target *target = nand->target;
383
384 if (target->state != TARGET_HALTED) {
385 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
386 return ERROR_NAND_OPERATION_FAILED;
387 }
388
389 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
390 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
391 return ERROR_NAND_OPERATION_FAILED;
392 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
393 /* data = MLC_DATA, use sized access */
394 if (nand->bus_width == 8) {
395 uint8_t *data8 = data;
396 target_read_u8(target, 0x200b0000, data8);
397 } else if (nand->bus_width == 16) {
398 uint16_t *data16 = data;
399 target_read_u16(target, 0x200b0000, data16);
400 } else {
401 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
402 return ERROR_NAND_OPERATION_FAILED;
403 }
404 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
405 uint32_t data32;
406
407 /* data = SLC_DATA, must use 32-bit access */
408 target_read_u32(target, 0x20020000, &data32);
409
410 if (nand->bus_width == 8) {
411 uint8_t *data8 = data;
412 *data8 = data32 & 0xff;
413 } else if (nand->bus_width == 16) {
414 uint16_t *data16 = data;
415 *data16 = data32 & 0xffff;
416 } else {
417 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
418 return ERROR_NAND_OPERATION_FAILED;
419 }
420 }
421
422 return ERROR_OK;
423 }
424
425 static int lpc3180_write_page(struct nand_device *nand,
426 uint32_t page,
427 uint8_t *data,
428 uint32_t data_size,
429 uint8_t *oob,
430 uint32_t oob_size)
431 {
432 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
433 struct target *target = nand->target;
434 int retval;
435 uint8_t status;
436 uint8_t *page_buffer;
437
438 if (target->state != TARGET_HALTED) {
439 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
440 return ERROR_NAND_OPERATION_FAILED;
441 }
442
443 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
444 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
445 return ERROR_NAND_OPERATION_FAILED;
446 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
447 uint8_t *oob_buffer;
448 int quarter, num_quarters;
449
450 if (!data && oob) {
451 LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
452 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
453 }
454
455 if (oob && (oob_size > 24)) {
456 LOG_ERROR("LPC3180 MLC controller can't write more "
457 "than 6 bytes for each quarter's OOB data");
458 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
459 }
460
461 if (data_size > (uint32_t)nand->page_size) {
462 LOG_ERROR("data size exceeds page size");
463 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
464 }
465
466 /* MLC_CMD = sequential input */
467 target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
468
469 page_buffer = malloc(512);
470 oob_buffer = malloc(6);
471
472 if (nand->page_size == 512) {
473 /* MLC_ADDR = 0x0 (one column cycle) */
474 target_write_u32(target, 0x200b8004, 0x0);
475
476 /* MLC_ADDR = row */
477 target_write_u32(target, 0x200b8004, page & 0xff);
478 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
479
480 if (nand->address_cycles == 4)
481 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
482 } else {
483 /* MLC_ADDR = 0x0 (two column cycles) */
484 target_write_u32(target, 0x200b8004, 0x0);
485 target_write_u32(target, 0x200b8004, 0x0);
486
487 /* MLC_ADDR = row */
488 target_write_u32(target, 0x200b8004, page & 0xff);
489 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
490 }
491
492 /* when using the MLC controller, we have to treat a large page device
493 * as being made out of four quarters, each the size of a small page device
494 */
495 num_quarters = (nand->page_size == 2048) ? 4 : 1;
496
497 for (quarter = 0; quarter < num_quarters; quarter++) {
498 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
499 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
500
501 memset(page_buffer, 0xff, 512);
502 if (data) {
503 memcpy(page_buffer, data, thisrun_data_size);
504 data_size -= thisrun_data_size;
505 data += thisrun_data_size;
506 }
507
508 memset(oob_buffer, 0xff, 6);
509 if (oob) {
510 memcpy(oob_buffer, oob, thisrun_oob_size);
511 oob_size -= thisrun_oob_size;
512 oob += thisrun_oob_size;
513 }
514
515 /* write MLC_ECC_ENC_REG to start encode cycle */
516 target_write_u32(target, 0x200b8008, 0x0);
517
518 target_write_memory(target, 0x200a8000,
519 4, 128, page_buffer);
520 target_write_memory(target, 0x200a8000,
521 1, 6, oob_buffer);
522
523 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
524 target_write_u32(target, 0x200b8010, 0x0);
525
526 if (!lpc3180_controller_ready(nand, 1000)) {
527 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
528 free(page_buffer);
529 free(oob_buffer);
530 return ERROR_NAND_OPERATION_FAILED;
531 }
532 }
533
534 /* MLC_CMD = auto program command */
535 target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
536
537 retval = nand_read_status(nand, &status);
538 if (retval != ERROR_OK) {
539 LOG_ERROR("couldn't read status");
540 free(page_buffer);
541 free(oob_buffer);
542 return ERROR_NAND_OPERATION_FAILED;
543 }
544
545 if (status & NAND_STATUS_FAIL) {
546 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
547 free(page_buffer);
548 free(oob_buffer);
549 return ERROR_NAND_OPERATION_FAILED;
550 }
551
552 free(page_buffer);
553 free(oob_buffer);
554 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
555
556 /**********************************************************************
557 * Write both SLC NAND flash page main area and spare area.
558 * Small page -
559 * ------------------------------------------
560 * | 512 bytes main | 16 bytes spare |
561 * ------------------------------------------
562 * Large page -
563 * ------------------------------------------
564 * | 2048 bytes main | 64 bytes spare |
565 * ------------------------------------------
566 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
567 * data is written to the 3rd word of the spare area. The ECC
568 * generated for the 2nd 256-byte data is written to the 4th word
569 * of the spare area. The ECC generated for the 3rd 256-byte data is
570 * written to the 7th word of the spare area. The ECC generated
571 * for the 4th 256-byte data is written to the 8th word of the
572 * spare area and so on.
573 *
574 **********************************************************************/
575
576 int i = 0, target_mem_base;
577 uint8_t *ecc_flash_buffer;
578 struct working_area *pworking_area;
579
580 if (lpc3180_info->is_bulk) {
581
582 if (!data && oob) {
583 /*if oob only mode is active original method is used as SLC
584 *controller hangs during DMA interworking. Anyway the code supports
585 *the oob only mode below. */
586 return nand_write_page_raw(nand,
587 page,
588 data,
589 data_size,
590 oob,
591 oob_size);
592 }
593 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
594 if (ERROR_OK != retval)
595 return retval;
596
597 /* allocate a working area */
598 if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
599 LOG_ERROR("Reserve at least 0x%x physical target working area",
600 nand->page_size + 0x200);
601 return ERROR_FLASH_OPERATION_FAILED;
602 }
603 if (target->working_area_phys%4) {
604 LOG_ERROR(
605 "Reserve the physical target working area at word boundary");
606 return ERROR_FLASH_OPERATION_FAILED;
607 }
608 if (target_alloc_working_area(target, target->working_area_size,
609 &pworking_area) != ERROR_OK) {
610 LOG_ERROR("no working area specified, can't read LPC internal flash");
611 return ERROR_FLASH_OPERATION_FAILED;
612 }
613 target_mem_base = target->working_area_phys;
614
615 if (nand->page_size == 2048)
616 page_buffer = malloc(2048);
617 else
618 page_buffer = malloc(512);
619
620 ecc_flash_buffer = malloc(64);
621
622 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
623 *enabled, DMA write to SLC, WIDTH = bus_width) */
624 target_write_u32(target, 0x20020014, 0x3c);
625
626 if (data && !oob) {
627 /* set DMA LLI-s in target memory and in DMA*/
628 for (i = 0; i < nand->page_size/0x100; i++) {
629
630 int tmp;
631 /* -------LLI for 256 byte block---------
632 * DMACC0SrcAddr = SRAM */
633 target_write_u32(target,
634 target_mem_base+0+i*32,
635 target_mem_base+DATA_OFFS+i*256);
636 if (i == 0)
637 target_write_u32(target,
638 0x31000100,
639 target_mem_base+DATA_OFFS);
640 /* DMACCxDestAddr = SLC_DMA_DATA */
641 target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
642 if (i == 0)
643 target_write_u32(target, 0x31000104, 0x20020038);
644 /* DMACCxLLI = next element */
645 tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
646 target_write_u32(target, target_mem_base+8+i*32, tmp);
647 if (i == 0)
648 target_write_u32(target, 0x31000108, tmp);
649 /* DMACCxControl = TransferSize =64, Source burst size =16,
650 * Destination burst size = 16, Source transfer width = 32 bit,
651 * Destination transfer width = 32 bit, Source AHB master select = M0,
652 * Destination AHB master select = M0, Source increment = 1,
653 * Destination increment = 0, Terminal count interrupt enable bit = 0*/
654 target_write_u32(target,
655 target_mem_base+12+i*32,
656 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
657 0<<27 | 0<<31);
658 if (i == 0)
659 target_write_u32(target,
660 0x3100010c,
661 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
662 0<<27 | 0<<31);
663
664 /* -------LLI for 3 byte ECC---------
665 * DMACC0SrcAddr = SLC_ECC*/
666 target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
667 /* DMACCxDestAddr = SRAM */
668 target_write_u32(target,
669 target_mem_base+20+i*32,
670 target_mem_base+SPARE_OFFS+8+16*(i>>1)+(i%2)*4);
671 /* DMACCxLLI = next element */
672 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
673 target_write_u32(target, target_mem_base+24+i*32, tmp);
674 /* DMACCxControl = TransferSize =1, Source burst size =4,
675 * Destination burst size = 4, Source transfer width = 32 bit,
676 * Destination transfer width = 32 bit, Source AHB master select = M0,
677 * Destination AHB master select = M0, Source increment = 0,
678 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
679 target_write_u32(target,
680 target_mem_base+28+i*32,
681 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
682 31);
683 }
684 } else if (data && oob) {
685 /* -------LLI for 512 or 2048 bytes page---------
686 * DMACC0SrcAddr = SRAM */
687 target_write_u32(target, target_mem_base, target_mem_base+DATA_OFFS);
688 target_write_u32(target, 0x31000100, target_mem_base+DATA_OFFS);
689 /* DMACCxDestAddr = SLC_DMA_DATA */
690 target_write_u32(target, target_mem_base+4, 0x20020038);
691 target_write_u32(target, 0x31000104, 0x20020038);
692 /* DMACCxLLI = next element */
693 target_write_u32(target,
694 target_mem_base+8,
695 (target_mem_base+32)&0xfffffffc);
696 target_write_u32(target, 0x31000108,
697 (target_mem_base+32)&0xfffffffc);
698 /* DMACCxControl = TransferSize =512 or 128, Source burst size =16,
699 * Destination burst size = 16, Source transfer width = 32 bit,
700 * Destination transfer width = 32 bit, Source AHB master select = M0,
701 * Destination AHB master select = M0, Source increment = 1,
702 * Destination increment = 0, Terminal count interrupt enable bit = 0*/
703 target_write_u32(target,
704 target_mem_base+12,
705 (nand->page_size ==
706 2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
707 1<<26 | 0<<27 | 0<<31);
708 target_write_u32(target,
709 0x3100010c,
710 (nand->page_size ==
711 2048 ? 512 : 128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 |
712 1<<26 | 0<<27 | 0<<31);
713 i = 1;
714 } else if (!data && oob)
715 i = 0;
716
717 /* -------LLI for spare area---------
718 * DMACC0SrcAddr = SRAM*/
719 target_write_u32(target, target_mem_base+0+i*32, target_mem_base+SPARE_OFFS);
720 if (i == 0)
721 target_write_u32(target, 0x31000100, target_mem_base+SPARE_OFFS);
722 /* DMACCxDestAddr = SLC_DMA_DATA */
723 target_write_u32(target, target_mem_base+4+i*32, 0x20020038);
724 if (i == 0)
725 target_write_u32(target, 0x31000104, 0x20020038);
726 /* DMACCxLLI = next element = NULL */
727 target_write_u32(target, target_mem_base+8+i*32, 0);
728 if (i == 0)
729 target_write_u32(target, 0x31000108, 0);
730 /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
731 * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
732 * Destination transfer width = 32 bit, Source AHB master select = M0,
733 * Destination AHB master select = M0, Source increment = 1,
734 * Destination increment = 0, Terminal count interrupt enable bit = 0*/
735 target_write_u32(target,
736 target_mem_base+12+i*32,
737 (nand->page_size ==
738 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 |
739 0<<27 | 0<<31);
740 if (i == 0)
741 target_write_u32(target, 0x3100010c,
742 (nand->page_size == 2048 ?
743 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 |
744 0<<25 | 1<<26 | 0<<27 | 0<<31);
745
746 memset(ecc_flash_buffer, 0xff, 64);
747 if (oob)
748 memcpy(ecc_flash_buffer, oob, oob_size);
749 target_write_memory(target,
750 target_mem_base+SPARE_OFFS,
751 4,
752 16,
753 ecc_flash_buffer);
754
755 if (data) {
756 memset(page_buffer, 0xff, nand->page_size == 2048 ? 2048 : 512);
757 memcpy(page_buffer, data, data_size);
758 target_write_memory(target,
759 target_mem_base+DATA_OFFS,
760 4,
761 nand->page_size == 2048 ? 512 : 128,
762 page_buffer);
763 }
764
765 free(page_buffer);
766 free(ecc_flash_buffer);
767
768 /* Enable DMA after channel set up !
769 LLI only works when DMA is the flow controller!
770 */
771 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
772 *FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
773 target_write_u32(target,
774 0x31000110,
775 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
776
777 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
778 target_write_u32(target, 0x20020010, 0x3);
779
780 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
781 target_write_u32(target, 0x20020028, 2);
782
783 /* SLC_TC */
784 if (!data && oob)
785 target_write_u32(target, 0x20020030,
786 (nand->page_size == 2048 ? 0x10 : 0x04));
787 else
788 target_write_u32(target, 0x20020030,
789 (nand->page_size == 2048 ? 0x840 : 0x210));
790
791 nand_write_finish(nand);
792
793 if (!lpc3180_tc_ready(nand, 1000)) {
794 LOG_ERROR("timeout while waiting for completion of DMA");
795 return ERROR_NAND_OPERATION_FAILED;
796 }
797
798 target_free_working_area(target, pworking_area);
799
800 LOG_INFO("Page = 0x%" PRIx32 " was written.", page);
801
802 } else
803 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
804 }
805
806 return ERROR_OK;
807 }
808
809 static int lpc3180_read_page(struct nand_device *nand,
810 uint32_t page,
811 uint8_t *data,
812 uint32_t data_size,
813 uint8_t *oob,
814 uint32_t oob_size)
815 {
816 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
817 struct target *target = nand->target;
818 uint8_t *page_buffer;
819
820 if (target->state != TARGET_HALTED) {
821 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
822 return ERROR_NAND_OPERATION_FAILED;
823 }
824
825 if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER) {
826 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
827 return ERROR_NAND_OPERATION_FAILED;
828 } else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
829 uint8_t *oob_buffer;
830 uint32_t page_bytes_done = 0;
831 uint32_t oob_bytes_done = 0;
832 uint32_t mlc_isr;
833
834 #if 0
835 if (oob && (oob_size > 6)) {
836 LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
837 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
838 }
839 #endif
840
841 if (data_size > (uint32_t)nand->page_size) {
842 LOG_ERROR("data size exceeds page size");
843 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
844 }
845
846 if (nand->page_size == 2048) {
847 page_buffer = malloc(2048);
848 oob_buffer = malloc(64);
849 } else {
850 page_buffer = malloc(512);
851 oob_buffer = malloc(16);
852 }
853
854 if (!data && oob) {
855 /* MLC_CMD = Read OOB
856 * we can use the READOOB command on both small and large page devices,
857 * as the controller translates the 0x50 command to a 0x0 with appropriate
858 * positioning of the serial buffer read pointer
859 */
860 target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
861 } else {
862 /* MLC_CMD = Read0 */
863 target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
864 }
865
866 if (nand->page_size == 512) {
867 /* small page device
868 * MLC_ADDR = 0x0 (one column cycle) */
869 target_write_u32(target, 0x200b8004, 0x0);
870
871 /* MLC_ADDR = row */
872 target_write_u32(target, 0x200b8004, page & 0xff);
873 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
874
875 if (nand->address_cycles == 4)
876 target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
877 } else {
878 /* large page device
879 * MLC_ADDR = 0x0 (two column cycles) */
880 target_write_u32(target, 0x200b8004, 0x0);
881 target_write_u32(target, 0x200b8004, 0x0);
882
883 /* MLC_ADDR = row */
884 target_write_u32(target, 0x200b8004, page & 0xff);
885 target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
886
887 /* MLC_CMD = Read Start */
888 target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
889 }
890
891 while (page_bytes_done < (uint32_t)nand->page_size) {
892 /* MLC_ECC_AUTO_DEC_REG = dummy */
893 target_write_u32(target, 0x200b8014, 0xaa55aa55);
894
895 if (!lpc3180_controller_ready(nand, 1000)) {
896 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
897 free(page_buffer);
898 free(oob_buffer);
899 return ERROR_NAND_OPERATION_FAILED;
900 }
901
902 target_read_u32(target, 0x200b8048, &mlc_isr);
903
904 if (mlc_isr & 0x8) {
905 if (mlc_isr & 0x40) {
906 LOG_ERROR("uncorrectable error detected: 0x%2.2x",
907 (unsigned)mlc_isr);
908 free(page_buffer);
909 free(oob_buffer);
910 return ERROR_NAND_OPERATION_FAILED;
911 }
912
913 LOG_WARNING("%i symbol error detected and corrected",
914 ((int)(((mlc_isr & 0x30) >> 4) + 1)));
915 }
916
917 if (data)
918 target_read_memory(target,
919 0x200a8000,
920 4,
921 128,
922 page_buffer + page_bytes_done);
923
924 if (oob)
925 target_read_memory(target,
926 0x200a8000,
927 4,
928 4,
929 oob_buffer + oob_bytes_done);
930
931 page_bytes_done += 512;
932 oob_bytes_done += 16;
933 }
934
935 if (data)
936 memcpy(data, page_buffer, data_size);
937
938 if (oob)
939 memcpy(oob, oob_buffer, oob_size);
940
941 free(page_buffer);
942 free(oob_buffer);
943 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
944
945 /**********************************************************************
946 * Read both SLC NAND flash page main area and spare area.
947 * Small page -
948 * ------------------------------------------
949 * | 512 bytes main | 16 bytes spare |
950 * ------------------------------------------
951 * Large page -
952 * ------------------------------------------
953 * | 2048 bytes main | 64 bytes spare |
954 * ------------------------------------------
955 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
956 * data is compared with the 3rd word of the spare area. The ECC
957 * generated for the 2nd 256-byte data is compared with the 4th word
958 * of the spare area. The ECC generated for the 3rd 256-byte data is
959 * compared with the 7th word of the spare area. The ECC generated
960 * for the 4th 256-byte data is compared with the 8th word of the
961 * spare area and so on.
962 *
963 **********************************************************************/
964
965 int retval, i, target_mem_base;
966 uint8_t *ecc_hw_buffer;
967 uint8_t *ecc_flash_buffer;
968 struct working_area *pworking_area;
969
970 if (lpc3180_info->is_bulk) {
971
972 /* read always the data and also oob areas*/
973
974 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
975 if (ERROR_OK != retval)
976 return retval;
977
978 /* allocate a working area */
979 if (target->working_area_size < (uint32_t) nand->page_size + 0x200) {
980 LOG_ERROR("Reserve at least 0x%x physical target working area",
981 nand->page_size + 0x200);
982 return ERROR_FLASH_OPERATION_FAILED;
983 }
984 if (target->working_area_phys%4) {
985 LOG_ERROR(
986 "Reserve the physical target working area at word boundary");
987 return ERROR_FLASH_OPERATION_FAILED;
988 }
989 if (target_alloc_working_area(target, target->working_area_size,
990 &pworking_area) != ERROR_OK) {
991 LOG_ERROR("no working area specified, can't read LPC internal flash");
992 return ERROR_FLASH_OPERATION_FAILED;
993 }
994 target_mem_base = target->working_area_phys;
995
996 if (nand->page_size == 2048)
997 page_buffer = malloc(2048);
998 else
999 page_buffer = malloc(512);
1000
1001 ecc_hw_buffer = malloc(32);
1002 ecc_flash_buffer = malloc(64);
1003
1004 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst
1005 *enabled, DMA read from SLC, WIDTH = bus_width) */
1006 target_write_u32(target, 0x20020014, 0x3e);
1007
1008 /* set DMA LLI-s in target memory and in DMA*/
1009 for (i = 0; i < nand->page_size/0x100; i++) {
1010 int tmp;
1011 /* -------LLI for 256 byte block---------
1012 * DMACC0SrcAddr = SLC_DMA_DATA*/
1013 target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
1014 if (i == 0)
1015 target_write_u32(target, 0x31000100, 0x20020038);
1016 /* DMACCxDestAddr = SRAM */
1017 target_write_u32(target,
1018 target_mem_base+4+i*32,
1019 target_mem_base+DATA_OFFS+i*256);
1020 if (i == 0)
1021 target_write_u32(target,
1022 0x31000104,
1023 target_mem_base+DATA_OFFS);
1024 /* DMACCxLLI = next element */
1025 tmp = (target_mem_base+(1+i*2)*16)&0xfffffffc;
1026 target_write_u32(target, target_mem_base+8+i*32, tmp);
1027 if (i == 0)
1028 target_write_u32(target, 0x31000108, tmp);
1029 /* DMACCxControl = TransferSize =64, Source burst size =16,
1030 * Destination burst size = 16, Source transfer width = 32 bit,
1031 * Destination transfer width = 32 bit, Source AHB master select = M0,
1032 * Destination AHB master select = M0, Source increment = 0,
1033 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1034 target_write_u32(target,
1035 target_mem_base+12+i*32,
1036 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1037 31);
1038 if (i == 0)
1039 target_write_u32(target,
1040 0x3100010c,
1041 0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1042 31);
1043
1044 /* -------LLI for 3 byte ECC---------
1045 * DMACC0SrcAddr = SLC_ECC*/
1046 target_write_u32(target, target_mem_base+16+i*32, 0x20020034);
1047 /* DMACCxDestAddr = SRAM */
1048 target_write_u32(target,
1049 target_mem_base+20+i*32,
1050 target_mem_base+ECC_OFFS+i*4);
1051 /* DMACCxLLI = next element */
1052 tmp = (target_mem_base+(2+i*2)*16)&0xfffffffc;
1053 target_write_u32(target, target_mem_base+24+i*32, tmp);
1054 /* DMACCxControl = TransferSize =1, Source burst size =4,
1055 * Destination burst size = 4, Source transfer width = 32 bit,
1056 * Destination transfer width = 32 bit, Source AHB master select = M0,
1057 * Destination AHB master select = M0, Source increment = 0,
1058 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1059 target_write_u32(target,
1060 target_mem_base+28+i*32,
1061 0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<
1062 31);
1063 }
1064
1065 /* -------LLI for spare area---------
1066 * DMACC0SrcAddr = SLC_DMA_DATA*/
1067 target_write_u32(target, target_mem_base+0+i*32, 0x20020038);
1068 /* DMACCxDestAddr = SRAM */
1069 target_write_u32(target, target_mem_base+4+i*32, target_mem_base+SPARE_OFFS);
1070 /* DMACCxLLI = next element = NULL */
1071 target_write_u32(target, target_mem_base+8+i*32, 0);
1072 /* DMACCxControl = TransferSize =16 for large page or 4 for small page,
1073 * Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1074 * Destination transfer width = 32 bit, Source AHB master select = M0,
1075 * Destination AHB master select = M0, Source increment = 0,
1076 * Destination increment = 1, Terminal count interrupt enable bit = 0*/
1077 target_write_u32(target,
1078 target_mem_base + 12 + i * 32,
1079 (nand->page_size == 2048 ? 0x10 : 0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 |
1080 0<<24 | 0<<25 | 0<<26 | 1<<27 | 0<<31);
1081
1082 /* Enable DMA after channel set up !
1083 LLI only works when DMA is the flow controller!
1084 */
1085 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC),
1086 *FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1087 target_write_u32(target,
1088 0x31000110,
1089 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1090
1091 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1092 target_write_u32(target, 0x20020010, 0x3);
1093
1094 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1095 target_write_u32(target, 0x20020028, 2);
1096
1097 /* SLC_TC */
1098 target_write_u32(target, 0x20020030,
1099 (nand->page_size == 2048 ? 0x840 : 0x210));
1100
1101 if (!lpc3180_tc_ready(nand, 1000)) {
1102 LOG_ERROR("timeout while waiting for completion of DMA");
1103 free(page_buffer);
1104 free(ecc_hw_buffer);
1105 free(ecc_flash_buffer);
1106 target_free_working_area(target, pworking_area);
1107 return ERROR_NAND_OPERATION_FAILED;
1108 }
1109
1110 if (data) {
1111 target_read_memory(target,
1112 target_mem_base+DATA_OFFS,
1113 4,
1114 nand->page_size == 2048 ? 512 : 128,
1115 page_buffer);
1116 memcpy(data, page_buffer, data_size);
1117
1118 LOG_INFO("Page = 0x%" PRIx32 " was read.", page);
1119
1120 /* check hw generated ECC for each 256 bytes block with the saved
1121 *ECC in flash spare area*/
1122 int idx = nand->page_size/0x200;
1123 target_read_memory(target,
1124 target_mem_base+SPARE_OFFS,
1125 4,
1126 16,
1127 ecc_flash_buffer);
1128 target_read_memory(target,
1129 target_mem_base+ECC_OFFS,
1130 4,
1131 8,
1132 ecc_hw_buffer);
1133 for (i = 0; i < idx; i++) {
1134 if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+i*8)) !=
1135 (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+8+i*16)))
1136 LOG_WARNING(
1137 "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
1138 i * 2 + 1, page);
1139 if ((0x00ffffff & *(uint32_t *)(void *)(ecc_hw_buffer+4+i*8)) !=
1140 (0x00ffffff & *(uint32_t *)(void *)(ecc_flash_buffer+12+i*16)))
1141 LOG_WARNING(
1142 "ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32,
1143 i * 2 + 2, page);
1144 }
1145 }
1146
1147 if (oob)
1148 memcpy(oob, ecc_flash_buffer, oob_size);
1149
1150 free(page_buffer);
1151 free(ecc_hw_buffer);
1152 free(ecc_flash_buffer);
1153
1154 target_free_working_area(target, pworking_area);
1155
1156 } else
1157 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
1158 }
1159
1160 return ERROR_OK;
1161 }
1162
1163 static int lpc3180_controller_ready(struct nand_device *nand, int timeout)
1164 {
1165 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1166 struct target *target = nand->target;
1167
1168 if (target->state != TARGET_HALTED) {
1169 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1170 return ERROR_NAND_OPERATION_FAILED;
1171 }
1172
1173 LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout);
1174
1175 do {
1176 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
1177 uint8_t status;
1178
1179 /* Read MLC_ISR, wait for controller to become ready */
1180 target_read_u8(target, 0x200b8048, &status);
1181
1182 if (status & 2) {
1183 LOG_DEBUG("lpc3180_controller_ready count=%d",
1184 timeout);
1185 return 1;
1186 }
1187 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1188 uint32_t status;
1189
1190 /* Read SLC_STAT and check READY bit */
1191 target_read_u32(target, 0x20020018, &status);
1192
1193 if (status & 1) {
1194 LOG_DEBUG("lpc3180_controller_ready count=%d",
1195 timeout);
1196 return 1;
1197 }
1198 }
1199
1200 alive_sleep(1);
1201 } while (timeout-- > 0);
1202
1203 return 0;
1204 }
1205
1206 static int lpc3180_nand_ready(struct nand_device *nand, int timeout)
1207 {
1208 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1209 struct target *target = nand->target;
1210
1211 if (target->state != TARGET_HALTED) {
1212 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1213 return ERROR_NAND_OPERATION_FAILED;
1214 }
1215
1216 LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout);
1217
1218 do {
1219 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER) {
1220 uint8_t status = 0x0;
1221
1222 /* Read MLC_ISR, wait for NAND flash device to become ready */
1223 target_read_u8(target, 0x200b8048, &status);
1224
1225 if (status & 1) {
1226 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1227 timeout);
1228 return 1;
1229 }
1230 } else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1231 uint32_t status = 0x0;
1232
1233 /* Read SLC_STAT and check READY bit */
1234 target_read_u32(target, 0x20020018, &status);
1235
1236 if (status & 1) {
1237 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1238 timeout);
1239 return 1;
1240 }
1241 }
1242
1243 alive_sleep(1);
1244 } while (timeout-- > 0);
1245
1246 return 0;
1247 }
1248
1249 static int lpc3180_tc_ready(struct nand_device *nand, int timeout)
1250 {
1251 struct lpc3180_nand_controller *lpc3180_info = nand->controller_priv;
1252 struct target *target = nand->target;
1253
1254 if (target->state != TARGET_HALTED) {
1255 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1256 return ERROR_NAND_OPERATION_FAILED;
1257 }
1258
1259 LOG_DEBUG("lpc3180_tc_ready count start=%d",
1260 timeout);
1261
1262 do {
1263 if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER) {
1264 uint32_t status = 0x0;
1265 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1266 target_read_u32(target, 0x2002001c, &status);
1267
1268 if (status & 2) {
1269 LOG_DEBUG("lpc3180_tc_ready count=%d",
1270 timeout);
1271 return 1;
1272 }
1273 }
1274
1275 alive_sleep(1);
1276 } while (timeout-- > 0);
1277
1278 return 0;
1279 }
1280
1281 COMMAND_HANDLER(handle_lpc3180_select_command)
1282 {
1283 struct lpc3180_nand_controller *lpc3180_info = NULL;
1284 char *selected[] = {
1285 "no", "mlc", "slc"
1286 };
1287
1288 if ((CMD_ARGC < 1) || (CMD_ARGC > 3))
1289 return ERROR_COMMAND_SYNTAX_ERROR;
1290
1291 unsigned num;
1292 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1293 struct nand_device *nand = get_nand_device_by_num(num);
1294 if (!nand) {
1295 command_print(CMD_CTX, "nand device '#%s' is out of bounds", CMD_ARGV[0]);
1296 return ERROR_OK;
1297 }
1298
1299 lpc3180_info = nand->controller_priv;
1300
1301 if (CMD_ARGC >= 2) {
1302 if (strcmp(CMD_ARGV[1], "mlc") == 0)
1303 lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
1304 else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1305 lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
1306 if (CMD_ARGC == 3 && strcmp(CMD_ARGV[2], "bulk") == 0)
1307 lpc3180_info->is_bulk = 1;
1308 else
1309 lpc3180_info->is_bulk = 0;
1310 } else
1311 return ERROR_COMMAND_SYNTAX_ERROR;
1312 }
1313
1314 if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
1315 command_print(CMD_CTX, "%s controller selected",
1316 selected[lpc3180_info->selected_controller]);
1317 else
1318 command_print(CMD_CTX,
1319 lpc3180_info->is_bulk ? "%s controller selected bulk mode is available" :
1320 "%s controller selected bulk mode is not available",
1321 selected[lpc3180_info->selected_controller]);
1322
1323 return ERROR_OK;
1324 }
1325
1326 static const struct command_registration lpc3180_exec_command_handlers[] = {
1327 {
1328 .name = "select",
1329 .handler = handle_lpc3180_select_command,
1330 .mode = COMMAND_EXEC,
1331 .help =
1332 "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1333 .usage = "bank_id ['mlc'|'slc' ['bulk'] ]",
1334 },
1335 COMMAND_REGISTRATION_DONE
1336 };
1337 static const struct command_registration lpc3180_command_handler[] = {
1338 {
1339 .name = "lpc3180",
1340 .mode = COMMAND_ANY,
1341 .help = "LPC3180 NAND flash controller commands",
1342 .usage = "",
1343 .chain = lpc3180_exec_command_handlers,
1344 },
1345 COMMAND_REGISTRATION_DONE
1346 };
1347
1348 struct nand_flash_controller lpc3180_nand_controller = {
1349 .name = "lpc3180",
1350 .commands = lpc3180_command_handler,
1351 .nand_device_command = lpc3180_nand_device_command,
1352 .init = lpc3180_init,
1353 .reset = lpc3180_reset,
1354 .command = lpc3180_command,
1355 .address = lpc3180_address,
1356 .write_data = lpc3180_write_data,
1357 .read_data = lpc3180_read_data,
1358 .write_page = lpc3180_write_page,
1359 .read_page = lpc3180_read_page,
1360 .nand_ready = lpc3180_nand_ready,
1361 };
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