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flash: iterating over an address range now handles multiple banks
[openocd.git] / src / flash / nor / cfi.c
blob43e19b5f7b4d6d72d4b4eec2649b5ef319e2527b
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24 #ifdef HAVE_CONFIG_H
25 #include "config.h"
26 #endif
27
28 #include "imp.h"
29 #include "cfi.h"
30 #include "non_cfi.h"
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34
35
36 #define CFI_MAX_BUS_WIDTH 4
37 #define CFI_MAX_CHIP_WIDTH 4
38
39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
40 #define CFI_MAX_INTEL_CODESIZE 256
41
42 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
43 {
44 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
45 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
46 };
47
48 /* CFI fixups foward declarations */
49 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
51 static void cfi_fixup_reversed_erase_regions(struct flash_bank *flash, void *param);
52
53 /* fixup after reading cmdset 0002 primary query table */
54 static const struct cfi_fixup cfi_0002_fixups[] = {
55 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
59 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
61 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
62 {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
63 {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
64 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
65 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
66 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
67 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
68 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
69 {0, 0, NULL, NULL}
70 };
71
72 /* fixup after reading cmdset 0001 primary query table */
73 static const struct cfi_fixup cfi_0001_fixups[] = {
74 {0, 0, NULL, NULL}
75 };
76
77 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
78 {
79 struct cfi_flash_bank *cfi_info = bank->driver_priv;
80 const struct cfi_fixup *f;
81
82 for (f = fixups; f->fixup; f++)
83 {
84 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
85 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
86 {
87 f->fixup(bank, f->param);
88 }
89 }
90 }
91
92 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
93 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
94 {
95 struct cfi_flash_bank *cfi_info = bank->driver_priv;
96
97 if (cfi_info->x16_as_x8) offset *= 2;
98
99 /* while the sector list isn't built, only accesses to sector 0 work */
100 if (sector == 0)
101 return bank->base + offset * bank->bus_width;
102 else
103 {
104 if (!bank->sectors)
105 {
106 LOG_ERROR("BUG: sector list not yet built");
107 exit(-1);
108 }
109 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
110 }
111 }
112
113 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
114 {
115 int i;
116
117 /* clear whole buffer, to ensure bits that exceed the bus_width
118 * are set to zero
119 */
120 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
121 cmd_buf[i] = 0;
122
123 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
124 {
125 for (i = bank->bus_width; i > 0; i--)
126 {
127 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
128 }
129 }
130 else
131 {
132 for (i = 1; i <= bank->bus_width; i++)
133 {
134 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
135 }
136 }
137 }
138
139 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
140 {
141 uint8_t command[CFI_MAX_BUS_WIDTH];
142
143 cfi_command(bank, cmd, command);
144 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
145 }
146
147 /* read unsigned 8-bit value from the bank
148 * flash banks are expected to be made of similar chips
149 * the query result should be the same for all
150 */
151 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
152 {
153 struct target *target = bank->target;
154 uint8_t data[CFI_MAX_BUS_WIDTH];
155
156 int retval;
157 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
158 if (retval != ERROR_OK)
159 return retval;
160
161 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
162 *val = data[0];
163 else
164 *val = data[bank->bus_width - 1];
165
166 return ERROR_OK;
167 }
168
169 /* read unsigned 8-bit value from the bank
170 * in case of a bank made of multiple chips,
171 * the individual values are ORed
172 */
173 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
174 {
175 struct target *target = bank->target;
176 uint8_t data[CFI_MAX_BUS_WIDTH];
177 int i;
178
179 int retval;
180 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
181 if (retval != ERROR_OK)
182 return retval;
183
184 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
185 {
186 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
187 data[0] |= data[i];
188
189 *val = data[0];
190 }
191 else
192 {
193 uint8_t value = 0;
194 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
195 value |= data[bank->bus_width - 1 - i];
196
197 *val = value;
198 }
199 return ERROR_OK;
200 }
201
202 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
203 {
204 struct target *target = bank->target;
205 struct cfi_flash_bank *cfi_info = bank->driver_priv;
206 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
207 int retval;
208
209 if (cfi_info->x16_as_x8)
210 {
211 uint8_t i;
212 for (i = 0;i < 2;i++)
213 {
214 retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
215 &data[i*bank->bus_width]);
216 if (retval != ERROR_OK)
217 return retval;
218 }
219 } else
220 {
221 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
222 if (retval != ERROR_OK)
223 return retval;
224 }
225
226 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
227 *val = data[0] | data[bank->bus_width] << 8;
228 else
229 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
230
231 return ERROR_OK;
232 }
233
234 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
235 {
236 struct target *target = bank->target;
237 struct cfi_flash_bank *cfi_info = bank->driver_priv;
238 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
239 int retval;
240
241 if (cfi_info->x16_as_x8)
242 {
243 uint8_t i;
244 for (i = 0;i < 4;i++)
245 {
246 retval = target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
247 &data[i*bank->bus_width]);
248 if (retval != ERROR_OK)
249 return retval;
250 }
251 }
252 else
253 {
254 retval = target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
255 if (retval != ERROR_OK)
256 return retval;
257 }
258
259 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
260 *val = data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
261 else
262 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
263 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
264
265 return ERROR_OK;
266 }
267
268 static int cfi_reset(struct flash_bank *bank)
269 {
270 struct cfi_flash_bank *cfi_info = bank->driver_priv;
271 int retval = ERROR_OK;
272
273 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
274 {
275 return retval;
276 }
277
278 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
279 {
280 return retval;
281 }
282
283 if (cfi_info->manufacturer == 0x20 &&
284 (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
285 {
286 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
287 * so we send an extra 0xF0 reset to fix the bug */
288 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
289 {
290 return retval;
291 }
292 }
293
294 return retval;
295 }
296
297 static void cfi_intel_clear_status_register(struct flash_bank *bank)
298 {
299 struct target *target = bank->target;
300
301 if (target->state != TARGET_HALTED)
302 {
303 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
304 exit(-1);
305 }
306
307 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
308 }
309
310 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
311 {
312 uint8_t status;
313
314 int retval = ERROR_OK;
315
316 for (;;)
317 {
318 if (timeout-- < 0)
319 {
320 LOG_ERROR("timeout while waiting for WSM to become ready");
321 return ERROR_FAIL;
322 }
323
324 retval = cfi_get_u8(bank, 0, 0x0, &status);
325 if (retval != ERROR_OK)
326 return retval;
327
328 if (status & 0x80)
329 break;
330
331 alive_sleep(1);
332 }
333
334 /* mask out bit 0 (reserved) */
335 status = status & 0xfe;
336
337 LOG_DEBUG("status: 0x%x", status);
338
339 if (status != 0x80)
340 {
341 LOG_ERROR("status register: 0x%x", status);
342 if (status & 0x2)
343 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
344 if (status & 0x4)
345 LOG_ERROR("Program suspended");
346 if (status & 0x8)
347 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
348 if (status & 0x10)
349 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
350 if (status & 0x20)
351 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
352 if (status & 0x40)
353 LOG_ERROR("Block Erase Suspended");
354
355 cfi_intel_clear_status_register(bank);
356
357 retval = ERROR_FAIL;
358 }
359
360 *val = status;
361 return retval;
362 }
363
364 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
365 {
366 uint8_t status, oldstatus;
367 struct cfi_flash_bank *cfi_info = bank->driver_priv;
368 int retval;
369
370 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
371 if (retval != ERROR_OK)
372 return retval;
373
374 do {
375 retval = cfi_get_u8(bank, 0, 0x0, &status);
376
377 if (retval != ERROR_OK)
378 return retval;
379
380 if ((status ^ oldstatus) & 0x40) {
381 if (status & cfi_info->status_poll_mask & 0x20) {
382 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
383 if (retval != ERROR_OK)
384 return retval;
385 retval = cfi_get_u8(bank, 0, 0x0, &status);
386 if (retval != ERROR_OK)
387 return retval;
388 if ((status ^ oldstatus) & 0x40) {
389 LOG_ERROR("dq5 timeout, status: 0x%x", status);
390 return(ERROR_FLASH_OPERATION_FAILED);
391 } else {
392 LOG_DEBUG("status: 0x%x", status);
393 return(ERROR_OK);
394 }
395 }
396 } else { /* no toggle: finished, OK */
397 LOG_DEBUG("status: 0x%x", status);
398 return(ERROR_OK);
399 }
400
401 oldstatus = status;
402 alive_sleep(1);
403 } while (timeout-- > 0);
404
405 LOG_ERROR("timeout, status: 0x%x", status);
406
407 return(ERROR_FLASH_BUSY);
408 }
409
410 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
411 {
412 int retval;
413 struct cfi_flash_bank *cfi_info = bank->driver_priv;
414 struct cfi_intel_pri_ext *pri_ext;
415
416 if (cfi_info->pri_ext)
417 free(cfi_info->pri_ext);
418
419 pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
420 if (pri_ext == NULL)
421 {
422 LOG_ERROR("Out of memory");
423 return ERROR_FAIL;
424 }
425 cfi_info->pri_ext = pri_ext;
426
427 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
428 if (retval != ERROR_OK)
429 return retval;
430 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
431 if (retval != ERROR_OK)
432 return retval;
433 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
434 if (retval != ERROR_OK)
435 return retval;
436
437 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
438 {
439 if ((retval = cfi_reset(bank)) != ERROR_OK)
440 {
441 return retval;
442 }
443 LOG_ERROR("Could not read bank flash bank information");
444 return ERROR_FLASH_BANK_INVALID;
445 }
446
447 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
448 if (retval != ERROR_OK)
449 return retval;
450 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
451 if (retval != ERROR_OK)
452 return retval;
453
454 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
455
456 retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
457 if (retval != ERROR_OK)
458 return retval;
459 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
460 if (retval != ERROR_OK)
461 return retval;
462 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
463 if (retval != ERROR_OK)
464 return retval;
465
466 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
467 pri_ext->feature_support,
468 pri_ext->suspend_cmd_support,
469 pri_ext->blk_status_reg_mask);
470
471 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
472 if (retval != ERROR_OK)
473 return retval;
474 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
475 if (retval != ERROR_OK)
476 return retval;
477
478 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
479 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
480 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
481
482 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
483 if (retval != ERROR_OK)
484 return retval;
485 if (pri_ext->num_protection_fields != 1)
486 {
487 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
488 }
489
490 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
491 if (retval != ERROR_OK)
492 return retval;
493 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
494 if (retval != ERROR_OK)
495 return retval;
496 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
497 if (retval != ERROR_OK)
498 return retval;
499
500 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
501
502 return ERROR_OK;
503 }
504
505 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
506 {
507 int retval;
508 struct cfi_flash_bank *cfi_info = bank->driver_priv;
509 struct cfi_spansion_pri_ext *pri_ext;
510
511 if (cfi_info->pri_ext)
512 free(cfi_info->pri_ext);
513
514 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
515 if (pri_ext == NULL)
516 {
517 LOG_ERROR("Out of memory");
518 return ERROR_FAIL;
519 }
520 cfi_info->pri_ext = pri_ext;
521
522 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
523 if (retval != ERROR_OK)
524 return retval;
525 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
526 if (retval != ERROR_OK)
527 return retval;
528 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
529 if (retval != ERROR_OK)
530 return retval;
531
532 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
533 {
534 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
535 {
536 return retval;
537 }
538 LOG_ERROR("Could not read spansion bank information");
539 return ERROR_FLASH_BANK_INVALID;
540 }
541
542 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
543 if (retval != ERROR_OK)
544 return retval;
545 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
546 if (retval != ERROR_OK)
547 return retval;
548
549 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
550
551 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
552 if (retval != ERROR_OK)
553 return retval;
554 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
555 if (retval != ERROR_OK)
556 return retval;
557 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
558 if (retval != ERROR_OK)
559 return retval;
560 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
561 if (retval != ERROR_OK)
562 return retval;
563 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
564 if (retval != ERROR_OK)
565 return retval;
566 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
567 if (retval != ERROR_OK)
568 return retval;
569 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
570 if (retval != ERROR_OK)
571 return retval;
572 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
573 if (retval != ERROR_OK)
574 return retval;
575 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
576 if (retval != ERROR_OK)
577 return retval;
578 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
579 if (retval != ERROR_OK)
580 return retval;
581 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
582 if (retval != ERROR_OK)
583 return retval;
584
585 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
586 pri_ext->EraseSuspend, pri_ext->BlkProt);
587
588 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
589 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
590
591 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
592
593
594 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
595 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
596 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
597
598 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
599
600 /* default values for implementation specific workarounds */
601 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
602 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
603 pri_ext->_reversed_geometry = 0;
604
605 return ERROR_OK;
606 }
607
608 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
609 {
610 int retval;
611 struct cfi_atmel_pri_ext atmel_pri_ext;
612 struct cfi_flash_bank *cfi_info = bank->driver_priv;
613 struct cfi_spansion_pri_ext *pri_ext;
614
615 if (cfi_info->pri_ext)
616 free(cfi_info->pri_ext);
617
618 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
619 if (pri_ext == NULL)
620 {
621 LOG_ERROR("Out of memory");
622 return ERROR_FAIL;
623 }
624
625 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
626 * but a different primary extended query table.
627 * We read the atmel table, and prepare a valid AMD/Spansion query table.
628 */
629
630 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
631
632 cfi_info->pri_ext = pri_ext;
633
634 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
635 if (retval != ERROR_OK)
636 return retval;
637 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
638 if (retval != ERROR_OK)
639 return retval;
640 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
641 if (retval != ERROR_OK)
642 return retval;
643
644 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
645 {
646 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
647 {
648 return retval;
649 }
650 LOG_ERROR("Could not read atmel bank information");
651 return ERROR_FLASH_BANK_INVALID;
652 }
653
654 pri_ext->pri[0] = atmel_pri_ext.pri[0];
655 pri_ext->pri[1] = atmel_pri_ext.pri[1];
656 pri_ext->pri[2] = atmel_pri_ext.pri[2];
657
658 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
659 if (retval != ERROR_OK)
660 return retval;
661 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
662 if (retval != ERROR_OK)
663 return retval;
664
665 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
666
667 pri_ext->major_version = atmel_pri_ext.major_version;
668 pri_ext->minor_version = atmel_pri_ext.minor_version;
669
670 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
671 if (retval != ERROR_OK)
672 return retval;
673 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
674 if (retval != ERROR_OK)
675 return retval;
676 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
677 if (retval != ERROR_OK)
678 return retval;
679 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
680 if (retval != ERROR_OK)
681 return retval;
682
683 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
684 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
685
686 if (atmel_pri_ext.features & 0x02)
687 pri_ext->EraseSuspend = 2;
688
689 if (atmel_pri_ext.bottom_boot)
690 pri_ext->TopBottom = 2;
691 else
692 pri_ext->TopBottom = 3;
693
694 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
695 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
696
697 return ERROR_OK;
698 }
699
700 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
701 {
702 struct cfi_flash_bank *cfi_info = bank->driver_priv;
703
704 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
705 {
706 return cfi_read_atmel_pri_ext(bank);
707 }
708 else
709 {
710 return cfi_read_spansion_pri_ext(bank);
711 }
712 }
713
714 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
715 {
716 int printed;
717 struct cfi_flash_bank *cfi_info = bank->driver_priv;
718 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
719
720 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
721 buf += printed;
722 buf_size -= printed;
723
724 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
725 pri_ext->pri[1], pri_ext->pri[2],
726 pri_ext->major_version, pri_ext->minor_version);
727 buf += printed;
728 buf_size -= printed;
729
730 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
731 (pri_ext->SiliconRevision) >> 2,
732 (pri_ext->SiliconRevision) & 0x03);
733 buf += printed;
734 buf_size -= printed;
735
736 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
737 pri_ext->EraseSuspend,
738 pri_ext->BlkProt);
739 buf += printed;
740 buf_size -= printed;
741
742 printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
743 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
744 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
745
746 return ERROR_OK;
747 }
748
749 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
750 {
751 int printed;
752 struct cfi_flash_bank *cfi_info = bank->driver_priv;
753 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
754
755 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
756 buf += printed;
757 buf_size -= printed;
758
759 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
760 buf += printed;
761 buf_size -= printed;
762
763 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
764 buf += printed;
765 buf_size -= printed;
766
767 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
768 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
769 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
770 buf += printed;
771 buf_size -= printed;
772
773 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
774
775 return ERROR_OK;
776 }
777
778 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
779 */
780 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
781 {
782 struct cfi_flash_bank *cfi_info;
783
784 if (CMD_ARGC < 6)
785 {
786 LOG_WARNING("incomplete flash_bank cfi configuration");
787 return ERROR_FLASH_BANK_INVALID;
788 }
789
790 /* both widths must:
791 * - not exceed max value;
792 * - not be null;
793 * - be equal to a power of 2.
794 * bus must be wide enought to hold one chip */
795 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
796 || (bank->bus_width > CFI_MAX_BUS_WIDTH)
797 || (bank->chip_width == 0)
798 || (bank->bus_width == 0)
799 || (bank->chip_width & (bank->chip_width - 1))
800 || (bank->bus_width & (bank->bus_width - 1))
801 || (bank->chip_width > bank->bus_width))
802 {
803 LOG_ERROR("chip and bus width have to specified in bytes");
804 return ERROR_FLASH_BANK_INVALID;
805 }
806
807 cfi_info = malloc(sizeof(struct cfi_flash_bank));
808 cfi_info->probed = 0;
809 cfi_info->erase_region_info = NULL;
810 cfi_info->pri_ext = NULL;
811 bank->driver_priv = cfi_info;
812
813 cfi_info->write_algorithm = NULL;
814
815 cfi_info->x16_as_x8 = 0;
816 cfi_info->jedec_probe = 0;
817 cfi_info->not_cfi = 0;
818
819 for (unsigned i = 6; i < CMD_ARGC; i++)
820 {
821 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
822 {
823 cfi_info->x16_as_x8 = 1;
824 }
825 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
826 {
827 cfi_info->jedec_probe = 1;
828 }
829 }
830
831 cfi_info->write_algorithm = NULL;
832
833 /* bank wasn't probed yet */
834 cfi_info->qry[0] = 0xff;
835
836 return ERROR_OK;
837 }
838
839 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
840 {
841 int retval;
842 struct cfi_flash_bank *cfi_info = bank->driver_priv;
843 int i;
844
845 cfi_intel_clear_status_register(bank);
846
847 for (i = first; i <= last; i++)
848 {
849 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
850 {
851 return retval;
852 }
853
854 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
855 {
856 return retval;
857 }
858
859 uint8_t status;
860 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ), &status);
861 if (retval != ERROR_OK)
862 return retval;
863
864 if (status == 0x80)
865 bank->sectors[i].is_erased = 1;
866 else
867 {
868 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
869 {
870 return retval;
871 }
872
873 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
874 return ERROR_FLASH_OPERATION_FAILED;
875 }
876 }
877
878 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
879 }
880
881 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
882 {
883 int retval;
884 struct cfi_flash_bank *cfi_info = bank->driver_priv;
885 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
886 int i;
887
888 for (i = first; i <= last; i++)
889 {
890 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
891 {
892 return retval;
893 }
894
895 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
896 {
897 return retval;
898 }
899
900 if ((retval = cfi_send_command(bank, 0x80, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
901 {
902 return retval;
903 }
904
905 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
906 {
907 return retval;
908 }
909
910 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
911 {
912 return retval;
913 }
914
915 if ((retval = cfi_send_command(bank, 0x30, flash_address(bank, i, 0x0))) != ERROR_OK)
916 {
917 return retval;
918 }
919
920 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
921 bank->sectors[i].is_erased = 1;
922 else
923 {
924 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
925 {
926 return retval;
927 }
928
929 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
930 return ERROR_FLASH_OPERATION_FAILED;
931 }
932 }
933
934 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
935 }
936
937 static int cfi_erase(struct flash_bank *bank, int first, int last)
938 {
939 struct cfi_flash_bank *cfi_info = bank->driver_priv;
940
941 if (bank->target->state != TARGET_HALTED)
942 {
943 LOG_ERROR("Target not halted");
944 return ERROR_TARGET_NOT_HALTED;
945 }
946
947 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
948 {
949 return ERROR_FLASH_SECTOR_INVALID;
950 }
951
952 if (cfi_info->qry[0] != 'Q')
953 return ERROR_FLASH_BANK_NOT_PROBED;
954
955 switch (cfi_info->pri_id)
956 {
957 case 1:
958 case 3:
959 return cfi_intel_erase(bank, first, last);
960 break;
961 case 2:
962 return cfi_spansion_erase(bank, first, last);
963 break;
964 default:
965 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
966 break;
967 }
968
969 return ERROR_OK;
970 }
971
972 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
973 {
974 int retval;
975 struct cfi_flash_bank *cfi_info = bank->driver_priv;
976 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
977 int retry = 0;
978 int i;
979
980 /* if the device supports neither legacy lock/unlock (bit 3) nor
981 * instant individual block locking (bit 5).
982 */
983 if (!(pri_ext->feature_support & 0x28))
984 {
985 LOG_ERROR("lock/unlock not supported on flash");
986 return ERROR_FLASH_OPERATION_FAILED;
987 }
988
989 cfi_intel_clear_status_register(bank);
990
991 for (i = first; i <= last; i++)
992 {
993 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
994 {
995 return retval;
996 }
997 if (set)
998 {
999 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1000 {
1001 return retval;
1002 }
1003 bank->sectors[i].is_protected = 1;
1004 }
1005 else
1006 {
1007 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1008 {
1009 return retval;
1010 }
1011 bank->sectors[i].is_protected = 0;
1012 }
1013
1014 /* instant individual block locking doesn't require reading of the status register */
1015 if (!(pri_ext->feature_support & 0x20))
1016 {
1017 /* Clear lock bits operation may take up to 1.4s */
1018 uint8_t status;
1019 retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1020 if (retval != ERROR_OK)
1021 return retval;
1022 }
1023 else
1024 {
1025 uint8_t block_status;
1026 /* read block lock bit, to verify status */
1027 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1028 {
1029 return retval;
1030 }
1031 retval = cfi_get_u8(bank, i, 0x2, &block_status);
1032 if (retval != ERROR_OK)
1033 return retval;
1034
1035 if ((block_status & 0x1) != set)
1036 {
1037 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
1038 if ((retval = cfi_send_command(bank, 0x70, flash_address(bank, 0, 0x55))) != ERROR_OK)
1039 {
1040 return retval;
1041 }
1042 uint8_t status;
1043 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1044 if (retval != ERROR_OK)
1045 return retval;
1046
1047 if (retry > 10)
1048 return ERROR_FLASH_OPERATION_FAILED;
1049 else
1050 {
1051 i--;
1052 retry++;
1053 }
1054 }
1055 }
1056 }
1057
1058 /* if the device doesn't support individual block lock bits set/clear,
1059 * all blocks have been unlocked in parallel, so we set those that should be protected
1060 */
1061 if ((!set) && (!(pri_ext->feature_support & 0x20)))
1062 {
1063 /* FIX!!! this code path is broken!!!
1064 *
1065 * The correct approach is:
1066 *
1067 * 1. read out current protection status
1068 *
1069 * 2. override read out protection status w/unprotected.
1070 *
1071 * 3. re-protect what should be protected.
1072 *
1073 */
1074 for (i = 0; i < bank->num_sectors; i++)
1075 {
1076 if (bank->sectors[i].is_protected == 1)
1077 {
1078 cfi_intel_clear_status_register(bank);
1079
1080 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1081 {
1082 return retval;
1083 }
1084
1085 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1086 {
1087 return retval;
1088 }
1089
1090 uint8_t status;
1091 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1092 if (retval != ERROR_OK)
1093 return retval;
1094 }
1095 }
1096 }
1097
1098 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1099 }
1100
1101 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1102 {
1103 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1104
1105 if (bank->target->state != TARGET_HALTED)
1106 {
1107 LOG_ERROR("Target not halted");
1108 return ERROR_TARGET_NOT_HALTED;
1109 }
1110
1111 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1112 {
1113 LOG_ERROR("Invalid sector range");
1114 return ERROR_FLASH_SECTOR_INVALID;
1115 }
1116
1117 if (cfi_info->qry[0] != 'Q')
1118 return ERROR_FLASH_BANK_NOT_PROBED;
1119
1120 switch (cfi_info->pri_id)
1121 {
1122 case 1:
1123 case 3:
1124 return cfi_intel_protect(bank, set, first, last);
1125 break;
1126 default:
1127 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1128 return ERROR_FAIL;
1129 }
1130 }
1131
1132 /* Convert code image to target endian */
1133 /* FIXME create general block conversion fcts in target.c?) */
1134 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
1135 {
1136 uint32_t i;
1137 for (i = 0; i< count; i++)
1138 {
1139 target_buffer_set_u32(target, dest, *src);
1140 dest += 4;
1141 src++;
1142 }
1143 }
1144
1145 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1146 {
1147 struct target *target = bank->target;
1148
1149 uint8_t buf[CFI_MAX_BUS_WIDTH];
1150 cfi_command(bank, cmd, buf);
1151 switch (bank->bus_width)
1152 {
1153 case 1 :
1154 return buf[0];
1155 break;
1156 case 2 :
1157 return target_buffer_get_u16(target, buf);
1158 break;
1159 case 4 :
1160 return target_buffer_get_u32(target, buf);
1161 break;
1162 default :
1163 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1164 return 0;
1165 }
1166 }
1167
1168 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1169 {
1170 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1171 struct target *target = bank->target;
1172 struct reg_param reg_params[7];
1173 struct arm_algorithm armv4_5_info;
1174 struct working_area *source;
1175 uint32_t buffer_size = 32768;
1176 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1177
1178 /* algorithm register usage:
1179 * r0: source address (in RAM)
1180 * r1: target address (in Flash)
1181 * r2: count
1182 * r3: flash write command
1183 * r4: status byte (returned to host)
1184 * r5: busy test pattern
1185 * r6: error test pattern
1186 */
1187
1188 static const uint32_t word_32_code[] = {
1189 0xe4904004, /* loop: ldr r4, [r0], #4 */
1190 0xe5813000, /* str r3, [r1] */
1191 0xe5814000, /* str r4, [r1] */
1192 0xe5914000, /* busy: ldr r4, [r1] */
1193 0xe0047005, /* and r7, r4, r5 */
1194 0xe1570005, /* cmp r7, r5 */
1195 0x1afffffb, /* bne busy */
1196 0xe1140006, /* tst r4, r6 */
1197 0x1a000003, /* bne done */
1198 0xe2522001, /* subs r2, r2, #1 */
1199 0x0a000001, /* beq done */
1200 0xe2811004, /* add r1, r1 #4 */
1201 0xeafffff2, /* b loop */
1202 0xeafffffe /* done: b -2 */
1203 };
1204
1205 static const uint32_t word_16_code[] = {
1206 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1207 0xe1c130b0, /* strh r3, [r1] */
1208 0xe1c140b0, /* strh r4, [r1] */
1209 0xe1d140b0, /* busy ldrh r4, [r1] */
1210 0xe0047005, /* and r7, r4, r5 */
1211 0xe1570005, /* cmp r7, r5 */
1212 0x1afffffb, /* bne busy */
1213 0xe1140006, /* tst r4, r6 */
1214 0x1a000003, /* bne done */
1215 0xe2522001, /* subs r2, r2, #1 */
1216 0x0a000001, /* beq done */
1217 0xe2811002, /* add r1, r1 #2 */
1218 0xeafffff2, /* b loop */
1219 0xeafffffe /* done: b -2 */
1220 };
1221
1222 static const uint32_t word_8_code[] = {
1223 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1224 0xe5c13000, /* strb r3, [r1] */
1225 0xe5c14000, /* strb r4, [r1] */
1226 0xe5d14000, /* busy ldrb r4, [r1] */
1227 0xe0047005, /* and r7, r4, r5 */
1228 0xe1570005, /* cmp r7, r5 */
1229 0x1afffffb, /* bne busy */
1230 0xe1140006, /* tst r4, r6 */
1231 0x1a000003, /* bne done */
1232 0xe2522001, /* subs r2, r2, #1 */
1233 0x0a000001, /* beq done */
1234 0xe2811001, /* add r1, r1 #1 */
1235 0xeafffff2, /* b loop */
1236 0xeafffffe /* done: b -2 */
1237 };
1238 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1239 const uint32_t *target_code_src;
1240 uint32_t target_code_size;
1241 int retval = ERROR_OK;
1242
1243
1244 cfi_intel_clear_status_register(bank);
1245
1246 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1247 armv4_5_info.core_mode = ARM_MODE_SVC;
1248 armv4_5_info.core_state = ARM_STATE_ARM;
1249
1250 /* If we are setting up the write_algorith, we need target_code_src */
1251 /* if not we only need target_code_size. */
1252
1253 /* However, we don't want to create multiple code paths, so we */
1254 /* do the unecessary evaluation of target_code_src, which the */
1255 /* compiler will probably nicely optimize away if not needed */
1256
1257 /* prepare algorithm code for target endian */
1258 switch (bank->bus_width)
1259 {
1260 case 1 :
1261 target_code_src = word_8_code;
1262 target_code_size = sizeof(word_8_code);
1263 break;
1264 case 2 :
1265 target_code_src = word_16_code;
1266 target_code_size = sizeof(word_16_code);
1267 break;
1268 case 4 :
1269 target_code_src = word_32_code;
1270 target_code_size = sizeof(word_32_code);
1271 break;
1272 default:
1273 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1274 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1275 }
1276
1277 /* flash write code */
1278 if (!cfi_info->write_algorithm)
1279 {
1280 if (target_code_size > sizeof(target_code))
1281 {
1282 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1284 }
1285 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1286
1287 /* Get memory for block write handler */
1288 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1289 if (retval != ERROR_OK)
1290 {
1291 LOG_WARNING("No working area available, can't do block memory writes");
1292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1293 };
1294
1295 /* write algorithm code to working area */
1296 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1297 if (retval != ERROR_OK)
1298 {
1299 LOG_ERROR("Unable to write block write code to target");
1300 goto cleanup;
1301 }
1302 }
1303
1304 /* Get a workspace buffer for the data to flash starting with 32k size.
1305 Half size until buffer would be smaller 256 Bytem then fail back */
1306 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1307 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1308 {
1309 buffer_size /= 2;
1310 if (buffer_size <= 256)
1311 {
1312 LOG_WARNING("no large enough working area available, can't do block memory writes");
1313 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1314 goto cleanup;
1315 }
1316 };
1317
1318 /* setup algo registers */
1319 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1320 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1321 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1322 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1323 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1324 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1325 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1326
1327 /* prepare command and status register patterns */
1328 write_command_val = cfi_command_val(bank, 0x40);
1329 busy_pattern_val = cfi_command_val(bank, 0x80);
1330 error_pattern_val = cfi_command_val(bank, 0x7e);
1331
1332 LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1333
1334 /* Programming main loop */
1335 while (count > 0)
1336 {
1337 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1338 uint32_t wsm_error;
1339
1340 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1341 {
1342 goto cleanup;
1343 }
1344
1345 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1346 buf_set_u32(reg_params[1].value, 0, 32, address);
1347 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1348
1349 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1350 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1351 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1352
1353 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1354
1355 /* Execute algorithm, assume breakpoint for last instruction */
1356 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1357 cfi_info->write_algorithm->address,
1358 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1359 10000, /* 10s should be enough for max. 32k of data */
1360 &armv4_5_info);
1361
1362 /* On failure try a fall back to direct word writes */
1363 if (retval != ERROR_OK)
1364 {
1365 cfi_intel_clear_status_register(bank);
1366 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1367 retval = ERROR_FLASH_OPERATION_FAILED;
1368 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1369 /* FIXME To allow fall back or recovery, we must save the actual status
1370 somewhere, so that a higher level code can start recovery. */
1371 goto cleanup;
1372 }
1373
1374 /* Check return value from algo code */
1375 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1376 if (wsm_error)
1377 {
1378 /* read status register (outputs debug inforation) */
1379 uint8_t status;
1380 cfi_intel_wait_status_busy(bank, 100, &status);
1381 cfi_intel_clear_status_register(bank);
1382 retval = ERROR_FLASH_OPERATION_FAILED;
1383 goto cleanup;
1384 }
1385
1386 buffer += thisrun_count;
1387 address += thisrun_count;
1388 count -= thisrun_count;
1389
1390 keep_alive();
1391 }
1392
1393 /* free up resources */
1394 cleanup:
1395 if (source)
1396 target_free_working_area(target, source);
1397
1398 if (cfi_info->write_algorithm)
1399 {
1400 target_free_working_area(target, cfi_info->write_algorithm);
1401 cfi_info->write_algorithm = NULL;
1402 }
1403
1404 destroy_reg_param(&reg_params[0]);
1405 destroy_reg_param(&reg_params[1]);
1406 destroy_reg_param(&reg_params[2]);
1407 destroy_reg_param(&reg_params[3]);
1408 destroy_reg_param(&reg_params[4]);
1409 destroy_reg_param(&reg_params[5]);
1410 destroy_reg_param(&reg_params[6]);
1411
1412 return retval;
1413 }
1414
1415 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1416 {
1417 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1418 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1419 struct target *target = bank->target;
1420 struct reg_param reg_params[10];
1421 struct arm_algorithm armv4_5_info;
1422 struct working_area *source;
1423 uint32_t buffer_size = 32768;
1424 uint32_t status;
1425 int retval = ERROR_OK;
1426
1427 /* input parameters - */
1428 /* R0 = source address */
1429 /* R1 = destination address */
1430 /* R2 = number of writes */
1431 /* R3 = flash write command */
1432 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1433 /* output parameters - */
1434 /* R5 = 0x80 ok 0x00 bad */
1435 /* temp registers - */
1436 /* R6 = value read from flash to test status */
1437 /* R7 = holding register */
1438 /* unlock registers - */
1439 /* R8 = unlock1_addr */
1440 /* R9 = unlock1_cmd */
1441 /* R10 = unlock2_addr */
1442 /* R11 = unlock2_cmd */
1443
1444 static const uint32_t word_32_code[] = {
1445 /* 00008100 <sp_32_code>: */
1446 0xe4905004, /* ldr r5, [r0], #4 */
1447 0xe5889000, /* str r9, [r8] */
1448 0xe58ab000, /* str r11, [r10] */
1449 0xe5883000, /* str r3, [r8] */
1450 0xe5815000, /* str r5, [r1] */
1451 0xe1a00000, /* nop */
1452 /* */
1453 /* 00008110 <sp_32_busy>: */
1454 0xe5916000, /* ldr r6, [r1] */
1455 0xe0257006, /* eor r7, r5, r6 */
1456 0xe0147007, /* ands r7, r4, r7 */
1457 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1458 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1459 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1460 0xe5916000, /* ldr r6, [r1] */
1461 0xe0257006, /* eor r7, r5, r6 */
1462 0xe0147007, /* ands r7, r4, r7 */
1463 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1464 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1465 0x1a000004, /* bne 8154 <sp_32_done> */
1466 /* */
1467 /* 00008140 <sp_32_cont>: */
1468 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1469 0x03a05080, /* moveq r5, #128 ; 0x80 */
1470 0x0a000001, /* beq 8154 <sp_32_done> */
1471 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1472 0xeaffffe8, /* b 8100 <sp_32_code> */
1473 /* */
1474 /* 00008154 <sp_32_done>: */
1475 0xeafffffe /* b 8154 <sp_32_done> */
1476 };
1477
1478 static const uint32_t word_16_code[] = {
1479 /* 00008158 <sp_16_code>: */
1480 0xe0d050b2, /* ldrh r5, [r0], #2 */
1481 0xe1c890b0, /* strh r9, [r8] */
1482 0xe1cab0b0, /* strh r11, [r10] */
1483 0xe1c830b0, /* strh r3, [r8] */
1484 0xe1c150b0, /* strh r5, [r1] */
1485 0xe1a00000, /* nop (mov r0,r0) */
1486 /* */
1487 /* 00008168 <sp_16_busy>: */
1488 0xe1d160b0, /* ldrh r6, [r1] */
1489 0xe0257006, /* eor r7, r5, r6 */
1490 0xe0147007, /* ands r7, r4, r7 */
1491 0x0a000007, /* beq 8198 <sp_16_cont> */
1492 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1493 0x0afffff9, /* beq 8168 <sp_16_busy> */
1494 0xe1d160b0, /* ldrh r6, [r1] */
1495 0xe0257006, /* eor r7, r5, r6 */
1496 0xe0147007, /* ands r7, r4, r7 */
1497 0x0a000001, /* beq 8198 <sp_16_cont> */
1498 0xe3a05000, /* mov r5, #0 ; 0x0 */
1499 0x1a000004, /* bne 81ac <sp_16_done> */
1500 /* */
1501 /* 00008198 <sp_16_cont>: */
1502 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1503 0x03a05080, /* moveq r5, #128 ; 0x80 */
1504 0x0a000001, /* beq 81ac <sp_16_done> */
1505 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1506 0xeaffffe8, /* b 8158 <sp_16_code> */
1507 /* */
1508 /* 000081ac <sp_16_done>: */
1509 0xeafffffe /* b 81ac <sp_16_done> */
1510 };
1511
1512 static const uint32_t word_16_code_dq7only[] = {
1513 /* <sp_16_code>: */
1514 0xe0d050b2, /* ldrh r5, [r0], #2 */
1515 0xe1c890b0, /* strh r9, [r8] */
1516 0xe1cab0b0, /* strh r11, [r10] */
1517 0xe1c830b0, /* strh r3, [r8] */
1518 0xe1c150b0, /* strh r5, [r1] */
1519 0xe1a00000, /* nop (mov r0,r0) */
1520 /* */
1521 /* <sp_16_busy>: */
1522 0xe1d160b0, /* ldrh r6, [r1] */
1523 0xe0257006, /* eor r7, r5, r6 */
1524 0xe2177080, /* ands r7, #0x80 */
1525 0x1afffffb, /* bne 8168 <sp_16_busy> */
1526 /* */
1527 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1528 0x03a05080, /* moveq r5, #128 ; 0x80 */
1529 0x0a000001, /* beq 81ac <sp_16_done> */
1530 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1531 0xeafffff0, /* b 8158 <sp_16_code> */
1532 /* */
1533 /* 000081ac <sp_16_done>: */
1534 0xeafffffe /* b 81ac <sp_16_done> */
1535 };
1536
1537 static const uint32_t word_8_code[] = {
1538 /* 000081b0 <sp_16_code_end>: */
1539 0xe4d05001, /* ldrb r5, [r0], #1 */
1540 0xe5c89000, /* strb r9, [r8] */
1541 0xe5cab000, /* strb r11, [r10] */
1542 0xe5c83000, /* strb r3, [r8] */
1543 0xe5c15000, /* strb r5, [r1] */
1544 0xe1a00000, /* nop (mov r0,r0) */
1545 /* */
1546 /* 000081c0 <sp_8_busy>: */
1547 0xe5d16000, /* ldrb r6, [r1] */
1548 0xe0257006, /* eor r7, r5, r6 */
1549 0xe0147007, /* ands r7, r4, r7 */
1550 0x0a000007, /* beq 81f0 <sp_8_cont> */
1551 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1552 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1553 0xe5d16000, /* ldrb r6, [r1] */
1554 0xe0257006, /* eor r7, r5, r6 */
1555 0xe0147007, /* ands r7, r4, r7 */
1556 0x0a000001, /* beq 81f0 <sp_8_cont> */
1557 0xe3a05000, /* mov r5, #0 ; 0x0 */
1558 0x1a000004, /* bne 8204 <sp_8_done> */
1559 /* */
1560 /* 000081f0 <sp_8_cont>: */
1561 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1562 0x03a05080, /* moveq r5, #128 ; 0x80 */
1563 0x0a000001, /* beq 8204 <sp_8_done> */
1564 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1565 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1566 /* */
1567 /* 00008204 <sp_8_done>: */
1568 0xeafffffe /* b 8204 <sp_8_done> */
1569 };
1570
1571 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1572 armv4_5_info.core_mode = ARM_MODE_SVC;
1573 armv4_5_info.core_state = ARM_STATE_ARM;
1574
1575 int target_code_size;
1576 const uint32_t *target_code_src;
1577
1578 switch (bank->bus_width)
1579 {
1580 case 1 :
1581 target_code_src = word_8_code;
1582 target_code_size = sizeof(word_8_code);
1583 break;
1584 case 2 :
1585 /* Check for DQ5 support */
1586 if( cfi_info->status_poll_mask & (1 << 5) )
1587 {
1588 target_code_src = word_16_code;
1589 target_code_size = sizeof(word_16_code);
1590 }
1591 else
1592 {
1593 /* No DQ5 support. Use DQ7 DATA# polling only. */
1594 target_code_src = word_16_code_dq7only;
1595 target_code_size = sizeof(word_16_code_dq7only);
1596 }
1597 break;
1598 case 4 :
1599 target_code_src = word_32_code;
1600 target_code_size = sizeof(word_32_code);
1601 break;
1602 default:
1603 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1604 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1605 }
1606
1607 /* flash write code */
1608 if (!cfi_info->write_algorithm)
1609 {
1610 uint8_t *target_code;
1611
1612 /* convert bus-width dependent algorithm code to correct endiannes */
1613 target_code = malloc(target_code_size);
1614 if (target_code == NULL)
1615 {
1616 LOG_ERROR("Out of memory");
1617 return ERROR_FAIL;
1618 }
1619 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1620
1621 /* allocate working area */
1622 retval = target_alloc_working_area(target, target_code_size,
1623 &cfi_info->write_algorithm);
1624 if (retval != ERROR_OK)
1625 {
1626 free(target_code);
1627 return retval;
1628 }
1629
1630 /* write algorithm code to working area */
1631 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1632 target_code_size, target_code)) != ERROR_OK)
1633 {
1634 free(target_code);
1635 return retval;
1636 }
1637
1638 free(target_code);
1639 }
1640 /* the following code still assumes target code is fixed 24*4 bytes */
1641
1642 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1643 {
1644 buffer_size /= 2;
1645 if (buffer_size <= 256)
1646 {
1647 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1648 if (cfi_info->write_algorithm)
1649 target_free_working_area(target, cfi_info->write_algorithm);
1650
1651 LOG_WARNING("not enough working area available, can't do block memory writes");
1652 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1653 }
1654 };
1655
1656 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1657 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1658 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1659 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1660 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1661 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1662 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1663 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1664 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1665 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1666
1667 while (count > 0)
1668 {
1669 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1670
1671 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1672 if (retval != ERROR_OK)
1673 {
1674 break;
1675 }
1676
1677 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1678 buf_set_u32(reg_params[1].value, 0, 32, address);
1679 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1680 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1681 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1682 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1683 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1684 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1685 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1686
1687 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1688 cfi_info->write_algorithm->address,
1689 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1690 10000, &armv4_5_info);
1691 if (retval != ERROR_OK)
1692 {
1693 break;
1694 }
1695
1696 status = buf_get_u32(reg_params[5].value, 0, 32);
1697 if (status != 0x80)
1698 {
1699 LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1700 retval = ERROR_FLASH_OPERATION_FAILED;
1701 break;
1702 }
1703
1704 buffer += thisrun_count;
1705 address += thisrun_count;
1706 count -= thisrun_count;
1707 }
1708
1709 target_free_all_working_areas(target);
1710
1711 destroy_reg_param(&reg_params[0]);
1712 destroy_reg_param(&reg_params[1]);
1713 destroy_reg_param(&reg_params[2]);
1714 destroy_reg_param(&reg_params[3]);
1715 destroy_reg_param(&reg_params[4]);
1716 destroy_reg_param(&reg_params[5]);
1717 destroy_reg_param(&reg_params[6]);
1718 destroy_reg_param(&reg_params[7]);
1719 destroy_reg_param(&reg_params[8]);
1720 destroy_reg_param(&reg_params[9]);
1721
1722 return retval;
1723 }
1724
1725 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1726 {
1727 int retval;
1728 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1729 struct target *target = bank->target;
1730
1731 cfi_intel_clear_status_register(bank);
1732 if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1733 {
1734 return retval;
1735 }
1736
1737 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1738 {
1739 return retval;
1740 }
1741
1742 uint8_t status;
1743 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max), &status);
1744 if (retval != 0x80)
1745 {
1746 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1747 {
1748 return retval;
1749 }
1750
1751 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1752 return ERROR_FLASH_OPERATION_FAILED;
1753 }
1754
1755 return ERROR_OK;
1756 }
1757
1758 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1759 {
1760 int retval;
1761 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1762 struct target *target = bank->target;
1763
1764 /* Calculate buffer size and boundary mask */
1765 /* buffersize is (buffer size per chip) * (number of chips) */
1766 /* bufferwsize is buffersize in words */
1767 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1768 uint32_t buffermask = buffersize-1;
1769 uint32_t bufferwsize = buffersize / bank->bus_width;
1770
1771 /* Check for valid range */
1772 if (address & buffermask)
1773 {
1774 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1775 bank->base, address, cfi_info->max_buf_write_size);
1776 return ERROR_FLASH_OPERATION_FAILED;
1777 }
1778
1779 /* Check for valid size */
1780 if (wordcount > bufferwsize)
1781 {
1782 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1783 return ERROR_FLASH_OPERATION_FAILED;
1784 }
1785
1786 /* Write to flash buffer */
1787 cfi_intel_clear_status_register(bank);
1788
1789 /* Initiate buffer operation _*/
1790 if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1791 {
1792 return retval;
1793 }
1794 uint8_t status;
1795 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1796 if (retval != ERROR_OK)
1797 return retval;
1798 if (status != 0x80)
1799 {
1800 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1801 {
1802 return retval;
1803 }
1804
1805 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1806 return ERROR_FLASH_OPERATION_FAILED;
1807 }
1808
1809 /* Write buffer wordcount-1 and data words */
1810 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1811 {
1812 return retval;
1813 }
1814
1815 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1816 {
1817 return retval;
1818 }
1819
1820 /* Commit write operation */
1821 if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1822 {
1823 return retval;
1824 }
1825
1826 retval = cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max), &status);
1827 if (retval != ERROR_OK)
1828 return retval;
1829
1830 if (status != 0x80)
1831 {
1832 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1833 {
1834 return retval;
1835 }
1836
1837 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1838 return ERROR_FLASH_OPERATION_FAILED;
1839 }
1840
1841 return ERROR_OK;
1842 }
1843
1844 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1845 {
1846 int retval;
1847 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1848 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1849 struct target *target = bank->target;
1850
1851 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1852 {
1853 return retval;
1854 }
1855
1856 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1857 {
1858 return retval;
1859 }
1860
1861 if ((retval = cfi_send_command(bank, 0xa0, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1862 {
1863 return retval;
1864 }
1865
1866 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1867 {
1868 return retval;
1869 }
1870
1871 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1872 {
1873 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1874 {
1875 return retval;
1876 }
1877
1878 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1879 return ERROR_FLASH_OPERATION_FAILED;
1880 }
1881
1882 return ERROR_OK;
1883 }
1884
1885 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1886 {
1887 int retval;
1888 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1889 struct target *target = bank->target;
1890 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1891
1892 /* Calculate buffer size and boundary mask */
1893 /* buffersize is (buffer size per chip) * (number of chips) */
1894 /* bufferwsize is buffersize in words */
1895 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1896 uint32_t buffermask = buffersize-1;
1897 uint32_t bufferwsize = buffersize / bank->bus_width;
1898
1899 /* Check for valid range */
1900 if (address & buffermask)
1901 {
1902 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1903 return ERROR_FLASH_OPERATION_FAILED;
1904 }
1905
1906 /* Check for valid size */
1907 if (wordcount > bufferwsize)
1908 {
1909 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1910 return ERROR_FLASH_OPERATION_FAILED;
1911 }
1912
1913 // Unlock
1914 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1915 {
1916 return retval;
1917 }
1918
1919 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1920 {
1921 return retval;
1922 }
1923
1924 // Buffer load command
1925 if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
1926 {
1927 return retval;
1928 }
1929
1930 /* Write buffer wordcount-1 and data words */
1931 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1932 {
1933 return retval;
1934 }
1935
1936 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1937 {
1938 return retval;
1939 }
1940
1941 /* Commit write operation */
1942 if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
1943 {
1944 return retval;
1945 }
1946
1947 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1948 {
1949 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1950 {
1951 return retval;
1952 }
1953
1954 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1955 return ERROR_FLASH_OPERATION_FAILED;
1956 }
1957
1958 return ERROR_OK;
1959 }
1960
1961 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1962 {
1963 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1964
1965 switch (cfi_info->pri_id)
1966 {
1967 case 1:
1968 case 3:
1969 return cfi_intel_write_word(bank, word, address);
1970 break;
1971 case 2:
1972 return cfi_spansion_write_word(bank, word, address);
1973 break;
1974 default:
1975 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1976 break;
1977 }
1978
1979 return ERROR_FLASH_OPERATION_FAILED;
1980 }
1981
1982 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1983 {
1984 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1985
1986 switch (cfi_info->pri_id)
1987 {
1988 case 1:
1989 case 3:
1990 return cfi_intel_write_words(bank, word, wordcount, address);
1991 break;
1992 case 2:
1993 return cfi_spansion_write_words(bank, word, wordcount, address);
1994 break;
1995 default:
1996 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1997 break;
1998 }
1999
2000 return ERROR_FLASH_OPERATION_FAILED;
2001 }
2002
2003 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2004 {
2005 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2006 struct target *target = bank->target;
2007 uint32_t address = bank->base + offset;
2008 uint32_t read_p;
2009 int align; /* number of unaligned bytes */
2010 uint8_t current_word[CFI_MAX_BUS_WIDTH];
2011 int i;
2012 int retval;
2013
2014 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2015 (int)count, (unsigned)offset);
2016
2017 if (bank->target->state != TARGET_HALTED)
2018 {
2019 LOG_ERROR("Target not halted");
2020 return ERROR_TARGET_NOT_HALTED;
2021 }
2022
2023 if (offset + count > bank->size)
2024 return ERROR_FLASH_DST_OUT_OF_BANK;
2025
2026 if (cfi_info->qry[0] != 'Q')
2027 return ERROR_FLASH_BANK_NOT_PROBED;
2028
2029 /* start at the first byte of the first word (bus_width size) */
2030 read_p = address & ~(bank->bus_width - 1);
2031 if ((align = address - read_p) != 0)
2032 {
2033 LOG_INFO("Fixup %d unaligned read head bytes", align);
2034
2035 /* read a complete word from flash */
2036 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2037 return retval;
2038
2039 /* take only bytes we need */
2040 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2041 *buffer++ = current_word[i];
2042
2043 read_p += bank->bus_width;
2044 }
2045
2046 align = count / bank->bus_width;
2047 if (align)
2048 {
2049 if ((retval = target_read_memory(target, read_p, bank->bus_width, align, buffer)) != ERROR_OK)
2050 return retval;
2051
2052 read_p += align * bank->bus_width;
2053 buffer += align * bank->bus_width;
2054 count -= align * bank->bus_width;
2055 }
2056
2057 if (count)
2058 {
2059 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2060
2061 /* read a complete word from flash */
2062 if ((retval = target_read_memory(target, read_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2063 return retval;
2064
2065 /* take only bytes we need */
2066 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2067 *buffer++ = current_word[i];
2068 }
2069
2070 return ERROR_OK;
2071 }
2072
2073 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2074 {
2075 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2076 struct target *target = bank->target;
2077 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2078 uint32_t write_p;
2079 int align; /* number of unaligned bytes */
2080 int blk_count; /* number of bus_width bytes for block copy */
2081 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
2082 int i;
2083 int retval;
2084
2085 if (bank->target->state != TARGET_HALTED)
2086 {
2087 LOG_ERROR("Target not halted");
2088 return ERROR_TARGET_NOT_HALTED;
2089 }
2090
2091 if (offset + count > bank->size)
2092 return ERROR_FLASH_DST_OUT_OF_BANK;
2093
2094 if (cfi_info->qry[0] != 'Q')
2095 return ERROR_FLASH_BANK_NOT_PROBED;
2096
2097 /* start at the first byte of the first word (bus_width size) */
2098 write_p = address & ~(bank->bus_width - 1);
2099 if ((align = address - write_p) != 0)
2100 {
2101 LOG_INFO("Fixup %d unaligned head bytes", align);
2102
2103 /* read a complete word from flash */
2104 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2105 return retval;
2106
2107 /* replace only bytes that must be written */
2108 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2109 current_word[i] = *buffer++;
2110
2111 retval = cfi_write_word(bank, current_word, write_p);
2112 if (retval != ERROR_OK)
2113 return retval;
2114 write_p += bank->bus_width;
2115 }
2116
2117 /* handle blocks of bus_size aligned bytes */
2118 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2119 switch (cfi_info->pri_id)
2120 {
2121 /* try block writes (fails without working area) */
2122 case 1:
2123 case 3:
2124 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2125 break;
2126 case 2:
2127 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2128 break;
2129 default:
2130 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2131 retval = ERROR_FLASH_OPERATION_FAILED;
2132 break;
2133 }
2134 if (retval == ERROR_OK)
2135 {
2136 /* Increment pointers and decrease count on succesful block write */
2137 buffer += blk_count;
2138 write_p += blk_count;
2139 count -= blk_count;
2140 }
2141 else
2142 {
2143 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2144 {
2145 /* Calculate buffer size and boundary mask */
2146 /* buffersize is (buffer size per chip) * (number of chips) */
2147 /* bufferwsize is buffersize in words */
2148 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2149 uint32_t buffermask = buffersize-1;
2150 uint32_t bufferwsize = buffersize / bank->bus_width;
2151
2152 /* fall back to memory writes */
2153 while (count >= (uint32_t)bank->bus_width)
2154 {
2155 int fallback;
2156 if ((write_p & 0xff) == 0)
2157 {
2158 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
2159 }
2160 fallback = 1;
2161 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2162 {
2163 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2164 if (retval == ERROR_OK)
2165 {
2166 buffer += buffersize;
2167 write_p += buffersize;
2168 count -= buffersize;
2169 fallback = 0;
2170 }
2171 }
2172 /* try the slow way? */
2173 if (fallback)
2174 {
2175 for (i = 0; i < bank->bus_width; i++)
2176 current_word[i] = *buffer++;
2177
2178 retval = cfi_write_word(bank, current_word, write_p);
2179 if (retval != ERROR_OK)
2180 return retval;
2181
2182 write_p += bank->bus_width;
2183 count -= bank->bus_width;
2184 }
2185 }
2186 }
2187 else
2188 return retval;
2189 }
2190
2191 /* return to read array mode, so we can read from flash again for padding */
2192 if ((retval = cfi_reset(bank)) != ERROR_OK)
2193 {
2194 return retval;
2195 }
2196
2197 /* handle unaligned tail bytes */
2198 if (count > 0)
2199 {
2200 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2201
2202 /* read a complete word from flash */
2203 if ((retval = target_read_memory(target, write_p, bank->bus_width, 1, current_word)) != ERROR_OK)
2204 return retval;
2205
2206 /* replace only bytes that must be written */
2207 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2208 current_word[i] = *buffer++;
2209
2210 retval = cfi_write_word(bank, current_word, write_p);
2211 if (retval != ERROR_OK)
2212 return retval;
2213 }
2214
2215 /* return to read array mode */
2216 return cfi_reset(bank);
2217 }
2218
2219 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
2220 {
2221 (void) param;
2222 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2223 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2224
2225 pri_ext->_reversed_geometry = 1;
2226 }
2227
2228 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2229 {
2230 int i;
2231 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2232 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2233 (void) param;
2234
2235 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2236 {
2237 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2238
2239 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2240 {
2241 int j = (cfi_info->num_erase_regions - 1) - i;
2242 uint32_t swap;
2243
2244 swap = cfi_info->erase_region_info[i];
2245 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2246 cfi_info->erase_region_info[j] = swap;
2247 }
2248 }
2249 }
2250
2251 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2252 {
2253 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2254 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2255 struct cfi_unlock_addresses *unlock_addresses = param;
2256
2257 pri_ext->_unlock1 = unlock_addresses->unlock1;
2258 pri_ext->_unlock2 = unlock_addresses->unlock2;
2259 }
2260
2261
2262 static int cfi_query_string(struct flash_bank *bank, int address)
2263 {
2264 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2265 int retval;
2266
2267 if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2268 {
2269 return retval;
2270 }
2271
2272 retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2273 if (retval != ERROR_OK)
2274 return retval;
2275 retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2276 if (retval != ERROR_OK)
2277 return retval;
2278 retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2279 if (retval != ERROR_OK)
2280 return retval;
2281
2282 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2283
2284 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2285 {
2286 if ((retval = cfi_reset(bank)) != ERROR_OK)
2287 {
2288 return retval;
2289 }
2290 LOG_ERROR("Could not probe bank: no QRY");
2291 return ERROR_FLASH_BANK_INVALID;
2292 }
2293
2294 return ERROR_OK;
2295 }
2296
2297 static int cfi_probe(struct flash_bank *bank)
2298 {
2299 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2300 struct target *target = bank->target;
2301 int num_sectors = 0;
2302 int i;
2303 int sector = 0;
2304 uint32_t unlock1 = 0x555;
2305 uint32_t unlock2 = 0x2aa;
2306 int retval;
2307 uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2308
2309 if (bank->target->state != TARGET_HALTED)
2310 {
2311 LOG_ERROR("Target not halted");
2312 return ERROR_TARGET_NOT_HALTED;
2313 }
2314
2315 cfi_info->probed = 0;
2316 if (bank->sectors)
2317 {
2318 free(bank->sectors);
2319 bank->sectors = NULL;
2320 }
2321 if(cfi_info->erase_region_info)
2322 {
2323 free(cfi_info->erase_region_info);
2324 cfi_info->erase_region_info = NULL;
2325 }
2326
2327 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2328 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2329 */
2330 if (cfi_info->jedec_probe)
2331 {
2332 unlock1 = 0x5555;
2333 unlock2 = 0x2aaa;
2334 }
2335
2336 /* switch to read identifier codes mode ("AUTOSELECT") */
2337 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2338 {
2339 return retval;
2340 }
2341 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2342 {
2343 return retval;
2344 }
2345 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2346 {
2347 return retval;
2348 }
2349
2350 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, value_buf0)) != ERROR_OK)
2351 {
2352 return retval;
2353 }
2354 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01), bank->bus_width, 1, value_buf1)) != ERROR_OK)
2355 {
2356 return retval;
2357 }
2358 switch (bank->chip_width) {
2359 case 1:
2360 cfi_info->manufacturer = *value_buf0;
2361 cfi_info->device_id = *value_buf1;
2362 break;
2363 case 2:
2364 cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2365 cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2366 break;
2367 case 4:
2368 cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2369 cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2370 break;
2371 default:
2372 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2373 return ERROR_FLASH_OPERATION_FAILED;
2374 }
2375
2376 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2377 /* switch back to read array mode */
2378 if ((retval = cfi_reset(bank)) != ERROR_OK)
2379 {
2380 return retval;
2381 }
2382
2383 /* check device/manufacturer ID for known non-CFI flashes. */
2384 cfi_fixup_non_cfi(bank);
2385
2386 /* query only if this is a CFI compatible flash,
2387 * otherwise the relevant info has already been filled in
2388 */
2389 if (cfi_info->not_cfi == 0)
2390 {
2391 /* enter CFI query mode
2392 * according to JEDEC Standard No. 68.01,
2393 * a single bus sequence with address = 0x55, data = 0x98 should put
2394 * the device into CFI query mode.
2395 *
2396 * SST flashes clearly violate this, and we will consider them incompatbile for now
2397 */
2398
2399 retval = cfi_query_string(bank, 0x55);
2400 if (retval != ERROR_OK)
2401 {
2402 /*
2403 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2404 * be harmless enough:
2405 *
2406 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2407 */
2408 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2409 retval = cfi_query_string(bank, 0x555);
2410 }
2411 if (retval != ERROR_OK)
2412 return retval;
2413
2414 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2415 if (retval != ERROR_OK)
2416 return retval;
2417 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2418 if (retval != ERROR_OK)
2419 return retval;
2420 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2421 if (retval != ERROR_OK)
2422 return retval;
2423 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2424 if (retval != ERROR_OK)
2425 return retval;
2426
2427 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2428
2429 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2430 if (retval != ERROR_OK)
2431 return retval;
2432 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2433 if (retval != ERROR_OK)
2434 return retval;
2435 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2436 if (retval != ERROR_OK)
2437 return retval;
2438 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2439 if (retval != ERROR_OK)
2440 return retval;
2441 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2442 if (retval != ERROR_OK)
2443 return retval;
2444 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2445 if (retval != ERROR_OK)
2446 return retval;
2447 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2448 if (retval != ERROR_OK)
2449 return retval;
2450 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2451 if (retval != ERROR_OK)
2452 return retval;
2453 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2454 if (retval != ERROR_OK)
2455 return retval;
2456 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2457 if (retval != ERROR_OK)
2458 return retval;
2459 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2460 if (retval != ERROR_OK)
2461 return retval;
2462 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2463 if (retval != ERROR_OK)
2464 return retval;
2465
2466 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2467 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2468 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2469 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2470 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2471 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2472 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2473 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2474 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2475 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2476 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2477
2478 uint8_t data;
2479 retval = cfi_query_u8(bank, 0, 0x27, &data);
2480 if (retval != ERROR_OK)
2481 return retval;
2482 cfi_info->dev_size = 1 << data;
2483
2484 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2485 if (retval != ERROR_OK)
2486 return retval;
2487 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2488 if (retval != ERROR_OK)
2489 return retval;
2490 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2491 if (retval != ERROR_OK)
2492 return retval;
2493
2494 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2495
2496 if (cfi_info->num_erase_regions)
2497 {
2498 cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2499 * cfi_info->num_erase_regions);
2500 for (i = 0; i < cfi_info->num_erase_regions; i++)
2501 {
2502 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2503 if (retval != ERROR_OK)
2504 return retval;
2505 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2506 i,
2507 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2508 (cfi_info->erase_region_info[i] >> 16) * 256);
2509 }
2510 }
2511 else
2512 {
2513 cfi_info->erase_region_info = NULL;
2514 }
2515
2516 /* We need to read the primary algorithm extended query table before calculating
2517 * the sector layout to be able to apply fixups
2518 */
2519 switch (cfi_info->pri_id)
2520 {
2521 /* Intel command set (standard and extended) */
2522 case 0x0001:
2523 case 0x0003:
2524 cfi_read_intel_pri_ext(bank);
2525 break;
2526 /* AMD/Spansion, Atmel, ... command set */
2527 case 0x0002:
2528 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2529 cfi_read_0002_pri_ext(bank);
2530 break;
2531 default:
2532 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2533 break;
2534 }
2535
2536 /* return to read array mode
2537 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2538 */
2539 if ((retval = cfi_reset(bank)) != ERROR_OK)
2540 {
2541 return retval;
2542 }
2543 } /* end CFI case */
2544
2545 /* apply fixups depending on the primary command set */
2546 switch (cfi_info->pri_id)
2547 {
2548 /* Intel command set (standard and extended) */
2549 case 0x0001:
2550 case 0x0003:
2551 cfi_fixup(bank, cfi_0001_fixups);
2552 break;
2553 /* AMD/Spansion, Atmel, ... command set */
2554 case 0x0002:
2555 cfi_fixup(bank, cfi_0002_fixups);
2556 break;
2557 default:
2558 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2559 break;
2560 }
2561
2562 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2563 {
2564 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2565 }
2566
2567 if (cfi_info->num_erase_regions == 0)
2568 {
2569 /* a device might have only one erase block, spanning the whole device */
2570 bank->num_sectors = 1;
2571 bank->sectors = malloc(sizeof(struct flash_sector));
2572
2573 bank->sectors[sector].offset = 0x0;
2574 bank->sectors[sector].size = bank->size;
2575 bank->sectors[sector].is_erased = -1;
2576 bank->sectors[sector].is_protected = -1;
2577 }
2578 else
2579 {
2580 uint32_t offset = 0;
2581
2582 for (i = 0; i < cfi_info->num_erase_regions; i++)
2583 {
2584 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2585 }
2586
2587 bank->num_sectors = num_sectors;
2588 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2589
2590 for (i = 0; i < cfi_info->num_erase_regions; i++)
2591 {
2592 uint32_t j;
2593 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2594 {
2595 bank->sectors[sector].offset = offset;
2596 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2597 offset += bank->sectors[sector].size;
2598 bank->sectors[sector].is_erased = -1;
2599 bank->sectors[sector].is_protected = -1;
2600 sector++;
2601 }
2602 }
2603 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2604 {
2605 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2606 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2607 }
2608 }
2609
2610 cfi_info->probed = 1;
2611
2612 return ERROR_OK;
2613 }
2614
2615 static int cfi_auto_probe(struct flash_bank *bank)
2616 {
2617 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2618 if (cfi_info->probed)
2619 return ERROR_OK;
2620 return cfi_probe(bank);
2621 }
2622
2623 static int cfi_intel_protect_check(struct flash_bank *bank)
2624 {
2625 int retval;
2626 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2627 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2628 int i;
2629
2630 /* check if block lock bits are supported on this device */
2631 if (!(pri_ext->blk_status_reg_mask & 0x1))
2632 return ERROR_FLASH_OPERATION_FAILED;
2633
2634 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2635 {
2636 return retval;
2637 }
2638
2639 for (i = 0; i < bank->num_sectors; i++)
2640 {
2641 uint8_t block_status;
2642 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2643 if (retval != ERROR_OK)
2644 return retval;
2645
2646 if (block_status & 1)
2647 bank->sectors[i].is_protected = 1;
2648 else
2649 bank->sectors[i].is_protected = 0;
2650 }
2651
2652 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2653 }
2654
2655 static int cfi_spansion_protect_check(struct flash_bank *bank)
2656 {
2657 int retval;
2658 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2659 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2660 int i;
2661
2662 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2663 {
2664 return retval;
2665 }
2666
2667 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2668 {
2669 return retval;
2670 }
2671
2672 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2673 {
2674 return retval;
2675 }
2676
2677 for (i = 0; i < bank->num_sectors; i++)
2678 {
2679 uint8_t block_status;
2680 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2681 if (retval != ERROR_OK)
2682 return retval;
2683
2684 if (block_status & 1)
2685 bank->sectors[i].is_protected = 1;
2686 else
2687 bank->sectors[i].is_protected = 0;
2688 }
2689
2690 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2691 }
2692
2693 static int cfi_protect_check(struct flash_bank *bank)
2694 {
2695 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2696
2697 if (bank->target->state != TARGET_HALTED)
2698 {
2699 LOG_ERROR("Target not halted");
2700 return ERROR_TARGET_NOT_HALTED;
2701 }
2702
2703 if (cfi_info->qry[0] != 'Q')
2704 return ERROR_FLASH_BANK_NOT_PROBED;
2705
2706 switch (cfi_info->pri_id)
2707 {
2708 case 1:
2709 case 3:
2710 return cfi_intel_protect_check(bank);
2711 break;
2712 case 2:
2713 return cfi_spansion_protect_check(bank);
2714 break;
2715 default:
2716 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2717 break;
2718 }
2719
2720 return ERROR_OK;
2721 }
2722
2723 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2724 {
2725 int printed;
2726 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2727
2728 if (cfi_info->qry[0] == 0xff)
2729 {
2730 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2731 return ERROR_OK;
2732 }
2733
2734 if (cfi_info->not_cfi == 0)
2735 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2736 else
2737 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2738 buf += printed;
2739 buf_size -= printed;
2740
2741 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2742 cfi_info->manufacturer, cfi_info->device_id);
2743 buf += printed;
2744 buf_size -= printed;
2745
2746 if (cfi_info->not_cfi == 0)
2747 {
2748 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2749 buf += printed;
2750 buf_size -= printed;
2751
2752 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2753 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2754 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2755 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2756 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2757 buf += printed;
2758 buf_size -= printed;
2759
2760 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2761 1 << cfi_info->word_write_timeout_typ,
2762 1 << cfi_info->buf_write_timeout_typ,
2763 1 << cfi_info->block_erase_timeout_typ,
2764 1 << cfi_info->chip_erase_timeout_typ);
2765 buf += printed;
2766 buf_size -= printed;
2767
2768 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2769 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2770 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2771 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2772 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2773 buf += printed;
2774 buf_size -= printed;
2775
2776 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2777 cfi_info->dev_size,
2778 cfi_info->interface_desc,
2779 1 << cfi_info->max_buf_write_size);
2780 buf += printed;
2781 buf_size -= printed;
2782
2783 switch (cfi_info->pri_id)
2784 {
2785 case 1:
2786 case 3:
2787 cfi_intel_info(bank, buf, buf_size);
2788 break;
2789 case 2:
2790 cfi_spansion_info(bank, buf, buf_size);
2791 break;
2792 default:
2793 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2794 break;
2795 }
2796 }
2797
2798 return ERROR_OK;
2799 }
2800
2801 struct flash_driver cfi_flash = {
2802 .name = "cfi",
2803 .flash_bank_command = cfi_flash_bank_command,
2804 .erase = cfi_erase,
2805 .protect = cfi_protect,
2806 .write = cfi_write,
2807 .read = cfi_read,
2808 .probe = cfi_probe,
2809 .auto_probe = cfi_auto_probe,
2810 /* FIXME: access flash at bus_width size */
2811 .erase_check = default_flash_blank_check,
2812 .protect_check = cfi_protect_check,
2813 .info = get_cfi_info,
2814 };
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