src/target/arm_disassembler.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  19  ***************************************************************************/
  20
  21 #ifndef ARM_DISASSEMBLER_H
  22 #define ARM_DISASSEMBLER_H
  23
  24 enum arm_instruction_type {
  25         ARM_UNKNOWN_INSTUCTION,
  26
  27         /* Branch instructions */
  28         ARM_B,
  29         ARM_BL,
  30         ARM_BX,
  31         ARM_BLX,
  32
  33         /* Data processing instructions */
  34         ARM_AND,
  35         ARM_EOR,
  36         ARM_SUB,
  37         ARM_RSB,
  38         ARM_ADD,
  39         ARM_ADC,
  40         ARM_SBC,
  41         ARM_RSC,
  42         ARM_TST,
  43         ARM_TEQ,
  44         ARM_CMP,
  45         ARM_CMN,
  46         ARM_ORR,
  47         ARM_MOV,
  48         ARM_BIC,
  49         ARM_MVN,
  50
  51         /* Load/store instructions */
  52         ARM_LDR,
  53         ARM_LDRB,
  54         ARM_LDRT,
  55         ARM_LDRBT,
  56
  57         ARM_LDRH,
  58         ARM_LDRSB,
  59         ARM_LDRSH,
  60
  61         ARM_LDM,
  62
  63         ARM_STR,
  64         ARM_STRB,
  65         ARM_STRT,
  66         ARM_STRBT,
  67
  68         ARM_STRH,
  69
  70         ARM_STM,
  71
  72         /* Status register access instructions */
  73         ARM_MRS,
  74         ARM_MSR,
  75
  76         /* Multiply instructions */
  77         ARM_MUL,
  78         ARM_MLA,
  79         ARM_SMULL,
  80         ARM_SMLAL,
  81         ARM_UMULL,
  82         ARM_UMLAL,
  83
  84         /* Miscellaneous instructions */
  85         ARM_CLZ,
  86
  87         /* Exception return instructions */
  88         ARM_ERET,
  89
  90         /* Exception generating instructions */
  91         ARM_BKPT,
  92         ARM_SWI,
  93         ARM_HVC,
  94         ARM_SMC,
  95
  96         /* Coprocessor instructions */
  97         ARM_CDP,
  98         ARM_LDC,
  99         ARM_STC,
 100         ARM_MCR,
 101         ARM_MRC,
 102
 103         /* Semaphore instructions */
 104         ARM_SWP,
 105         ARM_SWPB,
 106
 107         /* Enhanced DSP extensions */
 108         ARM_MCRR,
 109         ARM_MRRC,
 110         ARM_PLD,
 111         ARM_QADD,
 112         ARM_QDADD,
 113         ARM_QSUB,
 114         ARM_QDSUB,
 115         ARM_SMLAxy,
 116         ARM_SMLALxy,
 117         ARM_SMLAWy,
 118         ARM_SMULxy,
 119         ARM_SMULWy,
 120         ARM_LDRD,
 121         ARM_STRD,
 122
 123         ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
 124 };
 125
 126 struct arm_b_bl_bx_blx_instr {
 127         int reg_operand;
 128         uint32_t target_address;
 129 };
 130
 131 union arm_shifter_operand {
 132         struct {
 133                 uint32_t immediate;
 134         } immediate;
 135         struct {
 136                 uint8_t Rm;
 137                 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 138                 uint8_t shift_imm;
 139         } immediate_shift;
 140         struct {
 141                 uint8_t Rm;
 142                 uint8_t shift;
 143                 uint8_t Rs;
 144         } register_shift;
 145 };
 146
 147 struct arm_data_proc_instr {
 148         int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
 149         uint8_t S;
 150         uint8_t Rn;
 151         uint8_t Rd;
 152         union arm_shifter_operand shifter_operand;
 153 };
 154
 155 struct arm_load_store_instr {
 156         uint8_t Rd;
 157         uint8_t Rn;
 158         uint8_t U;
 159         int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
 160         int offset_mode; /* 0: immediate, 1: (scaled) register */
 161         union {
 162                 uint32_t offset;
 163                 struct {
 164                         uint8_t Rm;
 165                         uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
 166                         uint8_t shift_imm;
 167                 } reg;
 168         } offset;
 169 };
 170
 171 struct arm_load_store_multiple_instr {
 172         uint8_t Rn;
 173         uint32_t register_list;
 174         uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
 175         uint8_t S;
 176         uint8_t W;
 177 };
 178
 179 struct arm_instruction {
 180         enum arm_instruction_type type;
 181         char text[128];
 182         uint32_t opcode;
 183
 184         /* return value ... Thumb-2 sizes vary */
 185         unsigned instruction_size;
 186
 187         union {
 188                 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
 189                 struct arm_data_proc_instr data_proc;
 190                 struct arm_load_store_instr load_store;
 191                 struct arm_load_store_multiple_instr load_store_multiple;
 192         } info;
 193
 194 };
 195
 196 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
 197                 struct arm_instruction *instruction);
 198 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
 199                 struct arm_instruction *instruction);
 200 int thumb2_opcode(struct target *target, uint32_t address,
 201                 struct arm_instruction *instruction);
 202 int arm_access_size(struct arm_instruction *instruction);
 203
 204 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 205
 206 #endif /* ARM_DISASSEMBLER_H */