1 # Intel (Altera) Arria10 FPGA SoC
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 # ARM CoreSight Debug Access Port (dap HPS)
10 if { [info exists DAP_TAPID] } {
11 set _DAP_TAPID $DAP_TAPID
13 set _DAP_TAPID 0x4ba00477
15 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
17 # Subsidiary TAP: fpga (tap)
18 # See Intel Arria 10 Handbook
19 # https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
20 # Intel Arria 10 GX 160 0x02ee20dd
21 # Intel Arria 10 GX 220 0x02e220dd
22 # Intel Arria 10 GX 270 0x02ee30dd
23 # Intel Arria 10 GX 320 0x02e230dd
24 # Intel Arria 10 GX 480 0x02e240dd
25 # Intel Arria 10 GX 570 0x02ee50dd
26 # Intel Arria 10 GX 660 0x02e250dd
27 # Intel Arria 10 GX 900 0x02ee60dd
28 # Intel Arria 10 GX 1150 0x02e660dd
29 # Intel Arria 10 GT 900 0x02e260dd
30 # Intel Arria 10 GT 1150 0x02e060dd
31 # Intel Arria 10 SX 160 0x02e620dd
32 # Intel Arria 10 SX 220 0x02e020dd
33 # Intel Arria 10 SX 270 0x02e630dd
34 # Intel Arria 10 SX 320 0x02e030dd
35 # Intel Arria 10 SX 480 0x02e040dd
36 # Intel Arria 10 SX 570 0x02e650dd
37 # Intel Arria 10 SX 660 0x02e050dd
38 jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
39 -expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
40 -expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
41 -expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
42 -expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
43 -expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
44 -expected-id 0x02e050dd
46 set _TARGETNAME $_CHIPNAME.cpu
51 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
53 target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
54 target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
56 target smp $_TARGETNAME.0 $_TARGETNAME.1