3 <title>Test results for version
1.62</title>
17 <td>Initial state
</td>
19 <td>Expected output
</td>
20 <td>Actual output
</td>
24 <td><a name=
"CON001"/>CON001
</td>
27 <td>Telnet connection
</td>
28 <td>Power on, jtag target attached
</td>
29 <td>On console, type
<br><code>telnet ip port
</code></td>
30 <td><code>Open On-Chip Debugger
<br>></code></td>
31 <td><code>> telnet
10.0.0.142<br>
32 Trying
10.0.0.142...
<br>
33 Connected to
10.0.0.142.
<br>
34 Escape character is '^]'.
<br>
35 Open On-Chip Debugger
<br>
41 <td><a name=
"CON002"/>CON002
</td>
44 <td>GDB server connection
</td>
45 <td>Power on, jtag target attached
</td>
46 <td>On GDB console, type
<br><code>target remote ip:port
</code></td>
47 <td><code>Remote debugging using
10.0.0.73:
3333</code></td>
49 (gdb) tar remo
10.0.0.142:
3333<br>
50 Remote debugging using
10.0.0.142:
3333<br>
51 0x00016434 in ?? ()
<br>
65 <td>Initial state
</td>
67 <td>Expected output
</td>
68 <td>Actual output
</td>
72 <td><a name=
"RES001"/>RES001
</td>
75 <td>Reset halt on a blank target
</td>
76 <td>Erase all the content of the flash
</td>
77 <td>Connect via the telnet interface and type
<br><code>reset halt
</code></td>
78 <td>Reset should return without error and the output should contain
<br><code>target state: halted
</code></td>
82 0x00000000:
75755000 8a930104
65696f65
939a3e98
214751f1 fa0edb9b
6664686d
931a989e
<br>
83 0x00000020:
676c65e4
9a0a0982
25653445 da02ba90 c4ed3165
9b9a8a9a
65676365 01981292<br>
84 0x00000040:
212e0982
82ba3f8b
34674765 96ba1a9a
6175e7e5
9b9ab91a
0789644d
120a9a18
<br>
85 0x00000060:
65446167 80d20982
6d6d6565
187090ca
65277d65
9a9a0b81
6960416c
9ffe88b8
<br>
87 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
89 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
96 <td><a name=
"RES002"/>RES002
</td>
99 <td>Reset init on a blank target
</td>
100 <td>Erase all the content of the flash
</td>
101 <td>Connect via the telnet interface and type
<br><code>reset init
</code></td>
102 <td>Reset should return without error and the output should contain
<br><code>executing reset script 'name_of_the_script'
</code></td>
106 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
108 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
109 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
110 target state: halted
<br>
111 target halted in ARM state due to debug-request, current mode: Undefined instruction
<br>
112 cpsr:
0xf00000db pc:
0x00000004<br>
113 jtag_speed
10 =
> JTAG clk=
6.400000<br>
120 <td><a name=
"RES003"/>RES003
</td>
123 <td>Reset after a power cycle of the target
</td>
124 <td>Reset the target then power cycle the target
</td>
125 <td>Connect via the telnet interface and type
<br><code>reset halt
</code> after the power was detected
</td>
126 <td>Reset should return without error and the output should contain
<br><code>target state: halted
</code></td>
129 nsed power dropout.
<br>
130 nsed power dropout.
<br>
131 nsed nSRST deasserted.
<br>
132 invalid mode value encountered
0<br>
133 cpsr contains invalid mode value - communication failure
<br>
134 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
136 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
137 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
138 target state: halted
<br>
139 target halted in ARM state due to debug-request, current mode: Supervisor
<br>
140 cpsr:
0x100000d3 pc:
0x0000001c<br>
141 jtag_speed
10 =
> JTAG clk=
6.400000<br>
143 nsed power restore.
<br>
144 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
146 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
147 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
148 target state: halted
<br>
149 target halted in ARM state due to debug-request, current mode: Supervisor
<br>
150 cpsr:
0x500000d3 pc:
0x00000000<br>
151 jtag_speed
10 =
> JTAG clk=
6.400000<br>
154 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
156 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
157 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
158 target state: halted
<br>
159 target halted in ARM state due to debug-request, current mode: Supervisor
<br>
160 cpsr:
0x500000d3 pc:
0x00000000<br>
161 jtag_speed
10 =
> JTAG clk=
6.400000<br>
169 <td><a name=
"RES004"/>RES004
</td>
172 <td>Reset halt on a blank target where reset halt is supported
</td>
173 <td>Erase all the content of the flash
</td>
174 <td>Connect via the telnet interface and type
<br><code>reset halt
</code></td>
175 <td>Reset should return without error and the output should contain
<br><code>target state: halted
</code></td>
179 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
181 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
182 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
183 target state: halted
<br>
184 target halted in ARM state due to debug-request, current mode: Supervisor
<br>
185 cpsr:
0x200000d3 pc:
0xfe50cba4<br>
192 <td><a name=
"RES005"/>RES005
</td>
195 <td>Reset halt on a blank target using return clock
</td>
196 <td>Erase all the content of the flash, set the configuration script to use RCLK
</td>
197 <td>Connect via the telnet interface and type
<br><code>reset halt
</code></td>
198 <td>Reset should return without error and the output should contain
<br><code>target state: halted
</code></td>
208 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
210 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
211 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
212 target state: halted
<br>
213 target halted in ARM state due to debug-request, current mode: Supervisor
<br>
214 cpsr:
0x200000d3 pc:
0xfe50cb50<br>
217 <td><font color=red
><b>FAIL
</b></font></td>
228 <td>Initial state
</td>
230 <td>Expected output
</td>
231 <td>Actual output
</td>
235 <td><a name=
"SPD001"/>SPD001
</td>
238 <td>16MHz on normal operation
</td>
239 <td>Reset init the target according to RES002
</td>
240 <td>Change speed and exercise a memory access over the JTAG, for example
<br><code>mdw
0x0 32</code></td>
241 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed
</td>
245 jtag_speed
4 =
> JTAG clk=
16.000000<br>
248 0x00000000:
75755000 8a930104
65696f65
939a3e98
214751f1 fa0edb9b
6664686d
931a989e
<br>
249 0x00000020:
676c65e4
9a0a0982
25653445 da02ba90 c4ed3165
9b9a8a9a
65676365 01981292<br>
250 0x00000040:
212e0982
82ba3f8b
34674765 96ba1a9a
6175e7e5
9b9ab91a
0789644d
120a9a18
<br>
251 0x00000060:
65446167 80d20982
6d6d6565
187090ca
65277d65
9a9a0b81
6960416c
9ffe88b8
<br>
258 <td><a name=
"SPD002"/>SPD002
</td>
261 <td>8MHz on normal operation
</td>
262 <td>Reset init the target according to RES002
</td>
263 <td>Change speed and exercise a memory access over the JTAG, for example
<br><code>mdw
0x0 32</code></td>
264 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed
</td>
268 jtag_speed
8 =
> JTAG clk=
8.000000<br>
271 0x00000000:
75755000 8a930104
65696f65
939a3e98
214751f1 fa0edb9b
6664686d
931a989e
<br>
272 0x00000020:
676c65e4
9a0a0982
25653445 da02ba90 c4ed3165
9b9a8a9a
65676365 01981292<br>
273 0x00000040:
212e0982
82ba3f8b
34674765 96ba1a9a
6175e7e5
9b9ab91a
0789644d
120a9a18
<br>
274 0x00000060:
65446167 80d20982
6d6d6565
187090ca
65277d65
9a9a0b81
6960416c
9ffe88b8
<br>
281 <td><a name=
"SPD003"/>SPD003
</td>
284 <td>4MHz on normal operation
</td>
285 <td>Reset init the target according to RES002
</td>
286 <td>Change speed and exercise a memory access over the JTAG, for example
<br><code>mdw
0x0 32</code></td>
287 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed
</td>
291 jtag_speed
16 =
> JTAG clk=
4.000000<br>
294 0x00000000:
75755000 8a930104
65696f65
939a3e98
214751f1 fa0edb9b
6664686d
931a989e
<br>
295 0x00000020:
676c65e4
9a0a0982
25653445 da02ba90 c4ed3165
9b9a8a9a
65676365 01981292<br>
296 0x00000040:
212e0982
82ba3f8b
34674765 96ba1a9a
6175e7e5
9b9ab91a
0789644d
120a9a18
<br>
297 0x00000060:
65446167 80d20982
6d6d6565
187090ca
65277d65
9a9a0b81
6960416c
9ffe88b8
<br>
304 <td><a name=
"SPD004"/>SPD004
</td>
307 <td>2MHz on normal operation
</td>
308 <td>Reset init the target according to RES002
</td>
309 <td>Change speed and exercise a memory access over the JTAG, for example
<br><code>mdw
0x0 32</code></td>
310 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed
</td>
313 > > jtag_khz
2000<br>
314 jtag_speed
32 =
> JTAG clk=
2.000000<br>
317 0x00000000:
75755000 8a930104
65696f65
939a3e98
214751f1 fa0edb9b
6664686d
931a989e
<br>
318 0x00000020:
676c65e4
9a0a0982
25653445 da02ba90 c4ed3165
9b9a8a9a
65676365 01981292<br>
319 0x00000040:
212e0982
82ba3f8b
34674765 96ba1a9a
6175e7e5
9b9ab91a
0789644d
120a9a18
<br>
320 0x00000060:
65446167 80d20982
6d6d6565
187090ca
65277d65
9a9a0b81
6960416c
9ffe88b8
<br>
327 <td><a name=
"SPD005"/>SPD005
</td>
330 <td>RCLK on normal operation
</td>
331 <td>Reset init the target according to RES002
</td>
332 <td>Change speed and exercise a memory access over the JTAG, for example
<br><code>mdw
0x0 32</code></td>
333 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed
</td>
343 <td><font color=red
><b>FAIL
</b></font></td>
354 <td>Initial state
</td>
356 <td>Expected output
</td>
357 <td>Actual output
</td>
361 <td><a name=
"DBG001"/>DBG001
</td>
364 <td>Load is working
</td>
365 <td>Reset init is working, RAM is accesible, GDB server is started
</td>
366 <td>On the console of the OS:
<br>
367 <code>arm-elf-gdb test_ram.elf
</code><br>
368 <code>(gdb) target remote ip:port
</code><br>
369 <code>(gdb) load
</load>
371 <td>Load should return without error, typical output looks like:
<br>
373 Loading section .text, size
0x14c lma
0x0<br>
374 Start address
0x40, load size
332<br>
375 Transfer rate:
180 bytes/sec,
332 bytes/write.
<br>
380 Loading section .text, size
0x1cc lma
0x20000000<br>
381 Loading section .vectors, size
0x40 lma
0x200001cc<br>
382 Loading section .rodata, size
0x4 lma
0x2000020c<br>
383 Start address
0x20000000, load size
528<br>
384 Transfer rate:
64 KB/sec,
176 bytes/write.
<br>
391 <td><a name=
"DBG002"/>DBG002
</td>
394 <td>Software breakpoint
</td>
395 <td>Load the test_ram.elf application, use instructions from GDB001
</td>
396 <td>In the GDB console:
<br>
398 (gdb) monitor gdb_breakpoint_override soft
<br>
399 force soft breakpoints
<br>
401 Breakpoint
1 at
0xec: file src/main.c, line
71.
<br>
406 <td>The software breakpoint should be reached, a typical output looks like:
<br>
408 target state: halted
<br>
409 target halted in ARM state due to breakpoint, current mode: Supervisor
<br>
410 cpsr:
0x000000d3 pc:
0x000000ec<br>
412 Breakpoint
1, main () at src/main.c:
71<br>
418 (gdb) monitor gdb_breakpoint_override soft
<br>
419 force soft breakpoints
<br>
420 Current language: auto
<br>
421 The current source language is
"auto; currently asm".
<br>
423 Breakpoint
1 at
0x20000170: file src/main.c, line
69.
<br>
427 Breakpoint
1, main () at src/main.c:
69<br>
429 Current language: auto
<br>
430 The current source language is
"auto; currently c".
<br>
437 <td><a name=
"DBG003"/>DBG003
</td>
440 <td>Single step in a RAM application
</td>
441 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002
</td>
442 <td>In GDB, type
<br><code>(gdb) step
</code></td>
443 <td>The next instruction should be reached, typical output:
<br>
446 target state: halted
<br>
447 target halted in ARM state due to single step, current mode: Abort
<br>
448 cpsr:
0x20000097 pc:
0x000000f0<br>
449 target state: halted
<br>
450 target halted in ARM state due to single step, current mode: Abort
<br>
451 cpsr:
0x20000097 pc:
0x000000f4<br>
465 <td><a name=
"DBG004"/>DBG004
</td>
468 <td>Software break points are working after a reset
</td>
469 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002
</td>
470 <td>In GDB, type
<br><code>
471 (gdb) monitor reset init
<br>
475 <td>The breakpoint should be reached, typical output:
<br>
477 target state: halted
<br>
478 target halted in ARM state due to breakpoint, current mode: Supervisor
<br>
479 cpsr:
0x000000d3 pc:
0x000000ec<br>
481 Breakpoint
1, main () at src/main.c:
71<br>
486 ((gdb) monitor reset init
<br>
487 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
489 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
490 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
491 target state: halted
<br>
492 target halted in ARM state due to debug-request, current mode: Supervisor
<br>
493 cpsr:
0x60000013 pc:
0x200001bc<br>
494 jtag_speed
10 =
> JTAG clk=
6.400000<br>
497 Loading section .text, size
0x1cc lma
0x20000000<br>
498 Loading section .vectors, size
0x40 lma
0x200001cc<br>
499 Loading section .rodata, size
0x4 lma
0x2000020c<br>
500 Start address
0x20000000, load size
528<br>
501 Transfer rate:
64 KB/sec,
176 bytes/write.
<br>
505 Breakpoint
1, main () at src/main.c:
69<br>
512 <td><a name=
"DBG005"/>DBG005
</td>
515 <td>Hardware breakpoint
</td>
516 <td>Flash the test_rom.elf application. Make this test after FLA004 has passed
</td>
517 <td>Be sure that
<code>gdb_memory_map
</code> and
<code>gdb_flash_program
</code> are enabled. In GDB, type
<br>
519 (gdb) monitor reset init
<br>
521 Loading section .text, size
0x194 lma
0x100000<br>
522 Start address
0x100040, load size
404<br>
523 Transfer rate:
179 bytes/sec,
404 bytes/write.
<br>
524 (gdb) monitor gdb_breakpoint_override hard
<br>
525 force hard breakpoints
<br>
527 Breakpoint
1 at
0x100134: file src/main.c, line
69.
<br>
531 <td>The breakpoint should be reached, typical output:
<br>
535 Breakpoint
1, main () at src/main.c:
69<br>
541 (gdb) monitor gdb_breakpoint_override hard
<br>
542 force hard breakpoints
<br>
544 Breakpoint
1 at
0x40000170: file src/main.c, line
69.
<br>
547 Note: automatically using hardware breakpoints for read-only addresses.
<br>
549 Breakpoint
1, main () at src/main.c:
69<br>
551 Current language: auto
<br>
552 The current source language is
"auto; currently c".
<br>
559 <td><a name=
"DBG006"/>DBG006
</td>
562 <td>Hardware breakpoint is set after a reset
</td>
563 <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005
</td>
564 <td>In GDB, type
<br>
566 (gdb) monitor reset
<br>
567 (gdb) monitor reg pc
0x100000<br>
568 pc (/
32):
0x00100000<br>
571 where the value inserted in PC is the start address of the application
573 <td>The breakpoint should be reached, typical output:
<br>
577 Breakpoint
1, main () at src/main.c:
69<br>
583 (gdb) monitor reset init
<br>
584 jtag_speed
6400 =
> JTAG clk=
0.010000<br>
586 JTAG tap: str710.cpu tap/device found:
0x3f0f0f0f (mfg:
0x787, part:
0xf0f0, ver:
0x3)
<br>
587 srst pulls trst - can not reset into halted mode. Issuing halt after reset.
<br>
588 target state: halted
<br>
589 target halted in ARM state due to debug-request, current mode: Undefined instruction
<br>
590 cpsr:
0x400000db pc:
0x010aea80<br>
591 jtag_speed
10 =
> JTAG clk=
6.400000<br>
593 (gdb) monitor reg pc
0x40000000<br>
594 pc (/
32):
0x40000000<br>
598 Breakpoint
1, main () at src/main.c:
69<br>
600 Current language: auto
<br>
601 The current source language is
"auto; currently c".
<br>
608 <td><a name=
"DBG007"/>DBG007
</td>
611 <td>Single step in ROM
</td>
612 <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed
</td>
613 <td>Be sure that
<code>gdb_memory_map
</code> and
<code>gdb_flash_program
</code> are enabled. In GDB, type
<br>
615 (gdb) monitor reset
<br>
617 Loading section .text, size
0x194 lma
0x100000<br>
618 Start address
0x100040, load size
404<br>
619 Transfer rate:
179 bytes/sec,
404 bytes/write.
<br>
620 (gdb) monitor arm7_9 force_hw_bkpts enable
<br>
621 force hardware breakpoints enabled
<br>
623 Breakpoint
1 at
0x100134: file src/main.c, line
69.
<br>
627 Breakpoint
1, main () at src/main.c:
69<br>
632 <td>The breakpoint should be reached, typical output:
<br>
634 target state: halted
<br>
635 target halted in ARM state due to single step, current mode: Supervisor
<br>
636 cpsr:
0x60000013 pc:
0x0010013c<br>
641 Breakpoint
2, main () at src/main.c:
69<br>
643 Current language: auto
<br>
644 The current source language is
"auto; currently c".
<br>
654 Note: these tests are not designed to test/debug the target, but to test functionalities!
661 <td>Initial state
</td>
663 <td>Expected output
</td>
664 <td>Actual output
</td>
668 <td><a name=
"RAM001"/>RAM001
</td>
671 <td>32 bit Write/read RAM
</td>
672 <td>Reset init is working
</td>
673 <td>On the telnet interface
<br>
674 <code> > mww ram_address
0xdeadbeef 16<br>
678 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of
16 locations
32bit long containing
0xdeadbeef.
<br>
680 > mww
0x0 0xdeadbeef 16<br>
682 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
683 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
684 0x00000040: e1a00000 e59fa51c e59f051c e04aa000
00080017 00009388 00009388 00009388<br>
685 0x00000060:
00009388 0002c2c0
0002c2c0
000094f8
000094f4
00009388 00009388 00009388<br>
689 > mww
0x20000000 0xdeadbeef 16<br>
690 > mdw
0x20000000 32<br>
691 0x20000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
692 0x20000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
693 0x20000040: e3a0020a e3a01073 e5801018 e5901008 e3110002
0afffffc e3a0020a e59f10d0
<br>
694 0x20000060: e5801008 e321f0db e59fd0c8 e321f0d7 e59fd0c4 e321f0d1 e59fd0c0 e321f0d2
<br>
700 <td><a name=
"RAM002"/>RAM002
</td>
703 <td>16 bit Write/read RAM
</td>
704 <td>Reset init is working
</td>
705 <td>On the telnet interface
<br>
706 <code> > mwh ram_address
0xbeef 16<br>
710 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of
16 locations
16bit long containing
0xbeef.
<br>
712 > mwh
0x0 0xbeef 16<br>
714 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
<br>
715 0x00000020:
00e0
0000 021c
0000 0240 0000 026c
0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
720 > mwh
0x20000000 0xbeef 16<br>
721 > mdh
0x20000000 32<br>
722 0x20000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef
<br>
723 0x20000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead
<br>
729 <td><a name=
"RAM003"/>RAM003
</td>
732 <td>8 bit Write/read RAM
</td>
733 <td>Reset init is working
</td>
734 <td>On the telnet interface
<br>
735 <code> > mwb ram_address
0xab 16<br>
739 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of
16 locations
8bit long containing
0xab.
<br>
741 > mwb ram_address
0xab 16<br>
742 > mdb ram_address
32<br>
743 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
748 > mwb
0x20000000 0xab 16<br>
749 > mdb
0x20000000 32<br>
750 0x20000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be
<br>
759 <H2>Flash access
</H2>
766 <td>Initial state
</td>
768 <td>Expected output
</td>
769 <td>Actual output
</td>
773 <td><a name=
"FLA001"/>FLA001
</td>
777 <td>Reset init is working
</td>
778 <td>On the telnet interface:
<br>
779 <code> > flash probe
0</code>
781 <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
<br>
782 <code>flash 'ecosflash' found at
0x01000000</code>
787 flash 'str7x' found at
0x40000000<br>
794 <td><a name=
"FLA002"/>FLA002
</td>
798 <td>Reset init is working, flash is probed
</td>
799 <td>On the telnet interface
<br>
800 <code> > flash fillw
0x1000000 0xdeadbeef 16
803 <td>The commands should execute without error. The output looks like:
<br>
805 wrote
64 bytes to
0x01000000 in
11.610000s (
0.091516 kb/s)
807 To verify the contents of the flash:
<br>
809 > mdw
0x1000000 32<br>
810 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
811 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
812 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
813 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
817 > flash fillw
0x40000000 0xdeadbeef 16<br>
818 wrote
64 bytes to
0x40000000 in
0.000000s (inf kb/s)
<br>
819 > mdw
0x40000000 32<br>
820 0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
821 0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
<br>
822 0x40000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
823 0x40000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
829 <td><a name=
"FLA003"/>FLA003
</td>
833 <td>Reset init is working, flash is probed
</td>
834 <td>On the telnet interface
<br>
835 <code> > flash erase_address
0x1000000 0x2000
838 <td>The commands should execute without error.
<br>
840 erased address
0x01000000 length
8192 in
4.970000s
842 To check that the flash has been erased, read at different addresses. The result should always be
0xff.
844 > mdw
0x1000000 32<br>
845 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
846 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
847 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
848 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
852 > flash erase_address
0x40000000 0x2000<br>
853 erased address
0x40000000 (length
8192) in
0.270000s (
29.630 kb/s)
<br>
854 > mdw
0x40000000 32 <br>
855 0x40000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
856 0x40000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
857 0x40000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
858 0x40000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
<br>
864 <td><a name=
"FLA004"/>FLA004
</td>
867 <td>Loading to flash from GDB
</td>
868 <td>Reset init is working, flash is probed, connectivity to GDB server is working
</td>
869 <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
<br>
871 (gdb) target remote ip:port
<br>
872 (gdb) monitor reset
<br>
874 Loading section .text, size
0x194 lma
0x100000<br>
875 Start address
0x100040, load size
404<br>
876 Transfer rate:
179 bytes/sec,
404 bytes/write.
877 (gdb) monitor verify_image path_to_elf_file
880 <td>The output should look like:
<br>
882 verified
404 bytes in
5.060000s
884 The failure message is something like:
<br>
885 <code>Verify operation failed address
0x00200000. Was
0x00 instead of
0x18</code>
890 Loading section .text, size
0x1cc lma
0x40000000<br>
891 Loading section .vectors, size
0x40 lma
0x400001cc<br>
892 Loading section .rodata, size
0x4 lma
0x4000020c<br>
893 Start address
0x40000000, load size
528<br>
894 Transfer rate:
53 bytes/sec,
176 bytes/write.
<br>
895 (gdb) monitor verify_image /tftp/
10.0.0.194/test_rom.elf
<br>
896 verified
528 bytes in
4.760000s (
0.108 kb/s)
<br>
897 Current language: auto
<br>
898 The current source language is
"auto; currently asm".
<br>