src/target/riscv/riscv.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #ifndef RISCV_H
   4 #define RISCV_H
   5
   6 struct riscv_program;
   7
   8 #include <stdint.h>
   9 #include "opcodes.h"
  10 #include "gdb_regs.h"
  11 #include "jtag/jtag.h"
  12 #include "target/register.h"
  13 #include <helper/command.h>
  14
  15 /* The register cache is statically allocated. */
  16 #define RISCV_MAX_HARTS 1024
  17 #define RISCV_MAX_REGISTERS 5000
  18 #define RISCV_MAX_TRIGGERS 32
  19 #define RISCV_MAX_HWBPS 16
  20
  21 #define DEFAULT_COMMAND_TIMEOUT_SEC             2
  22 #define DEFAULT_RESET_TIMEOUT_SEC               30
  23
  24 #define RISCV_SATP_MODE(xlen)  ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
  25 #define RISCV_SATP_PPN(xlen)  ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
  26 #define RISCV_PGSHIFT 12
  27
  28 # define PG_MAX_LEVEL 4
  29
  30 #define RISCV_NUM_MEM_ACCESS_METHODS  3
  31
  32 extern struct target_type riscv011_target;
  33 extern struct target_type riscv013_target;
  34
  35 /*
  36  * Definitions shared by code supporting all RISC-V versions.
  37  */
  38 typedef uint64_t riscv_reg_t;
  39 typedef uint32_t riscv_insn_t;
  40 typedef uint64_t riscv_addr_t;
  41
  42 enum riscv_mem_access_method {
  43         RISCV_MEM_ACCESS_UNSPECIFIED,
  44         RISCV_MEM_ACCESS_PROGBUF,
  45         RISCV_MEM_ACCESS_SYSBUS,
  46         RISCV_MEM_ACCESS_ABSTRACT
  47 };
  48
  49 enum riscv_halt_reason {
  50         RISCV_HALT_INTERRUPT,
  51         RISCV_HALT_BREAKPOINT,
  52         RISCV_HALT_SINGLESTEP,
  53         RISCV_HALT_TRIGGER,
  54         RISCV_HALT_UNKNOWN,
  55         RISCV_HALT_GROUP,
  56         RISCV_HALT_ERROR
  57 };
  58
  59 typedef struct {
  60         struct target *target;
  61         unsigned custom_number;
  62 } riscv_reg_info_t;
  63
  64 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE       0x80
  65 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER        0x81
  66 struct riscv_sample_buf {
  67         uint8_t *buf;
  68         unsigned int used;
  69         unsigned int size;
  70 };
  71
  72 typedef struct {
  73         bool enabled;
  74         struct {
  75                 bool enabled;
  76                 target_addr_t address;
  77                 uint32_t size_bytes;
  78         } bucket[16];
  79 } riscv_sample_config_t;
  80
  81 typedef struct {
  82         struct list_head list;
  83         uint16_t low, high;
  84         char *name;
  85 } range_list_t;
  86
  87 typedef struct {
  88         unsigned dtm_version;
  89
  90         struct command_context *cmd_ctx;
  91         void *version_specific;
  92
  93         /* The hart that is currently being debugged.  Note that this is
  94          * different than the hartid that the RTOS is expected to use.  This
  95          * one will change all the time, it's more of a global argument to
  96          * every function than an actual */
  97         int current_hartid;
  98
  99         /* Single buffer that contains all register names, instead of calling
 100          * malloc for each register. Needs to be freed when reg_list is freed. */
 101         char *reg_names;
 102
 103         /* It's possible that each core has a different supported ISA set. */
 104         int xlen;
 105         riscv_reg_t misa;
 106         /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
 107         unsigned int vlenb;
 108
 109         /* The number of triggers per hart. */
 110         unsigned int trigger_count;
 111
 112         /* For each physical trigger, contains -1 if the hwbp is available, or the
 113          * unique_id of the breakpoint/watchpoint that is using it.
 114          * Note that in RTOS mode the triggers are the same across all harts the
 115          * target controls, while otherwise only a single hart is controlled. */
 116         int trigger_unique_id[RISCV_MAX_HWBPS];
 117
 118         /* The number of entries in the debug buffer. */
 119         int debug_buffer_size;
 120
 121         /* This hart contains an implicit ebreak at the end of the program buffer. */
 122         bool impebreak;
 123
 124         bool triggers_enumerated;
 125
 126         /* Decremented every scan, and when it reaches 0 we clear the learned
 127          * delays, causing them to be relearned. Used for testing. */
 128         int reset_delays_wait;
 129
 130         /* This target has been prepped and is ready to step/resume. */
 131         bool prepped;
 132         /* This target was selected using hasel. */
 133         bool selected;
 134
 135         /* Helper functions that target the various RISC-V debug spec
 136          * implementations. */
 137         int (*get_register)(struct target *target, riscv_reg_t *value, int regid);
 138         int (*set_register)(struct target *target, int regid, uint64_t value);
 139         int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
 140         int (*set_register_buf)(struct target *target, int regno,
 141                         const uint8_t *buf);
 142         int (*select_current_hart)(struct target *target);
 143         bool (*is_halted)(struct target *target);
 144         /* Resume this target, as well as every other prepped target that can be
 145          * resumed near-simultaneously. Clear the prepped flag on any target that
 146          * was resumed. */
 147         int (*resume_go)(struct target *target);
 148         int (*step_current_hart)(struct target *target);
 149         int (*on_halt)(struct target *target);
 150         /* Get this target as ready as possible to resume, without actually
 151          * resuming. */
 152         int (*resume_prep)(struct target *target);
 153         int (*halt_prep)(struct target *target);
 154         int (*halt_go)(struct target *target);
 155         int (*on_step)(struct target *target);
 156         enum riscv_halt_reason (*halt_reason)(struct target *target);
 157         int (*write_debug_buffer)(struct target *target, unsigned index,
 158                         riscv_insn_t d);
 159         riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
 160         int (*execute_debug_buffer)(struct target *target);
 161         int (*dmi_write_u64_bits)(struct target *target);
 162         void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
 163         void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
 164         void (*fill_dmi_nop_u64)(struct target *target, char *buf);
 165
 166         int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
 167         int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
 168
 169         int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
 170         int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
 171
 172         int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
 173                         uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
 174
 175         int (*sample_memory)(struct target *target,
 176                                                  struct riscv_sample_buf *buf,
 177                                                  riscv_sample_config_t *config,
 178                                                  int64_t until_ms);
 179
 180         int (*read_memory)(struct target *target, target_addr_t address,
 181                         uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
 182
 183         /* How many harts are attached to the DM that this target is attached to? */
 184         int (*hart_count)(struct target *target);
 185         unsigned (*data_bits)(struct target *target);
 186
 187         COMMAND_HELPER((*print_info), struct target *target);
 188
 189         /* Storage for vector register types. */
 190         struct reg_data_type_vector vector_uint8;
 191         struct reg_data_type_vector vector_uint16;
 192         struct reg_data_type_vector vector_uint32;
 193         struct reg_data_type_vector vector_uint64;
 194         struct reg_data_type_vector vector_uint128;
 195         struct reg_data_type type_uint8_vector;
 196         struct reg_data_type type_uint16_vector;
 197         struct reg_data_type type_uint32_vector;
 198         struct reg_data_type type_uint64_vector;
 199         struct reg_data_type type_uint128_vector;
 200         struct reg_data_type_union_field vector_fields[5];
 201         struct reg_data_type_union vector_union;
 202         struct reg_data_type type_vector;
 203
 204         /* Set when trigger registers are changed by the user. This indicates we eed
 205          * to beware that we may hit a trigger that we didn't realize had been set. */
 206         bool manual_hwbp_set;
 207
 208         /* Memory access methods to use, ordered by priority, highest to lowest. */
 209         int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS];
 210
 211         /* Different memory regions may need different methods but single configuration is applied
 212          * for all. Following flags are used to warn only once about failing memory access method. */
 213         bool mem_access_progbuf_warn;
 214         bool mem_access_sysbus_warn;
 215         bool mem_access_abstract_warn;
 216
 217         /* In addition to the ones in the standard spec, we'll also expose additional
 218          * CSRs in this list. */
 219         struct list_head expose_csr;
 220         /* Same, but for custom registers.
 221          * Custom registers are for non-standard extensions and use abstract register numbers
 222          * from range 0xc000 ... 0xffff. */
 223         struct list_head expose_custom;
 224
 225         riscv_sample_config_t sample_config;
 226         struct riscv_sample_buf sample_buf;
 227 } riscv_info_t;
 228
 229 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
 230                            unsigned int value);
 231
 232 typedef struct {
 233         uint8_t tunneled_dr_width;
 234         struct scan_field tunneled_dr[4];
 235 } riscv_bscan_tunneled_scan_context_t;
 236
 237 typedef struct {
 238         const char *name;
 239         int level;
 240         unsigned va_bits;
 241         unsigned pte_shift;
 242         unsigned vpn_shift[PG_MAX_LEVEL];
 243         unsigned vpn_mask[PG_MAX_LEVEL];
 244         unsigned pte_ppn_shift[PG_MAX_LEVEL];
 245         unsigned pte_ppn_mask[PG_MAX_LEVEL];
 246         unsigned pa_ppn_shift[PG_MAX_LEVEL];
 247         unsigned pa_ppn_mask[PG_MAX_LEVEL];
 248 } virt2phys_info_t;
 249
 250 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 251 extern int riscv_command_timeout_sec;
 252
 253 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 254 extern int riscv_reset_timeout_sec;
 255
 256 extern bool riscv_enable_virtual;
 257 extern bool riscv_ebreakm;
 258 extern bool riscv_ebreaks;
 259 extern bool riscv_ebreaku;
 260
 261 /* Everything needs the RISC-V specific info structure, so here's a nice macro
 262  * that provides that. */
 263 static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
 264 static inline riscv_info_t *riscv_info(const struct target *target)
 265 {
 266         assert(target->arch_info);
 267         return target->arch_info;
 268 }
 269 #define RISCV_INFO(R) riscv_info_t *R = riscv_info(target);
 270
 271 extern uint8_t ir_dtmcontrol[4];
 272 extern struct scan_field select_dtmcontrol;
 273 extern uint8_t ir_dbus[4];
 274 extern struct scan_field select_dbus;
 275 extern uint8_t ir_idcode[4];
 276 extern struct scan_field select_idcode;
 277
 278 extern struct scan_field select_user4;
 279 extern struct scan_field *bscan_tunneled_select_dmi;
 280 extern uint32_t bscan_tunneled_select_dmi_num_fields;
 281 typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
 282 extern int bscan_tunnel_ir_width;
 283 extern bscan_tunnel_type_t bscan_tunnel_type;
 284
 285 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
 286 void select_dmi_via_bscan(struct target *target);
 287
 288 /*** OpenOCD Interface */
 289 int riscv_openocd_poll(struct target *target);
 290
 291 int riscv_halt(struct target *target);
 292
 293 int riscv_resume(
 294         struct target *target,
 295         int current,
 296         target_addr_t address,
 297         int handle_breakpoints,
 298         int debug_execution,
 299         bool single_hart
 300 );
 301
 302 int riscv_openocd_step(
 303         struct target *target,
 304         int current,
 305         target_addr_t address,
 306         int handle_breakpoints
 307 );
 308
 309 int riscv_openocd_assert_reset(struct target *target);
 310 int riscv_openocd_deassert_reset(struct target *target);
 311
 312 /*** RISC-V Interface ***/
 313
 314 /* Initializes the shared RISC-V structure. */
 315 void riscv_info_init(struct target *target, riscv_info_t *r);
 316
 317 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
 318  * then the only hart. */
 319 int riscv_step_rtos_hart(struct target *target);
 320
 321 bool riscv_supports_extension(struct target *target, char letter);
 322
 323 /* Returns XLEN for the given (or current) hart. */
 324 unsigned riscv_xlen(const struct target *target);
 325 int riscv_xlen_of_hart(const struct target *target);
 326
 327 /* Sets the current hart, which is the hart that will actually be used when
 328  * issuing debug commands. */
 329 int riscv_set_current_hartid(struct target *target, int hartid);
 330 int riscv_select_current_hart(struct target *target);
 331 int riscv_current_hartid(const struct target *target);
 332
 333 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
 334  * without requiring multiple targets.  */
 335
 336 /* Lists the number of harts in the system, which are assumed to be
 337  * consecutive and start with mhartid=0. */
 338 int riscv_count_harts(struct target *target);
 339
 340 /** Set register, updating the cache. */
 341 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
 342 /** Get register, from the cache if it's in there. */
 343 int riscv_get_register(struct target *target, riscv_reg_t *value,
 344                 enum gdb_regno r);
 345
 346 /* Checks the state of the current hart -- "is_halted" checks the actual
 347  * on-device register. */
 348 bool riscv_is_halted(struct target *target);
 349 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
 350
 351 /* These helper functions let the generic program interface get target-specific
 352  * information. */
 353 size_t riscv_debug_buffer_size(struct target *target);
 354
 355 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
 356 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
 357 int riscv_execute_debug_buffer(struct target *target);
 358
 359 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
 360 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
 361 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
 362 int riscv_dmi_write_u64_bits(struct target *target);
 363
 364 /* Invalidates the register cache. */
 365 void riscv_invalidate_register_cache(struct target *target);
 366
 367 int riscv_enumerate_triggers(struct target *target);
 368
 369 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 370 int riscv_remove_breakpoint(struct target *target,
 371                 struct breakpoint *breakpoint);
 372 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 373 int riscv_remove_watchpoint(struct target *target,
 374                 struct watchpoint *watchpoint);
 375 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_address);
 376
 377 int riscv_init_registers(struct target *target);
 378
 379 void riscv_semihosting_init(struct target *target);
 380 typedef enum {
 381         SEMI_NONE,              /* Not halted for a semihosting call. */
 382         SEMI_HANDLED,   /* Call handled, and target was resumed. */
 383         SEMI_WAITING,   /* Call handled, target is halted waiting until we can resume. */
 384         SEMI_ERROR              /* Something went wrong. */
 385 } semihosting_result_t;
 386 semihosting_result_t riscv_semihosting(struct target *target, int *retval);
 387
 388 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
 389                 riscv_bscan_tunneled_scan_context_t *ctxt);
 390
 391 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
 392 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
 393
 394 #endif