src/target/x86_32_common.h

   1 /*
   2  * Copyright(c) 2013 Intel Corporation.
   3  *
   4  * Adrian Burns (adrian.burns@intel.com)
   5  * Thomas Faust (thomas.faust@intel.com)
   6  * Ivan De Cesaris (ivan.de.cesaris@intel.com)
   7  * Julien Carreno (julien.carreno@intel.com)
   8  * Jeffrey Maxwell (jeffrey.r.maxwell@intel.com)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22  *
  23  * Contact Information:
  24  * Intel Corporation
  25  */
  26
  27 /*
  28  * @file
  29  * This is the interface to the x86 32 bit memory and breakpoint operations.
  30  */
  31
  32 #ifndef X86_32_COMMON_H
  33 #define X86_32_COMMON_H
  34
  35 #include <jtag/jtag.h>
  36 #include <helper/command.h>
  37
  38 extern const struct command_registration x86_32_command_handlers[];
  39
  40 /* for memory access */
  41 #define BYTE                    1
  42 #define WORD                    2
  43 #define DWORD                   4
  44
  45 #define EFLAGS_TF               0x00000100 /* Trap Flag */
  46 #define EFLAGS_IF               0x00000200 /* Interrupt Flag */
  47 #define EFLAGS_RF               0x00010000 /* Resume Flag */
  48 #define EFLAGS_VM86             0x00020000 /* Virtual 8086 Mode */
  49
  50 #define CSAR_DPL                0x00006000
  51 #define CSAR_D                  0x00400000
  52 #define SSAR_DPL                0x00006000
  53
  54 #define CR0_PE                  0x00000001 /* Protected Mode Enable */
  55 #define CR0_NW                  0x20000000 /* Non Write-Through */
  56 #define CR0_CD                  0x40000000 /* Cache Disable */
  57 #define CR0_PG                  0x80000000 /* Paging Enable */
  58
  59 /* TODO - move back to PM specific file */
  60 #define PM_DR6                  0xFFFF0FF0
  61
  62 #define DR6_BRKDETECT_0         0x00000001 /* B0 through B3 */
  63 #define DR6_BRKDETECT_1         0x00000002 /* breakpoint condition detected */
  64 #define DR6_BRKDETECT_2         0x00000004
  65 #define DR6_BRKDETECT_3         0x00000008
  66
  67 enum {
  68         /* general purpose registers */
  69         EAX = 0,
  70         ECX,
  71         EDX,
  72         EBX,
  73         ESP,
  74         EBP,
  75         ESI,
  76         EDI,
  77         /* instruction pointer & flags */
  78         EIP,
  79         EFLAGS,
  80
  81         /* segment registers */
  82         CS,
  83         SS,
  84         DS,
  85         ES,
  86         FS,
  87         GS,
  88
  89         /* floating point unit registers */
  90         ST0,
  91         ST1,
  92         ST2,
  93         ST3,
  94         ST4,
  95         ST5,
  96         ST6,
  97         ST7,
  98         FCTRL,
  99         FSTAT,
 100         FTAG,
 101         FISEG,
 102         FIOFF,
 103         FOSEG,
 104         FOOFF,
 105         FOP,
 106
 107         /* control registers */
 108         CR0,
 109         CR2,
 110         CR3,
 111         CR4,
 112
 113         /* debug registers */
 114         DR0,
 115         DR1,
 116         DR2,
 117         DR3,
 118         DR6,
 119         DR7,
 120
 121         /* descriptor tables */
 122         IDTB,
 123         IDTL,
 124         IDTAR,
 125         GDTB,
 126         GDTL,
 127         GDTAR,
 128         TR,
 129         LDTR,
 130         LDTB,
 131         LDTL,
 132         LDTAR,
 133
 134         /* segment registers */
 135         CSB,
 136         CSL,
 137         CSAR,
 138         DSB,
 139         DSL,
 140         DSAR,
 141         ESB,
 142         ESL,
 143         ESAR,
 144         FSB,
 145         FSL,
 146         FSAR,
 147         GSB,
 148         GSL,
 149         GSAR,
 150         SSB,
 151         SSL,
 152         SSAR,
 153         TSSB,
 154         TSSL,
 155         TSSAR,
 156
 157         /* PM control reg */
 158         PMCR,
 159 };
 160
 161 #define X86_32_COMMON_MAGIC 0x86328632
 162
 163 enum {
 164         /* memory read/write */
 165         MEMRDB32 = 0,
 166         MEMRDB16,
 167         MEMRDH32,
 168         MEMRDH16,
 169         MEMRDW32,
 170         MEMRDW16,
 171         MEMWRB32,
 172         MEMWRB16,
 173         MEMWRH32,
 174         MEMWRH16,
 175         MEMWRW32,
 176         MEMWRW16,
 177         /* IO read/write */
 178         IORDB32,
 179         IORDB16,
 180         IORDH32,
 181         IORDH16,
 182         IORDW32,
 183         IORDW16,
 184         IOWRB32,
 185         IOWRB16,
 186         IOWRH32,
 187         IOWRH16,
 188         IOWRW32,
 189         IOWRW16,
 190         /* lakemont1 core shadow ram access opcodes */
 191         SRAMACCESS,
 192         SRAM2PDR,
 193         PDR2SRAM,
 194         WBINVD,
 195 };
 196
 197 struct swbp_mem_patch {
 198         uint8_t orig_byte;
 199         uint32_t swbp_unique_id;
 200         uint32_t physaddr;
 201         struct swbp_mem_patch *next;
 202 };
 203
 204 /* TODO - probemode specific - consider removing */
 205 #define NUM_PM_REGS             18 /* regs used in save/restore */
 206
 207 struct x86_32_common {
 208         uint32_t common_magic;
 209         void *arch_info;
 210         struct reg_cache *cache;
 211         struct jtag_tap *curr_tap;
 212         uint32_t stored_pc;
 213         int flush;
 214
 215         /* pm_regs are for probemode save/restore state */
 216         uint32_t pm_regs[NUM_PM_REGS];
 217
 218         /* working area for fastdata access */
 219         struct working_area *fast_data_area;
 220
 221         int num_hw_bpoints;
 222         struct x86_32_dbg_reg *hw_break_list;
 223         struct swbp_mem_patch *swbbp_mem_patch_list;
 224
 225         /* core probemode implementation dependent functions */
 226         uint8_t (*get_num_user_regs)(struct target *t);
 227         bool (*is_paging_enabled)(struct target *t);
 228         int (*disable_paging)(struct target *t);
 229         int (*enable_paging)(struct target *t);
 230         bool (*sw_bpts_supported)(struct target *t);
 231         int (*transaction_status)(struct target *t);
 232         int (*submit_instruction)(struct target *t, int num);
 233         int (*read_hw_reg)(struct target *t, int reg, uint32_t *regval, uint8_t cache);
 234         int (*write_hw_reg)(struct target *t, int reg,
 235                                 uint32_t regval, uint8_t cache);
 236
 237         /* register cache to processor synchronization */
 238         int (*read_hw_reg_to_cache)(struct target *target, int num);
 239         int (*write_hw_reg_from_cache)(struct target *target, int num);
 240 };
 241
 242 static inline struct x86_32_common *
 243 target_to_x86_32(struct target *target)
 244 {
 245         return target->arch_info;
 246 }
 247 bool check_not_halted(const struct target *t);
 248
 249 /* breakpoint defines */
 250 #define MAX_DEBUG_REGS          4
 251 #define SW_BP_OPCODE            0xf1
 252 #define MAX_SW_BPTS             20
 253
 254 struct x86_32_dbg_reg {
 255         int used;
 256         uint32_t bp_value;
 257 };
 258
 259 #define DR7_G_ENABLE_SHIFT              1
 260 #define DR7_ENABLE_SIZE                 2 /* 2 bits per debug reg */
 261 #define DR7_RW_SHIFT                    16
 262 #define DR7_LENGTH_SHIFT                18
 263 #define DR7_RW_LEN_SIZE                 4
 264 #define DR7_BP_EXECUTE                  0 /* 00 - only on instruction execution*/
 265 #define DR7_BP_WRITE                    1 /* 01 - only on data writes */
 266 /*#define DR7_RW_IORW                   2 UNSUPPORTED 10 - an I/O read and I/O write */
 267 #define DR7_BP_READWRITE                3 /* on data read or data write */
 268 #define DR7_BP_LENGTH_1                 0 /* 00 - 1 byte length */
 269 #define DR7_BP_LENGTH_2                 1 /* 01 - 2 byte length */
 270 #define DR7_BP_LENGTH_4                 3 /* 11 - 4 byte length */
 271
 272 #define DR7_GLOBAL_ENABLE(val, regnum) \
 273         (val |= (1 << (DR7_G_ENABLE_SHIFT + (DR7_ENABLE_SIZE * (regnum)))))
 274
 275 #define DR7_GLOBAL_DISABLE(val, regnum) \
 276         (val &= ~(3 << (DR7_ENABLE_SIZE * (regnum))))
 277
 278 #define DR7_BP_FREE(val, regnum) \
 279         ((val & (3 << (DR7_ENABLE_SIZE * (regnum)))) == 0)
 280
 281 #define DR7_RESET_RWLEN_BITS(val, regnum) \
 282         (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 283
 284 #define DR7_SET_EXE(val, regnum) \
 285         (val &= ~(0x0f << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 286
 287 #define DR7_SET_WRITE(val, regnum) \
 288         (val |= (DR7_BP_WRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 289
 290 #define DR7_SET_ACCESS(val, regnum) \
 291         (val |= (DR7_BP_READWRITE << (DR7_RW_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 292
 293 #define DR7_SET_LENGTH(val, regnum, len) \
 294         (val |= (len == 1) ? (DR7_BP_LENGTH_1 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
 295         (len == 2) ? (DR7_BP_LENGTH_2 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))) : \
 296         (DR7_BP_LENGTH_4 << (DR7_LENGTH_SHIFT + DR7_RW_LEN_SIZE * (regnum))))
 297
 298 /* public interface */
 299 int x86_32_get_gdb_reg_list(struct target *t,
 300                         struct reg **reg_list[], int *reg_list_size,
 301                         enum target_register_class reg_class);
 302 int x86_32_common_init_arch_info(struct target *target,
 303                         struct x86_32_common *x86_32);
 304 int x86_32_common_mmu(struct target *t, int *enabled);
 305 int x86_32_common_virt2phys(struct target *t, uint32_t address, uint32_t *physical);
 306 int x86_32_common_read_phys_mem(struct target *t, uint32_t phys_address,
 307                         uint32_t size, uint32_t count, uint8_t *buffer);
 308 int x86_32_common_write_phys_mem(struct target *t, uint32_t phys_address,
 309                         uint32_t size, uint32_t count, const uint8_t *buffer);
 310 int x86_32_common_read_memory(struct target *t, uint32_t addr,
 311                         uint32_t size, uint32_t count, uint8_t *buf);
 312 int x86_32_common_write_memory(struct target *t, uint32_t addr,
 313                         uint32_t size, uint32_t count, const uint8_t *buf);
 314 int x86_32_common_read_io(struct target *t, uint32_t addr,
 315                         uint32_t size, uint8_t *buf);
 316 int x86_32_common_write_io(struct target *t, uint32_t addr,
 317                         uint32_t size, const uint8_t *buf);
 318 int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
 319 int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
 320 int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
 321 int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
 322
 323 #endif /* X86_32_COMMON_H */