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Restore -dev suffix
[openocd.git] / src / target / armv4_5.c
blobdc77af2b158830b628a78ba39a462d684551698d
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "arm.h"
32 #include "armv4_5.h"
33 #include "arm_jtag.h"
34 #include "breakpoints.h"
35 #include "arm_disassembler.h"
36 #include <helper/binarybuffer.h>
37 #include "algorithm.h"
38 #include "register.h"
39
40 /* offsets into armv4_5 core register cache */
41 enum {
42 /* ARMV4_5_CPSR = 31, */
43 ARMV4_5_SPSR_FIQ = 32,
44 ARMV4_5_SPSR_IRQ = 33,
45 ARMV4_5_SPSR_SVC = 34,
46 ARMV4_5_SPSR_ABT = 35,
47 ARMV4_5_SPSR_UND = 36,
48 ARM_SPSR_MON = 41,
49 };
50
51 static const uint8_t arm_usr_indices[17] = {
52 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
53 };
54
55 static const uint8_t arm_fiq_indices[8] = {
56 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
57 };
58
59 static const uint8_t arm_irq_indices[3] = {
60 23, 24, ARMV4_5_SPSR_IRQ,
61 };
62
63 static const uint8_t arm_svc_indices[3] = {
64 25, 26, ARMV4_5_SPSR_SVC,
65 };
66
67 static const uint8_t arm_abt_indices[3] = {
68 27, 28, ARMV4_5_SPSR_ABT,
69 };
70
71 static const uint8_t arm_und_indices[3] = {
72 29, 30, ARMV4_5_SPSR_UND,
73 };
74
75 static const uint8_t arm_mon_indices[3] = {
76 39, 40, ARM_SPSR_MON,
77 };
78
79 static const struct {
80 const char *name;
81 unsigned short psr;
82 /* For user and system modes, these list indices for all registers.
83 * otherwise they're just indices for the shadow registers and SPSR.
84 */
85 unsigned short n_indices;
86 const uint8_t *indices;
87 } arm_mode_data[] = {
88 /* Seven modes are standard from ARM7 on. "System" and "User" share
89 * the same registers; other modes shadow from 3 to 8 registers.
90 */
91 {
92 .name = "User",
93 .psr = ARM_MODE_USR,
94 .n_indices = ARRAY_SIZE(arm_usr_indices),
95 .indices = arm_usr_indices,
96 },
97 {
98 .name = "FIQ",
99 .psr = ARM_MODE_FIQ,
100 .n_indices = ARRAY_SIZE(arm_fiq_indices),
101 .indices = arm_fiq_indices,
102 },
103 {
104 .name = "Supervisor",
105 .psr = ARM_MODE_SVC,
106 .n_indices = ARRAY_SIZE(arm_svc_indices),
107 .indices = arm_svc_indices,
108 },
109 {
110 .name = "Abort",
111 .psr = ARM_MODE_ABT,
112 .n_indices = ARRAY_SIZE(arm_abt_indices),
113 .indices = arm_abt_indices,
114 },
115 {
116 .name = "IRQ",
117 .psr = ARM_MODE_IRQ,
118 .n_indices = ARRAY_SIZE(arm_irq_indices),
119 .indices = arm_irq_indices,
120 },
121 {
122 .name = "Undefined instruction",
123 .psr = ARM_MODE_UND,
124 .n_indices = ARRAY_SIZE(arm_und_indices),
125 .indices = arm_und_indices,
126 },
127 {
128 .name = "System",
129 .psr = ARM_MODE_SYS,
130 .n_indices = ARRAY_SIZE(arm_usr_indices),
131 .indices = arm_usr_indices,
132 },
133 /* TrustZone "Security Extensions" add a secure monitor mode.
134 * This is distinct from a "debug monitor" which can support
135 * non-halting debug, in conjunction with some debuggers.
136 */
137 {
138 .name = "Secure Monitor",
139 .psr = ARM_MODE_MON,
140 .n_indices = ARRAY_SIZE(arm_mon_indices),
141 .indices = arm_mon_indices,
142 },
143
144 /* These special modes are currently only supported
145 * by ARMv6M and ARMv7M profiles */
146 {
147 .name = "Thread",
148 .psr = ARM_MODE_THREAD,
149 },
150 {
151 .name = "Thread (User)",
152 .psr = ARM_MODE_USER_THREAD,
153 },
154 {
155 .name = "Handler",
156 .psr = ARM_MODE_HANDLER,
157 },
158 };
159
160 /** Map PSR mode bits to the name of an ARM processor operating mode. */
161 const char *arm_mode_name(unsigned psr_mode)
162 {
163 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
164 if (arm_mode_data[i].psr == psr_mode)
165 return arm_mode_data[i].name;
166 }
167 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
168 return "UNRECOGNIZED";
169 }
170
171 /** Return true iff the parameter denotes a valid ARM processor mode. */
172 bool is_arm_mode(unsigned psr_mode)
173 {
174 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
175 if (arm_mode_data[i].psr == psr_mode)
176 return true;
177 }
178 return false;
179 }
180
181 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
182 int arm_mode_to_number(enum arm_mode mode)
183 {
184 switch (mode) {
185 case ARM_MODE_ANY:
186 /* map MODE_ANY to user mode */
187 case ARM_MODE_USR:
188 return 0;
189 case ARM_MODE_FIQ:
190 return 1;
191 case ARM_MODE_IRQ:
192 return 2;
193 case ARM_MODE_SVC:
194 return 3;
195 case ARM_MODE_ABT:
196 return 4;
197 case ARM_MODE_UND:
198 return 5;
199 case ARM_MODE_SYS:
200 return 6;
201 case ARM_MODE_MON:
202 return 7;
203 default:
204 LOG_ERROR("invalid mode value encountered %d", mode);
205 return -1;
206 }
207 }
208
209 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
210 enum arm_mode armv4_5_number_to_mode(int number)
211 {
212 switch (number) {
213 case 0:
214 return ARM_MODE_USR;
215 case 1:
216 return ARM_MODE_FIQ;
217 case 2:
218 return ARM_MODE_IRQ;
219 case 3:
220 return ARM_MODE_SVC;
221 case 4:
222 return ARM_MODE_ABT;
223 case 5:
224 return ARM_MODE_UND;
225 case 6:
226 return ARM_MODE_SYS;
227 case 7:
228 return ARM_MODE_MON;
229 default:
230 LOG_ERROR("mode index out of bounds %d", number);
231 return ARM_MODE_ANY;
232 }
233 }
234
235 static const char *arm_state_strings[] = {
236 "ARM", "Thumb", "Jazelle", "ThumbEE",
237 };
238
239 /* Templates for ARM core registers.
240 *
241 * NOTE: offsets in this table are coupled to the arm_mode_data
242 * table above, the armv4_5_core_reg_map array below, and also to
243 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
244 */
245 static const struct {
246 /* The name is used for e.g. the "regs" command. */
247 const char *name;
248
249 /* The {cookie, mode} tuple uniquely identifies one register.
250 * In a given mode, cookies 0..15 map to registers R0..R15,
251 * with R13..R15 usually called SP, LR, PC.
252 *
253 * MODE_ANY is used as *input* to the mapping, and indicates
254 * various special cases (sigh) and errors.
255 *
256 * Cookie 16 is (currently) confusing, since it indicates
257 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
258 * (Exception modes have both CPSR and SPSR registers ...)
259 */
260 unsigned cookie;
261 unsigned gdb_index;
262 enum arm_mode mode;
263 } arm_core_regs[] = {
264 /* IMPORTANT: we guarantee that the first eight cached registers
265 * correspond to r0..r7, and the fifteenth to PC, so that callers
266 * don't need to map them.
267 */
268 { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
269 { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
270 { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
271 { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
272 { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
273 { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
274 { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
275 { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
276
277 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
278 * them as MODE_ANY creates special cases. (ANY means
279 * "not mapped" elsewhere; here it's "everything but FIQ".)
280 */
281 { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
282 { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
283 { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
284 { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
285 { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
286
287 /* Historical GDB mapping of indices:
288 * - 13-14 are sp and lr, but banked counterparts are used
289 * - 16-24 are left for deprecated 8 FPA + 1 FPS
290 * - 25 is the cpsr
291 */
292
293 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
294 { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
295 { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
296
297 /* guaranteed to be at index 15 */
298 { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
299 { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
300 { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
301 { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
302 { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
303 { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
304
305 { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
306 { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
307
308 { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
309 { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
310
311 { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
312 { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
313
314 { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
315 { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
316
317 { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
318 { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
319
320 { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
321 { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
322 { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
323 { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
324 { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
325 { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
326
327 /* These are only used for GDB target description, banked registers are accessed instead */
328 { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
329 { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
330
331 /* These exist only when the Security Extension (TrustZone) is present */
332 { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
333 { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
334 { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
335
336 };
337
338 /* map core mode (USR, FIQ, ...) and register number to
339 * indices into the register cache
340 */
341 const int armv4_5_core_reg_map[8][17] = {
342 { /* USR */
343 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
344 },
345 { /* FIQ (8 shadows of USR, vs normal 3) */
346 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
347 },
348 { /* IRQ */
349 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
350 },
351 { /* SVC */
352 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
353 },
354 { /* ABT */
355 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
356 },
357 { /* UND */
358 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
359 },
360 { /* SYS (same registers as USR) */
361 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
362 },
363 { /* MON */
364 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
365 }
366 };
367
368 /**
369 * Configures host-side ARM records to reflect the specified CPSR.
370 * Later, code can use arm_reg_current() to map register numbers
371 * according to how they are exposed by this mode.
372 */
373 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
374 {
375 enum arm_mode mode = cpsr & 0x1f;
376 int num;
377
378 /* NOTE: this may be called very early, before the register
379 * cache is set up. We can't defend against many errors, in
380 * particular against CPSRs that aren't valid *here* ...
381 */
382 if (arm->cpsr) {
383 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
384 arm->cpsr->valid = 1;
385 arm->cpsr->dirty = 0;
386 }
387
388 arm->core_mode = mode;
389
390 /* mode_to_number() warned; set up a somewhat-sane mapping */
391 num = arm_mode_to_number(mode);
392 if (num < 0) {
393 mode = ARM_MODE_USR;
394 num = 0;
395 }
396
397 arm->map = &armv4_5_core_reg_map[num][0];
398 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
399 ? NULL
400 : arm->core_cache->reg_list + arm->map[16];
401
402 /* Older ARMs won't have the J bit */
403 enum arm_state state;
404
405 if (cpsr & (1 << 5)) { /* T */
406 if (cpsr & (1 << 24)) { /* J */
407 LOG_WARNING("ThumbEE -- incomplete support");
408 state = ARM_STATE_THUMB_EE;
409 } else
410 state = ARM_STATE_THUMB;
411 } else {
412 if (cpsr & (1 << 24)) { /* J */
413 LOG_ERROR("Jazelle state handling is BROKEN!");
414 state = ARM_STATE_JAZELLE;
415 } else
416 state = ARM_STATE_ARM;
417 }
418 arm->core_state = state;
419
420 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
421 arm_mode_name(mode),
422 arm_state_strings[arm->core_state]);
423 }
424
425 /**
426 * Returns handle to the register currently mapped to a given number.
427 * Someone must have called arm_set_cpsr() before.
428 *
429 * \param arm This core's state and registers are used.
430 * \param regnum From 0..15 corresponding to R0..R14 and PC.
431 * Note that R0..R7 don't require mapping; you may access those
432 * as the first eight entries in the register cache. Likewise
433 * R15 (PC) doesn't need mapping; you may also access it directly.
434 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
435 * CPSR (arm->cpsr) is also not mapped.
436 */
437 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
438 {
439 struct reg *r;
440
441 if (regnum > 16)
442 return NULL;
443
444 if (!arm->map) {
445 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
446 r = arm->core_cache->reg_list + regnum;
447 } else
448 r = arm->core_cache->reg_list + arm->map[regnum];
449
450 /* e.g. invalid CPSR said "secure monitor" mode on a core
451 * that doesn't support it...
452 */
453 if (!r) {
454 LOG_ERROR("Invalid CPSR mode");
455 r = arm->core_cache->reg_list + regnum;
456 }
457
458 return r;
459 }
460
461 static const uint8_t arm_gdb_dummy_fp_value[12];
462
463 static struct reg_feature arm_gdb_dummy_fp_features = {
464 .name = "net.sourceforge.openocd.fake_fpa"
465 };
466
467 /**
468 * Dummy FPA registers are required to support GDB on ARM.
469 * Register packets require eight obsolete FPA register values.
470 * Modern ARM cores use Vector Floating Point (VFP), if they
471 * have any floating point support. VFP is not FPA-compatible.
472 */
473 struct reg arm_gdb_dummy_fp_reg = {
474 .name = "GDB dummy FPA register",
475 .value = (uint8_t *) arm_gdb_dummy_fp_value,
476 .valid = 1,
477 .size = 96,
478 .exist = false,
479 .number = 16,
480 .feature = &arm_gdb_dummy_fp_features,
481 .group = "fake_fpa",
482 };
483
484 static const uint8_t arm_gdb_dummy_fps_value[4];
485
486 /**
487 * Dummy FPA status registers are required to support GDB on ARM.
488 * Register packets require an obsolete FPA status register.
489 */
490 struct reg arm_gdb_dummy_fps_reg = {
491 .name = "GDB dummy FPA status register",
492 .value = (uint8_t *) arm_gdb_dummy_fps_value,
493 .valid = 1,
494 .size = 32,
495 .exist = false,
496 .number = 24,
497 .feature = &arm_gdb_dummy_fp_features,
498 .group = "fake_fpa",
499 };
500
501 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
502
503 static void arm_gdb_dummy_init(void)
504 {
505 register_init_dummy(&arm_gdb_dummy_fp_reg);
506 register_init_dummy(&arm_gdb_dummy_fps_reg);
507 }
508
509 static int armv4_5_get_core_reg(struct reg *reg)
510 {
511 int retval;
512 struct arm_reg *reg_arch_info = reg->arch_info;
513 struct target *target = reg_arch_info->target;
514
515 if (target->state != TARGET_HALTED) {
516 LOG_ERROR("Target not halted");
517 return ERROR_TARGET_NOT_HALTED;
518 }
519
520 retval = reg_arch_info->arm->read_core_reg(target, reg,
521 reg_arch_info->num, reg_arch_info->mode);
522 if (retval == ERROR_OK) {
523 reg->valid = 1;
524 reg->dirty = 0;
525 }
526
527 return retval;
528 }
529
530 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
531 {
532 struct arm_reg *reg_arch_info = reg->arch_info;
533 struct target *target = reg_arch_info->target;
534 struct arm *armv4_5_target = target_to_arm(target);
535 uint32_t value = buf_get_u32(buf, 0, 32);
536
537 if (target->state != TARGET_HALTED) {
538 LOG_ERROR("Target not halted");
539 return ERROR_TARGET_NOT_HALTED;
540 }
541
542 /* Except for CPSR, the "reg" command exposes a writeback model
543 * for the register cache.
544 */
545 if (reg == armv4_5_target->cpsr) {
546 arm_set_cpsr(armv4_5_target, value);
547
548 /* Older cores need help to be in ARM mode during halt
549 * mode debug, so we clear the J and T bits if we flush.
550 * For newer cores (v6/v7a/v7r) we don't need that, but
551 * it won't hurt since CPSR is always flushed anyway.
552 */
553 if (armv4_5_target->core_mode !=
554 (enum arm_mode)(value & 0x1f)) {
555 LOG_DEBUG("changing ARM core mode to '%s'",
556 arm_mode_name(value & 0x1f));
557 value &= ~((1 << 24) | (1 << 5));
558 armv4_5_target->write_core_reg(target, reg,
559 16, ARM_MODE_ANY, value);
560 }
561 } else {
562 buf_set_u32(reg->value, 0, 32, value);
563 reg->valid = 1;
564 }
565 reg->dirty = 1;
566
567 return ERROR_OK;
568 }
569
570 static const struct reg_arch_type arm_reg_type = {
571 .get = armv4_5_get_core_reg,
572 .set = armv4_5_set_core_reg,
573 };
574
575 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
576 {
577 int num_regs = ARRAY_SIZE(arm_core_regs);
578 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
579 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
580 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
581 int i;
582
583 if (!cache || !reg_list || !reg_arch_info) {
584 free(cache);
585 free(reg_list);
586 free(reg_arch_info);
587 return NULL;
588 }
589
590 cache->name = "ARM registers";
591 cache->next = NULL;
592 cache->reg_list = reg_list;
593 cache->num_regs = 0;
594
595 for (i = 0; i < num_regs; i++) {
596 /* Skip registers this core doesn't expose */
597 if (arm_core_regs[i].mode == ARM_MODE_MON
598 && arm->core_type != ARM_MODE_MON)
599 continue;
600
601 /* REVISIT handle Cortex-M, which only shadows R13/SP */
602
603 reg_arch_info[i].num = arm_core_regs[i].cookie;
604 reg_arch_info[i].mode = arm_core_regs[i].mode;
605 reg_arch_info[i].target = target;
606 reg_arch_info[i].arm = arm;
607
608 reg_list[i].name = (char *) arm_core_regs[i].name;
609 reg_list[i].number = arm_core_regs[i].gdb_index;
610 reg_list[i].size = 32;
611 reg_list[i].value = &reg_arch_info[i].value;
612 reg_list[i].type = &arm_reg_type;
613 reg_list[i].arch_info = &reg_arch_info[i];
614 reg_list[i].exist = true;
615
616 /* This really depends on the calling convention in use */
617 reg_list[i].caller_save = false;
618
619 /* Registers data type, as used by GDB target description */
620 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
621 switch (arm_core_regs[i].cookie) {
622 case 13:
623 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
624 break;
625 case 14:
626 case 15:
627 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
628 break;
629 default:
630 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
631 break;
632 }
633
634 /* let GDB shows banked registers only in "info all-reg" */
635 reg_list[i].feature = malloc(sizeof(struct reg_feature));
636 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
637 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
638 reg_list[i].group = "general";
639 } else {
640 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
641 reg_list[i].group = "banked";
642 }
643
644 cache->num_regs++;
645 }
646
647 arm->pc = reg_list + 15;
648 arm->cpsr = reg_list + ARMV4_5_CPSR;
649 arm->core_cache = cache;
650 return cache;
651 }
652
653 int arm_arch_state(struct target *target)
654 {
655 struct arm *arm = target_to_arm(target);
656
657 if (arm->common_magic != ARM_COMMON_MAGIC) {
658 LOG_ERROR("BUG: called for a non-ARM target");
659 return ERROR_FAIL;
660 }
661
662 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
663 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
664 arm_state_strings[arm->core_state],
665 debug_reason_name(target),
666 arm_mode_name(arm->core_mode),
667 buf_get_u32(arm->cpsr->value, 0, 32),
668 buf_get_u32(arm->pc->value, 0, 32),
669 arm->is_semihosting ? ", semihosting" : "");
670
671 return ERROR_OK;
672 }
673
674 #define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
675 (cache->reg_list[armv4_5_core_reg_map[mode][num]])
676
677 COMMAND_HANDLER(handle_armv4_5_reg_command)
678 {
679 struct target *target = get_current_target(CMD_CTX);
680 struct arm *arm = target_to_arm(target);
681 struct reg *regs;
682
683 if (!is_arm(arm)) {
684 command_print(CMD_CTX, "current target isn't an ARM");
685 return ERROR_FAIL;
686 }
687
688 if (target->state != TARGET_HALTED) {
689 command_print(CMD_CTX, "error: target must be halted for register accesses");
690 return ERROR_FAIL;
691 }
692
693 if (arm->core_type != ARM_MODE_ANY) {
694 command_print(CMD_CTX,
695 "Microcontroller Profile not supported - use standard reg cmd");
696 return ERROR_OK;
697 }
698
699 if (!is_arm_mode(arm->core_mode)) {
700 LOG_ERROR("not a valid arm core mode - communication failure?");
701 return ERROR_FAIL;
702 }
703
704 if (!arm->full_context) {
705 command_print(CMD_CTX, "error: target doesn't support %s",
706 CMD_NAME);
707 return ERROR_FAIL;
708 }
709
710 regs = arm->core_cache->reg_list;
711
712 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
713 const char *name;
714 char *sep = "\n";
715 char *shadow = "";
716
717 /* label this bank of registers (or shadows) */
718 switch (arm_mode_data[mode].psr) {
719 case ARM_MODE_SYS:
720 continue;
721 case ARM_MODE_USR:
722 name = "System and User";
723 sep = "";
724 break;
725 case ARM_MODE_MON:
726 if (arm->core_type != ARM_MODE_MON)
727 continue;
728 /* FALLTHROUGH */
729 default:
730 name = arm_mode_data[mode].name;
731 shadow = "shadow ";
732 break;
733 }
734 command_print(CMD_CTX, "%s%s mode %sregisters",
735 sep, name, shadow);
736
737 /* display N rows of up to 4 registers each */
738 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
739 char output[80];
740 int output_len = 0;
741
742 for (unsigned j = 0; j < 4; j++, i++) {
743 uint32_t value;
744 struct reg *reg = regs;
745
746 if (i >= arm_mode_data[mode].n_indices)
747 break;
748
749 reg += arm_mode_data[mode].indices[i];
750
751 /* REVISIT be smarter about faults... */
752 if (!reg->valid)
753 arm->full_context(target);
754
755 value = buf_get_u32(reg->value, 0, 32);
756 output_len += snprintf(output + output_len,
757 sizeof(output) - output_len,
758 "%8s: %8.8" PRIx32 " ",
759 reg->name, value);
760 }
761 command_print(CMD_CTX, "%s", output);
762 }
763 }
764
765 return ERROR_OK;
766 }
767
768 COMMAND_HANDLER(handle_armv4_5_core_state_command)
769 {
770 struct target *target = get_current_target(CMD_CTX);
771 struct arm *arm = target_to_arm(target);
772
773 if (!is_arm(arm)) {
774 command_print(CMD_CTX, "current target isn't an ARM");
775 return ERROR_FAIL;
776 }
777
778 if (arm->core_type == ARM_MODE_THREAD) {
779 /* armv7m not supported */
780 command_print(CMD_CTX, "Unsupported Command");
781 return ERROR_OK;
782 }
783
784 if (CMD_ARGC > 0) {
785 if (strcmp(CMD_ARGV[0], "arm") == 0)
786 arm->core_state = ARM_STATE_ARM;
787 if (strcmp(CMD_ARGV[0], "thumb") == 0)
788 arm->core_state = ARM_STATE_THUMB;
789 }
790
791 command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]);
792
793 return ERROR_OK;
794 }
795
796 COMMAND_HANDLER(handle_arm_disassemble_command)
797 {
798 int retval = ERROR_OK;
799 struct target *target = get_current_target(CMD_CTX);
800
801 if (target == NULL) {
802 LOG_ERROR("No target selected");
803 return ERROR_FAIL;
804 }
805
806 struct arm *arm = target_to_arm(target);
807 uint32_t address;
808 int count = 1;
809 int thumb = 0;
810
811 if (!is_arm(arm)) {
812 command_print(CMD_CTX, "current target isn't an ARM");
813 return ERROR_FAIL;
814 }
815
816 if (arm->core_type == ARM_MODE_THREAD) {
817 /* armv7m is always thumb mode */
818 thumb = 1;
819 }
820
821 switch (CMD_ARGC) {
822 case 3:
823 if (strcmp(CMD_ARGV[2], "thumb") != 0)
824 goto usage;
825 thumb = 1;
826 /* FALL THROUGH */
827 case 2:
828 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
829 /* FALL THROUGH */
830 case 1:
831 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
832 if (address & 0x01) {
833 if (!thumb) {
834 command_print(CMD_CTX, "Disassemble as Thumb");
835 thumb = 1;
836 }
837 address &= ~1;
838 }
839 break;
840 default:
841 usage:
842 count = 0;
843 retval = ERROR_COMMAND_SYNTAX_ERROR;
844 }
845
846 while (count-- > 0) {
847 struct arm_instruction cur_instruction;
848
849 if (thumb) {
850 /* Always use Thumb2 disassembly for best handling
851 * of 32-bit BL/BLX, and to work with newer cores
852 * (some ARMv6, all ARMv7) that use Thumb2.
853 */
854 retval = thumb2_opcode(target, address,
855 &cur_instruction);
856 if (retval != ERROR_OK)
857 break;
858 } else {
859 uint32_t opcode;
860
861 retval = target_read_u32(target, address, &opcode);
862 if (retval != ERROR_OK)
863 break;
864 retval = arm_evaluate_opcode(opcode, address,
865 &cur_instruction) != ERROR_OK;
866 if (retval != ERROR_OK)
867 break;
868 }
869 command_print(CMD_CTX, "%s", cur_instruction.text);
870 address += cur_instruction.instruction_size;
871 }
872
873 return retval;
874 }
875
876 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
877 {
878 struct command_context *context;
879 struct target *target;
880 struct arm *arm;
881 int retval;
882
883 context = current_command_context(interp);
884 assert(context != NULL);
885
886 target = get_current_target(context);
887 if (target == NULL) {
888 LOG_ERROR("%s: no current target", __func__);
889 return JIM_ERR;
890 }
891 if (!target_was_examined(target)) {
892 LOG_ERROR("%s: not yet examined", target_name(target));
893 return JIM_ERR;
894 }
895 arm = target_to_arm(target);
896 if (!is_arm(arm)) {
897 LOG_ERROR("%s: not an ARM", target_name(target));
898 return JIM_ERR;
899 }
900
901 if ((argc < 6) || (argc > 7)) {
902 /* FIXME use the command name to verify # params... */
903 LOG_ERROR("%s: wrong number of arguments", __func__);
904 return JIM_ERR;
905 }
906
907 int cpnum;
908 uint32_t op1;
909 uint32_t op2;
910 uint32_t CRn;
911 uint32_t CRm;
912 uint32_t value;
913 long l;
914
915 /* NOTE: parameter sequence matches ARM instruction set usage:
916 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
917 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
918 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
919 */
920 retval = Jim_GetLong(interp, argv[1], &l);
921 if (retval != JIM_OK)
922 return retval;
923 if (l & ~0xf) {
924 LOG_ERROR("%s: %s %d out of range", __func__,
925 "coprocessor", (int) l);
926 return JIM_ERR;
927 }
928 cpnum = l;
929
930 retval = Jim_GetLong(interp, argv[2], &l);
931 if (retval != JIM_OK)
932 return retval;
933 if (l & ~0x7) {
934 LOG_ERROR("%s: %s %d out of range", __func__,
935 "op1", (int) l);
936 return JIM_ERR;
937 }
938 op1 = l;
939
940 retval = Jim_GetLong(interp, argv[3], &l);
941 if (retval != JIM_OK)
942 return retval;
943 if (l & ~0xf) {
944 LOG_ERROR("%s: %s %d out of range", __func__,
945 "CRn", (int) l);
946 return JIM_ERR;
947 }
948 CRn = l;
949
950 retval = Jim_GetLong(interp, argv[4], &l);
951 if (retval != JIM_OK)
952 return retval;
953 if (l & ~0xf) {
954 LOG_ERROR("%s: %s %d out of range", __func__,
955 "CRm", (int) l);
956 return JIM_ERR;
957 }
958 CRm = l;
959
960 retval = Jim_GetLong(interp, argv[5], &l);
961 if (retval != JIM_OK)
962 return retval;
963 if (l & ~0x7) {
964 LOG_ERROR("%s: %s %d out of range", __func__,
965 "op2", (int) l);
966 return JIM_ERR;
967 }
968 op2 = l;
969
970 value = 0;
971
972 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
973 * that could easily be a typo! Check both...
974 *
975 * FIXME change the call syntax here ... simplest to just pass
976 * the MRC() or MCR() instruction to be executed. That will also
977 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
978 * if that's ever needed.
979 */
980 if (argc == 7) {
981 retval = Jim_GetLong(interp, argv[6], &l);
982 if (retval != JIM_OK)
983 return retval;
984 value = l;
985
986 /* NOTE: parameters reordered! */
987 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
988 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
989 if (retval != ERROR_OK)
990 return JIM_ERR;
991 } else {
992 /* NOTE: parameters reordered! */
993 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
994 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
995 if (retval != ERROR_OK)
996 return JIM_ERR;
997
998 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
999 }
1000
1001 return JIM_OK;
1002 }
1003
1004 COMMAND_HANDLER(handle_arm_semihosting_command)
1005 {
1006 struct target *target = get_current_target(CMD_CTX);
1007
1008 if (target == NULL) {
1009 LOG_ERROR("No target selected");
1010 return ERROR_FAIL;
1011 }
1012
1013 struct arm *arm = target_to_arm(target);
1014
1015 if (!is_arm(arm)) {
1016 command_print(CMD_CTX, "current target isn't an ARM");
1017 return ERROR_FAIL;
1018 }
1019
1020 if (!arm->setup_semihosting) {
1021 command_print(CMD_CTX, "semihosting not supported for current target");
1022 return ERROR_FAIL;
1023 }
1024
1025 if (CMD_ARGC > 0) {
1026 int semihosting;
1027
1028 COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
1029
1030 if (!target_was_examined(target)) {
1031 LOG_ERROR("Target not examined yet");
1032 return ERROR_FAIL;
1033 }
1034
1035 if (arm->setup_semihosting(target, semihosting) != ERROR_OK) {
1036 LOG_ERROR("Failed to Configure semihosting");
1037 return ERROR_FAIL;
1038 }
1039
1040 /* FIXME never let that "catch" be dropped! */
1041 arm->is_semihosting = semihosting;
1042 }
1043
1044 command_print(CMD_CTX, "semihosting is %s",
1045 arm->is_semihosting
1046 ? "enabled" : "disabled");
1047
1048 return ERROR_OK;
1049 }
1050
1051 static const struct command_registration arm_exec_command_handlers[] = {
1052 {
1053 .name = "reg",
1054 .handler = handle_armv4_5_reg_command,
1055 .mode = COMMAND_EXEC,
1056 .help = "display ARM core registers",
1057 .usage = "",
1058 },
1059 {
1060 .name = "core_state",
1061 .handler = handle_armv4_5_core_state_command,
1062 .mode = COMMAND_EXEC,
1063 .usage = "['arm'|'thumb']",
1064 .help = "display/change ARM core state",
1065 },
1066 {
1067 .name = "disassemble",
1068 .handler = handle_arm_disassemble_command,
1069 .mode = COMMAND_EXEC,
1070 .usage = "address [count ['thumb']]",
1071 .help = "disassemble instructions ",
1072 },
1073 {
1074 .name = "mcr",
1075 .mode = COMMAND_EXEC,
1076 .jim_handler = &jim_mcrmrc,
1077 .help = "write coprocessor register",
1078 .usage = "cpnum op1 CRn CRm op2 value",
1079 },
1080 {
1081 .name = "mrc",
1082 .jim_handler = &jim_mcrmrc,
1083 .help = "read coprocessor register",
1084 .usage = "cpnum op1 CRn CRm op2",
1085 },
1086 {
1087 "semihosting",
1088 .handler = handle_arm_semihosting_command,
1089 .mode = COMMAND_EXEC,
1090 .usage = "['enable'|'disable']",
1091 .help = "activate support for semihosting operations",
1092 },
1093
1094 COMMAND_REGISTRATION_DONE
1095 };
1096 const struct command_registration arm_command_handlers[] = {
1097 {
1098 .name = "arm",
1099 .mode = COMMAND_ANY,
1100 .help = "ARM command group",
1101 .usage = "",
1102 .chain = arm_exec_command_handlers,
1103 },
1104 COMMAND_REGISTRATION_DONE
1105 };
1106
1107 int arm_get_gdb_reg_list(struct target *target,
1108 struct reg **reg_list[], int *reg_list_size,
1109 enum target_register_class reg_class)
1110 {
1111 struct arm *arm = target_to_arm(target);
1112 unsigned int i;
1113
1114 if (!is_arm_mode(arm->core_mode)) {
1115 LOG_ERROR("not a valid arm core mode - communication failure?");
1116 return ERROR_FAIL;
1117 }
1118
1119 switch (reg_class) {
1120 case REG_CLASS_GENERAL:
1121 *reg_list_size = 26;
1122 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1123
1124 for (i = 0; i < 16; i++)
1125 (*reg_list)[i] = arm_reg_current(arm, i);
1126
1127 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1128 for (i = 16; i < 24; i++)
1129 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1130 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1131
1132 (*reg_list)[25] = arm->cpsr;
1133
1134 return ERROR_OK;
1135 break;
1136
1137 case REG_CLASS_ALL:
1138 *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
1139 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1140
1141 for (i = 0; i < 16; i++)
1142 (*reg_list)[i] = arm_reg_current(arm, i);
1143
1144 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1145 int reg_index = arm->core_cache->reg_list[i].number;
1146 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1147 && arm->core_type != ARM_MODE_MON))
1148 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1149 }
1150
1151 /* When we supply the target description, there is no need for fake FPA */
1152 for (i = 16; i < 24; i++) {
1153 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1154 (*reg_list)[i]->size = 0;
1155 }
1156 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1157 (*reg_list)[24]->size = 0;
1158
1159 return ERROR_OK;
1160 break;
1161
1162 default:
1163 LOG_ERROR("not a valid register class type in query.");
1164 return ERROR_FAIL;
1165 break;
1166 }
1167 }
1168
1169 /* wait for execution to complete and check exit point */
1170 static int armv4_5_run_algorithm_completion(struct target *target,
1171 uint32_t exit_point,
1172 int timeout_ms,
1173 void *arch_info)
1174 {
1175 int retval;
1176 struct arm *arm = target_to_arm(target);
1177
1178 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1179 if (retval != ERROR_OK)
1180 return retval;
1181 if (target->state != TARGET_HALTED) {
1182 retval = target_halt(target);
1183 if (retval != ERROR_OK)
1184 return retval;
1185 retval = target_wait_state(target, TARGET_HALTED, 500);
1186 if (retval != ERROR_OK)
1187 return retval;
1188 return ERROR_TARGET_TIMEOUT;
1189 }
1190
1191 /* fast exit: ARMv5+ code can use BKPT */
1192 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1193 LOG_WARNING(
1194 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1195 buf_get_u32(arm->pc->value, 0, 32));
1196 return ERROR_TARGET_TIMEOUT;
1197 }
1198
1199 return ERROR_OK;
1200 }
1201
1202 int armv4_5_run_algorithm_inner(struct target *target,
1203 int num_mem_params, struct mem_param *mem_params,
1204 int num_reg_params, struct reg_param *reg_params,
1205 uint32_t entry_point, uint32_t exit_point,
1206 int timeout_ms, void *arch_info,
1207 int (*run_it)(struct target *target, uint32_t exit_point,
1208 int timeout_ms, void *arch_info))
1209 {
1210 struct arm *arm = target_to_arm(target);
1211 struct arm_algorithm *arm_algorithm_info = arch_info;
1212 enum arm_state core_state = arm->core_state;
1213 uint32_t context[17];
1214 uint32_t cpsr;
1215 int exit_breakpoint_size = 0;
1216 int i;
1217 int retval = ERROR_OK;
1218
1219 LOG_DEBUG("Running algorithm");
1220
1221 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1222 LOG_ERROR("current target isn't an ARMV4/5 target");
1223 return ERROR_TARGET_INVALID;
1224 }
1225
1226 if (target->state != TARGET_HALTED) {
1227 LOG_WARNING("target not halted");
1228 return ERROR_TARGET_NOT_HALTED;
1229 }
1230
1231 if (!is_arm_mode(arm->core_mode)) {
1232 LOG_ERROR("not a valid arm core mode - communication failure?");
1233 return ERROR_FAIL;
1234 }
1235
1236 /* armv5 and later can terminate with BKPT instruction; less overhead */
1237 if (!exit_point && arm->is_armv4) {
1238 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1239 return ERROR_FAIL;
1240 }
1241
1242 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1243 * they'll be restored later.
1244 */
1245 for (i = 0; i <= 16; i++) {
1246 struct reg *r;
1247
1248 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1249 arm_algorithm_info->core_mode, i);
1250 if (!r->valid)
1251 arm->read_core_reg(target, r, i,
1252 arm_algorithm_info->core_mode);
1253 context[i] = buf_get_u32(r->value, 0, 32);
1254 }
1255 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1256
1257 for (i = 0; i < num_mem_params; i++) {
1258 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1259 mem_params[i].value);
1260 if (retval != ERROR_OK)
1261 return retval;
1262 }
1263
1264 for (i = 0; i < num_reg_params; i++) {
1265 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1266 if (!reg) {
1267 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1268 return ERROR_COMMAND_SYNTAX_ERROR;
1269 }
1270
1271 if (reg->size != reg_params[i].size) {
1272 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1273 reg_params[i].reg_name);
1274 return ERROR_COMMAND_SYNTAX_ERROR;
1275 }
1276
1277 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1278 if (retval != ERROR_OK)
1279 return retval;
1280 }
1281
1282 arm->core_state = arm_algorithm_info->core_state;
1283 if (arm->core_state == ARM_STATE_ARM)
1284 exit_breakpoint_size = 4;
1285 else if (arm->core_state == ARM_STATE_THUMB)
1286 exit_breakpoint_size = 2;
1287 else {
1288 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1289 return ERROR_COMMAND_SYNTAX_ERROR;
1290 }
1291
1292 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1293 LOG_DEBUG("setting core_mode: 0x%2.2x",
1294 arm_algorithm_info->core_mode);
1295 buf_set_u32(arm->cpsr->value, 0, 5,
1296 arm_algorithm_info->core_mode);
1297 arm->cpsr->dirty = 1;
1298 arm->cpsr->valid = 1;
1299 }
1300
1301 /* terminate using a hardware or (ARMv5+) software breakpoint */
1302 if (exit_point) {
1303 retval = breakpoint_add(target, exit_point,
1304 exit_breakpoint_size, BKPT_HARD);
1305 if (retval != ERROR_OK) {
1306 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1307 return ERROR_TARGET_FAILURE;
1308 }
1309 }
1310
1311 retval = target_resume(target, 0, entry_point, 1, 1);
1312 if (retval != ERROR_OK)
1313 return retval;
1314 retval = run_it(target, exit_point, timeout_ms, arch_info);
1315
1316 if (exit_point)
1317 breakpoint_remove(target, exit_point);
1318
1319 if (retval != ERROR_OK)
1320 return retval;
1321
1322 for (i = 0; i < num_mem_params; i++) {
1323 if (mem_params[i].direction != PARAM_OUT) {
1324 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1325 mem_params[i].size,
1326 mem_params[i].value);
1327 if (retvaltemp != ERROR_OK)
1328 retval = retvaltemp;
1329 }
1330 }
1331
1332 for (i = 0; i < num_reg_params; i++) {
1333 if (reg_params[i].direction != PARAM_OUT) {
1334
1335 struct reg *reg = register_get_by_name(arm->core_cache,
1336 reg_params[i].reg_name,
1337 0);
1338 if (!reg) {
1339 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1340 retval = ERROR_COMMAND_SYNTAX_ERROR;
1341 continue;
1342 }
1343
1344 if (reg->size != reg_params[i].size) {
1345 LOG_ERROR(
1346 "BUG: register '%s' size doesn't match reg_params[i].size",
1347 reg_params[i].reg_name);
1348 retval = ERROR_COMMAND_SYNTAX_ERROR;
1349 continue;
1350 }
1351
1352 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1353 }
1354 }
1355
1356 /* restore everything we saved before (17 or 18 registers) */
1357 for (i = 0; i <= 16; i++) {
1358 uint32_t regvalue;
1359 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1360 arm_algorithm_info->core_mode, i).value, 0, 32);
1361 if (regvalue != context[i]) {
1362 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1363 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1364 arm_algorithm_info->core_mode, i).name, context[i]);
1365 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1366 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1367 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1368 i).valid = 1;
1369 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1370 i).dirty = 1;
1371 }
1372 }
1373
1374 arm_set_cpsr(arm, cpsr);
1375 arm->cpsr->dirty = 1;
1376
1377 arm->core_state = core_state;
1378
1379 return retval;
1380 }
1381
1382 int armv4_5_run_algorithm(struct target *target,
1383 int num_mem_params,
1384 struct mem_param *mem_params,
1385 int num_reg_params,
1386 struct reg_param *reg_params,
1387 uint32_t entry_point,
1388 uint32_t exit_point,
1389 int timeout_ms,
1390 void *arch_info)
1391 {
1392 return armv4_5_run_algorithm_inner(target,
1393 num_mem_params,
1394 mem_params,
1395 num_reg_params,
1396 reg_params,
1397 entry_point,
1398 exit_point,
1399 timeout_ms,
1400 arch_info,
1401 armv4_5_run_algorithm_completion);
1402 }
1403
1404 /**
1405 * Runs ARM code in the target to calculate a CRC32 checksum.
1406 *
1407 */
1408 int arm_checksum_memory(struct target *target,
1409 uint32_t address, uint32_t count, uint32_t *checksum)
1410 {
1411 struct working_area *crc_algorithm;
1412 struct arm_algorithm arm_algo;
1413 struct arm *arm = target_to_arm(target);
1414 struct reg_param reg_params[2];
1415 int retval;
1416 uint32_t i;
1417 uint32_t exit_var = 0;
1418
1419 /* see contrib/loaders/checksum/armv4_5_crc.s for src */
1420
1421 static const uint32_t arm_crc_code[] = {
1422 0xE1A02000, /* mov r2, r0 */
1423 0xE3E00000, /* mov r0, #0xffffffff */
1424 0xE1A03001, /* mov r3, r1 */
1425 0xE3A04000, /* mov r4, #0 */
1426 0xEA00000B, /* b ncomp */
1427 /* nbyte: */
1428 0xE7D21004, /* ldrb r1, [r2, r4] */
1429 0xE59F7030, /* ldr r7, CRC32XOR */
1430 0xE0200C01, /* eor r0, r0, r1, asl 24 */
1431 0xE3A05000, /* mov r5, #0 */
1432 /* loop: */
1433 0xE3500000, /* cmp r0, #0 */
1434 0xE1A06080, /* mov r6, r0, asl #1 */
1435 0xE2855001, /* add r5, r5, #1 */
1436 0xE1A00006, /* mov r0, r6 */
1437 0xB0260007, /* eorlt r0, r6, r7 */
1438 0xE3550008, /* cmp r5, #8 */
1439 0x1AFFFFF8, /* bne loop */
1440 0xE2844001, /* add r4, r4, #1 */
1441 /* ncomp: */
1442 0xE1540003, /* cmp r4, r3 */
1443 0x1AFFFFF1, /* bne nbyte */
1444 /* end: */
1445 0xe1200070, /* bkpt #0 */
1446 /* CRC32XOR: */
1447 0x04C11DB7 /* .word 0x04C11DB7 */
1448 };
1449
1450 retval = target_alloc_working_area(target,
1451 sizeof(arm_crc_code), &crc_algorithm);
1452 if (retval != ERROR_OK)
1453 return retval;
1454
1455 /* convert code into a buffer in target endianness */
1456 for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) {
1457 retval = target_write_u32(target,
1458 crc_algorithm->address + i * sizeof(uint32_t),
1459 arm_crc_code[i]);
1460 if (retval != ERROR_OK)
1461 return retval;
1462 }
1463
1464 arm_algo.common_magic = ARM_COMMON_MAGIC;
1465 arm_algo.core_mode = ARM_MODE_SVC;
1466 arm_algo.core_state = ARM_STATE_ARM;
1467
1468 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1469 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1470
1471 buf_set_u32(reg_params[0].value, 0, 32, address);
1472 buf_set_u32(reg_params[1].value, 0, 32, count);
1473
1474 /* 20 second timeout/megabyte */
1475 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1476
1477 /* armv4 must exit using a hardware breakpoint */
1478 if (arm->is_armv4)
1479 exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
1480
1481 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1482 crc_algorithm->address,
1483 exit_var,
1484 timeout, &arm_algo);
1485 if (retval != ERROR_OK) {
1486 LOG_ERROR("error executing ARM crc algorithm");
1487 destroy_reg_param(&reg_params[0]);
1488 destroy_reg_param(&reg_params[1]);
1489 target_free_working_area(target, crc_algorithm);
1490 return retval;
1491 }
1492
1493 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1494
1495 destroy_reg_param(&reg_params[0]);
1496 destroy_reg_param(&reg_params[1]);
1497
1498 target_free_working_area(target, crc_algorithm);
1499
1500 return ERROR_OK;
1501 }
1502
1503 /**
1504 * Runs ARM code in the target to check whether a memory block holds
1505 * all ones. NOR flash which has been erased, and thus may be written,
1506 * holds all ones.
1507 *
1508 */
1509 int arm_blank_check_memory(struct target *target,
1510 uint32_t address, uint32_t count, uint32_t *blank)
1511 {
1512 struct working_area *check_algorithm;
1513 struct reg_param reg_params[3];
1514 struct arm_algorithm arm_algo;
1515 struct arm *arm = target_to_arm(target);
1516 int retval;
1517 uint32_t i;
1518 uint32_t exit_var = 0;
1519
1520 /* see contrib/loaders/erase_check/armv4_5_erase_check.s for src */
1521
1522 static const uint32_t check_code[] = {
1523 /* loop: */
1524 0xe4d03001, /* ldrb r3, [r0], #1 */
1525 0xe0022003, /* and r2, r2, r3 */
1526 0xe2511001, /* subs r1, r1, #1 */
1527 0x1afffffb, /* bne loop */
1528 /* end: */
1529 0xe1200070, /* bkpt #0 */
1530 };
1531
1532 /* make sure we have a working area */
1533 retval = target_alloc_working_area(target,
1534 sizeof(check_code), &check_algorithm);
1535 if (retval != ERROR_OK)
1536 return retval;
1537
1538 /* convert code into a buffer in target endianness */
1539 for (i = 0; i < ARRAY_SIZE(check_code); i++) {
1540 retval = target_write_u32(target,
1541 check_algorithm->address
1542 + i * sizeof(uint32_t),
1543 check_code[i]);
1544 if (retval != ERROR_OK)
1545 return retval;
1546 }
1547
1548 arm_algo.common_magic = ARM_COMMON_MAGIC;
1549 arm_algo.core_mode = ARM_MODE_SVC;
1550 arm_algo.core_state = ARM_STATE_ARM;
1551
1552 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1553 buf_set_u32(reg_params[0].value, 0, 32, address);
1554
1555 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1556 buf_set_u32(reg_params[1].value, 0, 32, count);
1557
1558 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1559 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
1560
1561 /* armv4 must exit using a hardware breakpoint */
1562 if (arm->is_armv4)
1563 exit_var = check_algorithm->address + sizeof(check_code) - 4;
1564
1565 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1566 check_algorithm->address,
1567 exit_var,
1568 10000, &arm_algo);
1569 if (retval != ERROR_OK) {
1570 destroy_reg_param(&reg_params[0]);
1571 destroy_reg_param(&reg_params[1]);
1572 destroy_reg_param(&reg_params[2]);
1573 target_free_working_area(target, check_algorithm);
1574 return retval;
1575 }
1576
1577 *blank = buf_get_u32(reg_params[2].value, 0, 32);
1578
1579 destroy_reg_param(&reg_params[0]);
1580 destroy_reg_param(&reg_params[1]);
1581 destroy_reg_param(&reg_params[2]);
1582
1583 target_free_working_area(target, check_algorithm);
1584
1585 return ERROR_OK;
1586 }
1587
1588 static int arm_full_context(struct target *target)
1589 {
1590 struct arm *arm = target_to_arm(target);
1591 unsigned num_regs = arm->core_cache->num_regs;
1592 struct reg *reg = arm->core_cache->reg_list;
1593 int retval = ERROR_OK;
1594
1595 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1596 if (reg->valid)
1597 continue;
1598 retval = armv4_5_get_core_reg(reg);
1599 }
1600 return retval;
1601 }
1602
1603 static int arm_default_mrc(struct target *target, int cpnum,
1604 uint32_t op1, uint32_t op2,
1605 uint32_t CRn, uint32_t CRm,
1606 uint32_t *value)
1607 {
1608 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1609 return ERROR_FAIL;
1610 }
1611
1612 static int arm_default_mcr(struct target *target, int cpnum,
1613 uint32_t op1, uint32_t op2,
1614 uint32_t CRn, uint32_t CRm,
1615 uint32_t value)
1616 {
1617 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1618 return ERROR_FAIL;
1619 }
1620
1621 int arm_init_arch_info(struct target *target, struct arm *arm)
1622 {
1623 target->arch_info = arm;
1624 arm->target = target;
1625
1626 arm->common_magic = ARM_COMMON_MAGIC;
1627
1628 /* core_type may be overridden by subtype logic */
1629 if (arm->core_type != ARM_MODE_THREAD) {
1630 arm->core_type = ARM_MODE_ANY;
1631 arm_set_cpsr(arm, ARM_MODE_USR);
1632 }
1633
1634 /* default full_context() has no core-specific optimizations */
1635 if (!arm->full_context && arm->read_core_reg)
1636 arm->full_context = arm_full_context;
1637
1638 if (!arm->mrc)
1639 arm->mrc = arm_default_mrc;
1640 if (!arm->mcr)
1641 arm->mcr = arm_default_mcr;
1642
1643 return ERROR_OK;
1644 }
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