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jtag: clean up TAP state name handling
[openocd.git] / src / flash / davinci_nand.c
blob41c2b20ab1f399f43e164efd8e6adbac96412b17
1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
19
20 /*
21 * DaVinci family NAND controller support for OpenOCD.
22 *
23 * This driver uses hardware ECC (1-bit or 4-bit) unless
24 * the chip is accessed in "raw" mode.
25 */
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "arm_nandio.h"
32
33
34 enum ecc {
35 HWECC1, /* all controllers support 1-bit ECC */
36 HWECC4, /* newer chips also have 4-bit ECC hardware */
37 HWECC4_INFIX, /* avoid this layout, except maybe for boot code */
38 };
39
40 struct davinci_nand {
41 target_t *target;
42
43 uint8_t chipsel; /* chipselect 0..3 == CS2..CS5 */
44 uint8_t eccmode;
45
46 /* Async EMIF controller base */
47 uint32_t aemif;
48
49 /* NAND chip addresses */
50 uint32_t data; /* without CLE or ALE */
51 uint32_t cmd; /* with CLE */
52 uint32_t addr; /* with ALE */
53
54 /* write acceleration */
55 struct arm_nand_data io;
56
57 /* page i/o for the relevant flavor of hardware ECC */
58 int (*read_page)(struct nand_device_s *nand, uint32_t page,
59 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
60 int (*write_page)(struct nand_device_s *nand, uint32_t page,
61 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
62 };
63
64 #define NANDFCR 0x60 /* flash control register */
65 #define NANDFSR 0x64 /* flash status register */
66 #define NANDFECC 0x70 /* 1-bit ECC data, CS0, 1st of 4 */
67 #define NAND4BITECCLOAD 0xbc /* 4-bit ECC, load saved values */
68 #define NAND4BITECC 0xc0 /* 4-bit ECC data, 1st of 4 */
69 #define NANDERRADDR 0xd0 /* 4-bit ECC err addr, 1st of 2 */
70 #define NANDERRVAL 0xd8 /* 4-bit ECC err value, 1st of 2 */
71
72 static int halted(target_t *target, const char *label)
73 {
74 if (target->state == TARGET_HALTED)
75 return true;
76
77 LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
78 return false;
79 }
80
81 static int davinci_register_commands(struct command_context_s *cmd_ctx)
82 {
83 return ERROR_OK;
84 }
85
86 static int davinci_init(struct nand_device_s *nand)
87 {
88 struct davinci_nand *info = nand->controller_priv;
89 target_t *target = info->target;
90 uint32_t nandfcr;
91
92 if (!halted(target, "init"))
93 return ERROR_NAND_OPERATION_FAILED;
94
95 /* We require something else to have configured AEMIF to talk
96 * to NAND chip in this range (including timings and width).
97 */
98 target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
99 if (!(nandfcr & (1 << info->chipsel))) {
100 LOG_ERROR("chip address %08" PRIx32 " not NAND-enabled?", info->data);
101 return ERROR_NAND_OPERATION_FAILED;
102 }
103
104 /* REVISIT verify: AxCR must be in 8-bit mode, since that's all we
105 * tested. 16 bit support should work too; but not with 4-bit ECC.
106 */
107
108 return ERROR_OK;
109 }
110
111 static int davinci_reset(struct nand_device_s *nand)
112 {
113 return ERROR_OK;
114 }
115
116 static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
117 {
118 struct davinci_nand *info = nand->controller_priv;
119 target_t *target = info->target;
120 uint32_t nandfsr;
121
122 /* NOTE: return code is zero/error, else success; not ERROR_* */
123
124 if (!halted(target, "ready"))
125 return 0;
126
127 do {
128 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
129
130 if (nandfsr & 0x01)
131 return 1;
132
133 alive_sleep(1);
134 } while (timeout-- > 0);
135
136 return 0;
137 }
138
139 static int davinci_command(struct nand_device_s *nand, uint8_t command)
140 {
141 struct davinci_nand *info = nand->controller_priv;
142 target_t *target = info->target;
143
144 if (!halted(target, "command"))
145 return ERROR_NAND_OPERATION_FAILED;
146
147 target_write_u8(target, info->cmd, command);
148 return ERROR_OK;
149 }
150
151 static int davinci_address(struct nand_device_s *nand, uint8_t address)
152 {
153 struct davinci_nand *info = nand->controller_priv;
154 target_t *target = info->target;
155
156 if (!halted(target, "address"))
157 return ERROR_NAND_OPERATION_FAILED;
158
159 target_write_u8(target, info->addr, address);
160 return ERROR_OK;
161 }
162
163 static int davinci_write_data(struct nand_device_s *nand, uint16_t data)
164 {
165 struct davinci_nand *info = nand->controller_priv;
166 target_t *target = info->target;
167
168 if (!halted(target, "write_data"))
169 return ERROR_NAND_OPERATION_FAILED;
170
171 target_write_u8(target, info->data, data);
172 return ERROR_OK;
173 }
174
175 static int davinci_read_data(struct nand_device_s *nand, void *data)
176 {
177 struct davinci_nand *info = nand->controller_priv;
178 target_t *target = info->target;
179
180 if (!halted(target, "read_data"))
181 return ERROR_NAND_OPERATION_FAILED;
182
183 target_read_u8(target, info->data, data);
184 return ERROR_OK;
185 }
186
187 /* REVISIT a bit of native code should let block reads be MUCH faster */
188
189 static int davinci_read_block_data(struct nand_device_s *nand,
190 uint8_t *data, int data_size)
191 {
192 struct davinci_nand *info = nand->controller_priv;
193 target_t *target = info->target;
194 uint32_t nfdata = info->data;
195 uint32_t tmp;
196
197 if (!halted(target, "read_block"))
198 return ERROR_NAND_OPERATION_FAILED;
199
200 while (data_size >= 4) {
201 target_read_u32(target, nfdata, &tmp);
202
203 data[0] = tmp;
204 data[1] = tmp >> 8;
205 data[2] = tmp >> 16;
206 data[3] = tmp >> 24;
207
208 data_size -= 4;
209 data += 4;
210 }
211
212 while (data_size > 0) {
213 target_read_u8(target, nfdata, data);
214
215 data_size -= 1;
216 data += 1;
217 }
218
219 return ERROR_OK;
220 }
221
222 static int davinci_write_block_data(struct nand_device_s *nand,
223 uint8_t *data, int data_size)
224 {
225 struct davinci_nand *info = nand->controller_priv;
226 target_t *target = info->target;
227 uint32_t nfdata = info->data;
228 uint32_t tmp;
229 int status;
230
231 if (!halted(target, "write_block"))
232 return ERROR_NAND_OPERATION_FAILED;
233
234 /* try the fast way first */
235 status = arm_nandwrite(&info->io, data, data_size);
236 if (status != ERROR_NAND_NO_BUFFER)
237 return status;
238
239 /* else do it slowly */
240 while (data_size >= 4) {
241 tmp = le_to_h_u32(data);
242 target_write_u32(target, nfdata, tmp);
243
244 data_size -= 4;
245 data += 4;
246 }
247
248 while (data_size > 0) {
249 target_write_u8(target, nfdata, *data);
250
251 data_size -= 1;
252 data += 1;
253 }
254
255 return ERROR_OK;
256 }
257
258 static int davinci_write_page(struct nand_device_s *nand, uint32_t page,
259 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
260 {
261 struct davinci_nand *info = nand->controller_priv;
262 uint8_t *ooballoc = NULL;
263 int status;
264
265 if (!nand->device)
266 return ERROR_NAND_DEVICE_NOT_PROBED;
267 if (!halted(info->target, "write_page"))
268 return ERROR_NAND_OPERATION_FAILED;
269
270 /* Always write both data and OOB ... we are not "raw" I/O! */
271 if (!data) {
272 LOG_ERROR("Missing NAND data; try 'nand raw_access enable'\n");
273 return ERROR_NAND_OPERATION_FAILED;
274 }
275
276 /* If we're not given OOB, write 0xff where we don't write ECC codes. */
277 switch (nand->page_size) {
278 case 512:
279 oob_size = 16;
280 break;
281 case 2048:
282 oob_size = 64;
283 break;
284 case 4096:
285 oob_size = 128;
286 break;
287 default:
288 return ERROR_NAND_OPERATION_FAILED;
289 }
290 if (!oob) {
291 ooballoc = malloc(oob_size);
292 if (!ooballoc)
293 return ERROR_NAND_OPERATION_FAILED;
294 oob = ooballoc;
295 memset(oob, 0x0ff, oob_size);
296 }
297
298 /* REVISIT avoid wasting SRAM: unless nand->use_raw is set,
299 * use 512 byte chunks. Read side support will often want
300 * to include oob_size ...
301 */
302 info->io.chunk_size = nand->page_size;
303
304 status = info->write_page(nand, page, data, data_size, oob, oob_size);
305 free(ooballoc);
306 return status;
307 }
308
309 static int davinci_read_page(struct nand_device_s *nand, uint32_t page,
310 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
311 {
312 struct davinci_nand *info = nand->controller_priv;
313
314 if (!nand->device)
315 return ERROR_NAND_DEVICE_NOT_PROBED;
316 if (!halted(info->target, "read_page"))
317 return ERROR_NAND_OPERATION_FAILED;
318
319 return info->read_page(nand, page, data, data_size, oob, oob_size);
320 }
321
322 static void davinci_write_pagecmd(struct nand_device_s *nand, uint8_t cmd, uint32_t page)
323 {
324 struct davinci_nand *info = nand->controller_priv;
325 target_t *target = info->target;
326 int page3 = nand->address_cycles - (nand->page_size == 512);
327
328 /* write command ({page,otp}x{read,program} */
329 target_write_u8(target, info->cmd, cmd);
330
331 /* column address (beginning-of-page) */
332 target_write_u8(target, info->addr, 0);
333 if (nand->page_size > 512)
334 target_write_u8(target, info->addr, 0);
335
336 /* page address */
337 target_write_u8(target, info->addr, page);
338 target_write_u8(target, info->addr, page >> 8);
339 if (page3)
340 target_write_u8(target, info->addr, page >> 16);
341 if (page3 == 2)
342 target_write_u8(target, info->addr, page >> 24);
343 }
344
345 static int davinci_writepage_tail(struct nand_device_s *nand,
346 uint8_t *oob, uint32_t oob_size)
347 {
348 struct davinci_nand *info = nand->controller_priv;
349 target_t *target = info->target;
350 uint8_t status;
351
352 if (oob_size)
353 davinci_write_block_data(nand, oob, oob_size);
354
355 /* non-cachemode page program */
356 target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
357
358 if (!davinci_nand_ready(nand, 100))
359 return ERROR_NAND_OPERATION_TIMEOUT;
360
361 if (nand_read_status(nand, &status) != ERROR_OK) {
362 LOG_ERROR("couldn't read status");
363 return ERROR_NAND_OPERATION_FAILED;
364 }
365
366 if (status & NAND_STATUS_FAIL) {
367 LOG_ERROR("write operation failed, status: 0x%02x", status);
368 return ERROR_NAND_OPERATION_FAILED;
369 }
370
371 return ERROR_OK;
372 }
373
374 /*
375 * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
376 */
377 static int davinci_write_page_ecc1(struct nand_device_s *nand, uint32_t page,
378 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
379 {
380 unsigned oob_offset;
381 struct davinci_nand *info = nand->controller_priv;
382 target_t *target = info->target;
383 const uint32_t fcr_addr = info->aemif + NANDFCR;
384 const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
385 uint32_t fcr, ecc1;
386
387 /* Write contiguous ECC bytes starting at specified offset.
388 * NOTE: Linux reserves twice as many bytes as we need; and
389 * for 16-bit OOB, those extra bytes are discontiguous.
390 */
391 switch (nand->page_size) {
392 case 512:
393 oob_offset = 0;
394 break;
395 case 2048:
396 oob_offset = 40;
397 break;
398 default:
399 oob_offset = 80;
400 break;
401 }
402
403 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
404
405 /* scrub any old ECC state */
406 target_read_u32(target, ecc1_addr, &ecc1);
407
408 target_read_u32(target, fcr_addr, &fcr);
409 fcr |= 1 << (8 + info->chipsel);
410
411 do {
412 /* set "start csX 1bit ecc" bit */
413 target_write_u32(target, fcr_addr, fcr);
414
415 /* write 512 bytes */
416 davinci_write_block_data(nand, data, 512);
417 data += 512;
418 data_size -= 512;
419
420 /* read the ecc, pack to 3 bytes, and invert so the ecc
421 * in an erased block is correct
422 */
423 target_read_u32(target, ecc1_addr, &ecc1);
424 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
425 ecc1 = ~ecc1;
426
427 /* save correct ECC code into oob data */
428 oob[oob_offset++] = (uint8_t)(ecc1);
429 oob[oob_offset++] = (uint8_t)(ecc1 >> 8);
430 oob[oob_offset++] = (uint8_t)(ecc1 >> 16);
431
432 } while (data_size);
433
434 /* write OOB into spare area */
435 return davinci_writepage_tail(nand, oob, oob_size);
436 }
437
438 /*
439 * Preferred "new style" ECC layout for use with 4-bit ECC. This somewhat
440 * slows down large page reads done with error correction (since the OOB
441 * is read first, so its ECC data can be used incrementally), but the
442 * manufacturer bad block markers are safe. Contrast: old "infix" style.
443 */
444 static int davinci_write_page_ecc4(struct nand_device_s *nand, uint32_t page,
445 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
446 {
447 static const uint8_t ecc512[] = {
448 0, 1, 2, 3, 4, /* 5== mfr badblock */
449 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
450 };
451 static const uint8_t ecc2048[] = {
452 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
453 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
454 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
455 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
456 };
457 static const uint8_t ecc4096[] = {
458 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
459 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
460 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
461 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
462 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
463 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
464 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
465 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
466 };
467
468 struct davinci_nand *info = nand->controller_priv;
469 const uint8_t *l;
470 target_t *target = info->target;
471 const uint32_t fcr_addr = info->aemif + NANDFCR;
472 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
473 uint32_t fcr, ecc4;
474
475 /* Use the same ECC layout Linux uses. For small page chips
476 * it's a bit cramped.
477 *
478 * NOTE: at this writing, 4KB pages have issues in Linux
479 * because they need more than 64 bytes of ECC data, which
480 * the standard ECC logic can't handle.
481 */
482 switch (nand->page_size) {
483 case 512:
484 l = ecc512;
485 break;
486 case 2048:
487 l = ecc2048;
488 break;
489 default:
490 l = ecc4096;
491 break;
492 }
493
494 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
495
496 /* scrub any old ECC state */
497 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
498
499 target_read_u32(target, fcr_addr, &fcr);
500 fcr &= ~(0x03 << 4);
501 fcr |= (1 << 12) | (info->chipsel << 4);
502
503 do {
504 uint32_t raw_ecc[4], *p;
505 int i;
506
507 /* start 4bit ecc on csX */
508 target_write_u32(target, fcr_addr, fcr);
509
510 /* write 512 bytes */
511 davinci_write_block_data(nand, data, 512);
512 data += 512;
513 data_size -= 512;
514
515 /* read the ecc, then save it into 10 bytes in the oob */
516 for (i = 0; i < 4; i++) {
517 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
518 raw_ecc[i] &= 0x03ff03ff;
519 }
520 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
521 oob[*l++] = p[0] & 0xff;
522 oob[*l++] = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
523 oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
524 oob[*l++] = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
525 oob[*l++] = (p[1] >> 18) & 0xff;
526 }
527
528 } while (data_size);
529
530 /* write OOB into spare area */
531 return davinci_writepage_tail(nand, oob, oob_size);
532 }
533
534 /*
535 * "Infix" OOB ... like Linux ECC_HW_SYNDROME. Avoided because it trashes
536 * manufacturer bad block markers, except on small page chips. Once you
537 * write to a page using this scheme, you need specialized code to update
538 * it (code which ignores now-invalid bad block markers).
539 *
540 * This is needed *only* to support older firmware. Older ROM Boot Loaders
541 * need it to read their second stage loader (UBL) into SRAM, but from then
542 * on the whole system can use the cleaner non-infix layouts. Systems with
543 * older second stage loaders (ABL/U-Boot, etc) or other system software
544 * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
545 */
546 static int davinci_write_page_ecc4infix(struct nand_device_s *nand, uint32_t page,
547 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
548 {
549 struct davinci_nand *info = nand->controller_priv;
550 target_t *target = info->target;
551 const uint32_t fcr_addr = info->aemif + NANDFCR;
552 const uint32_t ecc4_addr = info->aemif + NAND4BITECC;
553 uint32_t fcr, ecc4;
554
555 davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
556
557 /* scrub any old ECC state */
558 target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
559
560 target_read_u32(target, fcr_addr, &fcr);
561 fcr &= ~(0x03 << 4);
562 fcr |= (1 << 12) | (info->chipsel << 4);
563
564 do {
565 uint32_t raw_ecc[4], *p;
566 uint8_t *l;
567 int i;
568
569 /* start 4bit ecc on csX */
570 target_write_u32(target, fcr_addr, fcr);
571
572 /* write 512 bytes */
573 davinci_write_block_data(nand, data, 512);
574 data += 512;
575 data_size -= 512;
576
577 /* read the ecc */
578 for (i = 0; i < 4; i++) {
579 target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
580 raw_ecc[i] &= 0x03ff03ff;
581 }
582
583 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
584 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
585 *l++ = p[0] & 0xff;
586 *l++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
587 *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
588 *l++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
589 *l++ = (p[1] >> 18) & 0xff;
590 }
591
592 /* write this "out-of-band" data -- infix */
593 davinci_write_block_data(nand, oob, 16);
594 oob += 16;
595 oob_size -= 16;
596
597 } while (data_size);
598
599 /* the last data and OOB writes included the spare area */
600 return davinci_writepage_tail(nand, NULL, 0);
601 }
602
603 static int davinci_read_page_ecc4infix(struct nand_device_s *nand, uint32_t page,
604 uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
605 {
606 davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
607
608 /* large page devices need a start command */
609 if (nand->page_size > 512)
610 davinci_command(nand, NAND_CMD_READSTART);
611
612 if (!davinci_nand_ready(nand, 100))
613 return ERROR_NAND_OPERATION_TIMEOUT;
614
615 /* NOTE: not bothering to compute and use ECC data for now */
616
617 do {
618 /* write 512 bytes */
619 davinci_read_block_data(nand, data, 512);
620 data += 512;
621 data_size -= 512;
622
623 /* read this "out-of-band" data -- infix */
624 davinci_read_block_data(nand, oob, 16);
625 oob += 16;
626 oob_size -= 16;
627 } while (data_size);
628
629 return ERROR_OK;
630 }
631
632 static int davinci_nand_device_command(struct command_context_s *cmd_ctx,
633 char *cmd, char **argv, int argc,
634 struct nand_device_s *nand)
635 {
636 struct davinci_nand *info;
637 target_t *target;
638 unsigned long chip, aemif;
639 enum ecc eccmode;
640 int chipsel;
641 char *ep;
642
643 /* arguments:
644 * - "davinci"
645 * - target
646 * - nand chip address
647 * - ecc mode
648 * - aemif address
649 * Plus someday, optionally, ALE and CLE masks.
650 */
651 if (argc < 5) {
652 LOG_ERROR("parameters: %s target "
653 "chip_addr hwecc_mode aemif_addr",
654 argv[0]);
655 goto fail;
656 }
657
658 target = get_target(argv[1]);
659 if (!target) {
660 LOG_ERROR("invalid target %s", argv[1]);
661 goto fail;
662 }
663
664 chip = strtoul(argv[2], &ep, 0);
665 if (*ep || chip == 0 || chip == ULONG_MAX) {
666 LOG_ERROR("Invalid NAND chip address %s", argv[2]);
667 goto fail;
668 }
669
670 if (strcmp(argv[3], "hwecc1") == 0)
671 eccmode = HWECC1;
672 else if (strcmp(argv[3], "hwecc4") == 0)
673 eccmode = HWECC4;
674 else if (strcmp(argv[3], "hwecc4_infix") == 0)
675 eccmode = HWECC4_INFIX;
676 else {
677 LOG_ERROR("Invalid ecc mode %s", argv[3]);
678 goto fail;
679 }
680
681 aemif = strtoul(argv[4], &ep, 0);
682 if (*ep || aemif == 0 || aemif == ULONG_MAX) {
683 LOG_ERROR("Invalid AEMIF controller address %s", argv[4]);
684 goto fail;
685 }
686
687 /* REVISIT what we'd *like* to do is look up valid ranges using
688 * target-specific declarations, and not even need to pass the
689 * AEMIF controller address.
690 */
691 if (aemif == 0x01e00000 /* dm6446, dm357 */
692 || aemif == 0x01e10000 /* dm335, dm355 */
693 || aemif == 0x01d10000 /* dm365 */
694 ) {
695 if (chip < 0x02000000 || chip >= 0x0a000000) {
696 LOG_ERROR("NAND address %08lx out of range?", chip);
697 goto fail;
698 }
699 chipsel = (chip - 0x02000000) >> 25;
700 } else {
701 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
702 goto fail;
703 }
704
705 info = calloc(1, sizeof *info);
706 if (info == NULL)
707 goto fail;
708
709 info->target = target;
710 info->eccmode = eccmode;
711 info->chipsel = chipsel;
712 info->aemif = aemif;
713 info->data = chip;
714 info->cmd = chip | 0x10;
715 info->addr = chip | 0x08;
716
717 nand->controller_priv = info;
718
719 info->io.target = target;
720 info->io.data = info->data;
721
722 /* NOTE: for now we don't do any error correction on read.
723 * Nothing else in OpenOCD currently corrects read errors,
724 * and in any case it's *writing* that we care most about.
725 */
726 info->read_page = nand_read_page_raw;
727
728 switch (eccmode) {
729 case HWECC1:
730 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
731 info->write_page = davinci_write_page_ecc1;
732 break;
733 case HWECC4:
734 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
735 info->write_page = davinci_write_page_ecc4;
736 break;
737 case HWECC4_INFIX:
738 /* Same 4-bit ECC HW, with problematic page/ecc layout */
739 info->read_page = davinci_read_page_ecc4infix;
740 info->write_page = davinci_write_page_ecc4infix;
741 break;
742 }
743
744 return ERROR_OK;
745
746 fail:
747 return ERROR_NAND_OPERATION_FAILED;
748 }
749
750 nand_flash_controller_t davinci_nand_controller = {
751 .name = "davinci",
752 .nand_device_command = davinci_nand_device_command,
753 .register_commands = davinci_register_commands,
754 .init = davinci_init,
755 .reset = davinci_reset,
756 .command = davinci_command,
757 .address = davinci_address,
758 .write_data = davinci_write_data,
759 .read_data = davinci_read_data,
760 .write_page = davinci_write_page,
761 .read_page = davinci_read_page,
762 .write_block_data = davinci_write_block_data,
763 .read_block_data = davinci_read_block_data,
764 .nand_ready = davinci_nand_ready,
765 };
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