armv7a: add d-cache virtual address range flush function
[openocd.git] / src / target / nds32_tlb.c
blob58322cf1eaf664e9256af7f7d81bdf4f5aa162c7
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
24 #include "nds32_aice.h"
25 #include "nds32_tlb.h"
27 int nds32_probe_tlb(struct nds32 *nds32, const uint32_t virtual_address,
28 uint32_t *physical_address)
30 struct target *target = nds32->target;
31 struct aice_port_s *aice = target_to_aice(target);
33 return aice_read_tlb(aice, virtual_address, physical_address);
36 struct page_table_walker_info_s page_table_info[PAGE_SIZE_NUM] = {
37 /* 4K page */
38 {0xFFC00000, 20, 0x003FF000, 10, 0x00000FFF, 0xFFFFF000, 0xFFFFF000, 0xFFFFF000},
39 /* 8K page */
40 {0xFF000000, 22, 0x00FFE000, 11, 0x00001FFF, 0xFFFFF000, 0xFFFFE000, 0xFFFFE000},
43 int nds32_walk_page_table(struct nds32 *nds32, const uint32_t virtual_address,
44 uint32_t *physical_address)
46 struct target *target = nds32->target;
47 uint32_t value_mr1;
48 uint32_t load_address;
49 uint32_t L1_page_table_entry;
50 uint32_t L2_page_table_entry;
51 uint32_t page_size_index = nds32->mmu_config.default_min_page_size;
52 struct page_table_walker_info_s *page_table_info_p =
53 &(page_table_info[page_size_index]);
55 /* Read L1 Physical Page Table */
56 nds32_get_mapped_reg(nds32, MR1, &value_mr1);
57 load_address = (value_mr1 & page_table_info_p->L1_base_mask) |
58 ((virtual_address & page_table_info_p->L1_offset_mask) >>
59 page_table_info_p->L1_offset_shift);
60 /* load_address is physical address */
61 nds32_read_buffer(target, load_address, 4, (uint8_t *)&L1_page_table_entry);
63 /* Read L2 Physical Page Table */
64 if (L1_page_table_entry & 0x1) /* L1_PTE not present */
65 return ERROR_FAIL;
67 load_address = (L1_page_table_entry & page_table_info_p->L2_base_mask) |
68 ((virtual_address & page_table_info_p->L2_offset_mask) >>
69 page_table_info_p->L2_offset_shift);
70 /* load_address is physical address */
71 nds32_read_buffer(target, load_address, 4, (uint8_t *)&L2_page_table_entry);
73 if ((L2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */
74 return ERROR_FAIL;
76 *physical_address = (L2_page_table_entry & page_table_info_p->ppn_mask) |
77 (virtual_address & page_table_info_p->va_offset_mask);
79 return ERROR_OK;