1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * Copyright (C) ST-Ericsson SA 2011 michel.jaouen@stericsson.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
20 ***************************************************************************/
26 #include <helper/replacements.h>
29 #include "arm_disassembler.h"
32 #include <helper/binarybuffer.h>
33 #include <helper/command.h>
39 #include "arm_opcodes.h"
41 #include "target_type.h"
43 static void armv7a_show_fault_registers(struct target
*target
)
45 uint32_t dfsr
, ifsr
, dfar
, ifar
;
46 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
47 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
50 retval
= dpm
->prepare(dpm
);
51 if (retval
!= ERROR_OK
)
54 /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
56 /* c5/c0 - {data, instruction} fault status registers */
57 retval
= dpm
->instr_read_data_r0(dpm
,
58 ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
60 if (retval
!= ERROR_OK
)
63 retval
= dpm
->instr_read_data_r0(dpm
,
64 ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
66 if (retval
!= ERROR_OK
)
69 /* c6/c0 - {data, instruction} fault address registers */
70 retval
= dpm
->instr_read_data_r0(dpm
,
71 ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
73 if (retval
!= ERROR_OK
)
76 retval
= dpm
->instr_read_data_r0(dpm
,
77 ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
79 if (retval
!= ERROR_OK
)
82 LOG_USER("Data fault registers DFSR: %8.8" PRIx32
83 ", DFAR: %8.8" PRIx32
, dfsr
, dfar
);
84 LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
85 ", IFAR: %8.8" PRIx32
, ifsr
, ifar
);
88 /* (void) */ dpm
->finish(dpm
);
92 /* retrieve main id register */
93 static int armv7a_read_midr(struct target
*target
)
95 int retval
= ERROR_FAIL
;
96 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
97 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
99 retval
= dpm
->prepare(dpm
);
100 if (retval
!= ERROR_OK
)
102 /* MRC p15,0,<Rd>,c0,c0,0; read main id register*/
104 retval
= dpm
->instr_read_data_r0(dpm
,
105 ARMV4_5_MRC(15, 0, 0, 0, 0, 0),
107 if (retval
!= ERROR_OK
)
110 armv7a
->rev
= (midr
& 0xf);
111 armv7a
->partnum
= (midr
>> 4) & 0xfff;
112 armv7a
->arch
= (midr
>> 16) & 0xf;
113 armv7a
->variant
= (midr
>> 20) & 0xf;
114 armv7a
->implementor
= (midr
>> 24) & 0xff;
115 LOG_INFO("%s rev %" PRIx32
", partnum %" PRIx32
", arch %" PRIx32
116 ", variant %" PRIx32
", implementor %" PRIx32
,
122 armv7a
->implementor
);
129 static int armv7a_read_ttbcr(struct target
*target
)
131 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
132 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
133 uint32_t ttbcr
, ttbcr_n
;
134 int retval
= dpm
->prepare(dpm
);
135 if (retval
!= ERROR_OK
)
137 /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
138 retval
= dpm
->instr_read_data_r0(dpm
,
139 ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
141 if (retval
!= ERROR_OK
)
144 LOG_DEBUG("ttbcr %" PRIx32
, ttbcr
);
146 ttbcr_n
= ttbcr
& 0x7;
147 armv7a
->armv7a_mmu
.ttbcr
= ttbcr
;
148 armv7a
->armv7a_mmu
.cached
= 1;
151 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
152 * document # ARM DDI 0406C
154 armv7a
->armv7a_mmu
.ttbr_range
[0] = 0xffffffff >> ttbcr_n
;
155 armv7a
->armv7a_mmu
.ttbr_range
[1] = 0xffffffff;
156 armv7a
->armv7a_mmu
.ttbr_mask
[0] = 0xffffffff << (14 - ttbcr_n
);
157 armv7a
->armv7a_mmu
.ttbr_mask
[1] = 0xffffffff << 14;
158 armv7a
->armv7a_mmu
.cached
= 1;
160 retval
= armv7a_read_midr(target
);
161 if (retval
!= ERROR_OK
)
164 /* FIXME: why this special case based on part number? */
165 if ((armv7a
->partnum
& 0xf) == 0) {
166 /* ARM DDI 0344H , ARM DDI 0407F */
167 armv7a
->armv7a_mmu
.ttbr_mask
[0] = 7 << (32 - ttbcr_n
);
170 LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32
" ttbr1_mask %" PRIx32
,
171 (ttbcr_n
!= 0) ? "used" : "not used",
172 armv7a
->armv7a_mmu
.ttbr_mask
[0],
173 armv7a
->armv7a_mmu
.ttbr_mask
[1]);
175 /* FIXME: default is hard coded LINUX border */
176 armv7a
->armv7a_mmu
.os_border
= 0xc0000000;
178 LOG_INFO("SVC access above %" PRIx32
,
179 armv7a
->armv7a_mmu
.ttbr_range
[0] + 1);
180 armv7a
->armv7a_mmu
.os_border
= armv7a
->armv7a_mmu
.ttbr_range
[0] + 1;
187 /* method adapted to cortex A : reused arm v4 v5 method*/
188 int armv7a_mmu_translate_va(struct target
*target
, uint32_t va
, uint32_t *val
)
190 uint32_t first_lvl_descriptor
= 0x0;
191 uint32_t second_lvl_descriptor
= 0x0;
193 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
194 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
195 uint32_t ttbidx
= 0; /* default to ttbr0 */
201 retval
= dpm
->prepare(dpm
);
202 if (retval
!= ERROR_OK
)
205 /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
206 retval
= dpm
->instr_read_data_r0(dpm
,
207 ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
209 if (retval
!= ERROR_OK
)
212 /* if ttbcr has changed or was not read before, re-read the information */
213 if ((armv7a
->armv7a_mmu
.cached
== 0) ||
214 (armv7a
->armv7a_mmu
.ttbcr
!= ttbcr
)) {
215 armv7a_read_ttbcr(target
);
218 /* if va is above the range handled by ttbr0, select ttbr1 */
219 if (va
> armv7a
->armv7a_mmu
.ttbr_range
[0]) {
223 /* MRC p15,0,<Rt>,c2,c0,ttbidx */
224 retval
= dpm
->instr_read_data_r0(dpm
,
225 ARMV4_5_MRC(15, 0, 0, 2, 0, ttbidx
),
227 if (retval
!= ERROR_OK
)
230 ttb_mask
= armv7a
->armv7a_mmu
.ttbr_mask
[ttbidx
];
231 va_mask
= 0xfff00000 & armv7a
->armv7a_mmu
.ttbr_range
[ttbidx
];
233 LOG_DEBUG("ttb_mask %" PRIx32
" va_mask %" PRIx32
" ttbidx %i",
234 ttb_mask
, va_mask
, ttbidx
);
235 retval
= armv7a
->armv7a_mmu
.read_physical_memory(target
,
236 (ttb
& ttb_mask
) | ((va
& va_mask
) >> 18),
237 4, 1, (uint8_t *)&first_lvl_descriptor
);
238 if (retval
!= ERROR_OK
)
240 first_lvl_descriptor
= target_buffer_get_u32(target
, (uint8_t *)
241 &first_lvl_descriptor
);
242 /* reuse armv4_5 piece of code, specific armv7a changes may come later */
243 LOG_DEBUG("1st lvl desc: %8.8" PRIx32
"", first_lvl_descriptor
);
245 if ((first_lvl_descriptor
& 0x3) == 0) {
246 LOG_ERROR("Address translation failure");
247 return ERROR_TARGET_TRANSLATION_FAULT
;
251 if ((first_lvl_descriptor
& 0x40002) == 2) {
252 /* section descriptor */
253 *val
= (first_lvl_descriptor
& 0xfff00000) | (va
& 0x000fffff);
255 } else if ((first_lvl_descriptor
& 0x40002) == 0x40002) {
256 /* supersection descriptor */
257 if (first_lvl_descriptor
& 0x00f001e0) {
258 LOG_ERROR("Physical address does not fit into 32 bits");
259 return ERROR_TARGET_TRANSLATION_FAULT
;
261 *val
= (first_lvl_descriptor
& 0xff000000) | (va
& 0x00ffffff);
266 retval
= armv7a
->armv7a_mmu
.read_physical_memory(target
,
267 (first_lvl_descriptor
& 0xfffffc00) | ((va
& 0x000ff000) >> 10),
268 4, 1, (uint8_t *)&second_lvl_descriptor
);
269 if (retval
!= ERROR_OK
)
272 second_lvl_descriptor
= target_buffer_get_u32(target
, (uint8_t *)
273 &second_lvl_descriptor
);
275 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32
"", second_lvl_descriptor
);
277 if ((second_lvl_descriptor
& 0x3) == 0) {
278 LOG_ERROR("Address translation failure");
279 return ERROR_TARGET_TRANSLATION_FAULT
;
282 if ((second_lvl_descriptor
& 0x3) == 1) {
283 /* large page descriptor */
284 *val
= (second_lvl_descriptor
& 0xffff0000) | (va
& 0x0000ffff);
286 /* small page descriptor */
287 *val
= (second_lvl_descriptor
& 0xfffff000) | (va
& 0x00000fff);
296 /* V7 method VA TO PA */
297 int armv7a_mmu_translate_va_pa(struct target
*target
, uint32_t va
,
298 uint32_t *val
, int meminfo
)
300 int retval
= ERROR_FAIL
;
301 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
302 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
303 uint32_t virt
= va
& ~0xfff;
304 uint32_t NOS
, NS
, INNER
, OUTER
;
306 retval
= dpm
->prepare(dpm
);
307 if (retval
!= ERROR_OK
)
309 /* mmu must be enable in order to get a correct translation
310 * use VA to PA CP15 register for conversion */
311 retval
= dpm
->instr_write_data_r0(dpm
,
312 ARMV4_5_MCR(15, 0, 0, 7, 8, 0),
314 if (retval
!= ERROR_OK
)
316 retval
= dpm
->instr_read_data_r0(dpm
,
317 ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
319 /* decode memory attribute */
320 NOS
= (*val
>> 10) & 1; /* Not Outer shareable */
321 NS
= (*val
>> 9) & 1; /* Non secure */
322 INNER
= (*val
>> 4) & 0x7;
323 OUTER
= (*val
>> 2) & 0x3;
325 if (retval
!= ERROR_OK
)
327 *val
= (*val
& ~0xfff) + (va
& 0xfff);
329 LOG_WARNING("virt = phys : MMU disable !!");
331 LOG_INFO("%" PRIx32
" : %" PRIx32
" %s outer shareable %s secured",
333 NOS
== 1 ? "not" : " ",
334 NS
== 1 ? "not" : "");
337 LOG_INFO("outer: Non-Cacheable");
340 LOG_INFO("outer: Write-Back, Write-Allocate");
343 LOG_INFO("outer: Write-Through, No Write-Allocate");
346 LOG_INFO("outer: Write-Back, no Write-Allocate");
351 LOG_INFO("inner: Non-Cacheable");
354 LOG_INFO("inner: Strongly-ordered");
357 LOG_INFO("inner: Device");
360 LOG_INFO("inner: Write-Back, Write-Allocate");
363 LOG_INFO("inner: Write-Through");
366 LOG_INFO("inner: Write-Back, no Write-Allocate");
369 LOG_INFO("inner: %" PRIx32
" ???", INNER
);
379 /* FIXME: remove it */
380 static int armv7a_l2x_cache_init(struct target
*target
, uint32_t base
, uint32_t way
)
382 struct armv7a_l2x_cache
*l2x_cache
;
383 struct target_list
*head
= target
->head
;
386 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
387 l2x_cache
= calloc(1, sizeof(struct armv7a_l2x_cache
));
388 l2x_cache
->base
= base
;
389 l2x_cache
->way
= way
;
390 /*LOG_INFO("cache l2 initialized base %x way %d",
391 l2x_cache->base,l2x_cache->way);*/
392 if (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
)
393 LOG_INFO("outer cache already initialized\n");
394 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= l2x_cache
;
395 /* initialize all target in this cluster (smp target)
396 * l2 cache must be configured after smp declaration */
397 while (head
!= (struct target_list
*)NULL
) {
399 if (curr
!= target
) {
400 armv7a
= target_to_armv7a(curr
);
401 if (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
)
402 LOG_ERROR("smp target : outer cache already initialized\n");
403 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= l2x_cache
;
410 /* FIXME: remove it */
411 COMMAND_HANDLER(handle_cache_l2x
)
413 struct target
*target
= get_current_target(CMD_CTX
);
417 return ERROR_COMMAND_SYNTAX_ERROR
;
419 /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
420 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], base
);
421 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], way
);
423 /* AP address is in bits 31:24 of DP_SELECT */
424 armv7a_l2x_cache_init(target
, base
, way
);
429 int armv7a_handle_cache_info_command(struct command_context
*cmd_ctx
,
430 struct armv7a_cache_common
*armv7a_cache
)
432 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
433 (armv7a_cache
->outer_cache
);
437 if (armv7a_cache
->info
== -1) {
438 command_print(cmd_ctx
, "cache not yet identified");
442 for (cl
= 0; cl
< armv7a_cache
->loc
; cl
++) {
443 struct armv7a_arch_cache
*arch
= &(armv7a_cache
->arch
[cl
]);
445 if (arch
->ctype
& 1) {
446 command_print(cmd_ctx
,
447 "L%d I-Cache: linelen %" PRIi32
448 ", associativity %" PRIi32
450 ", cachesize %" PRId32
" KBytes",
452 arch
->i_size
.linelen
,
453 arch
->i_size
.associativity
,
455 arch
->i_size
.cachesize
);
458 if (arch
->ctype
>= 2) {
459 command_print(cmd_ctx
,
460 "L%d D-Cache: linelen %" PRIi32
461 ", associativity %" PRIi32
463 ", cachesize %" PRId32
" KBytes",
465 arch
->d_u_size
.linelen
,
466 arch
->d_u_size
.associativity
,
467 arch
->d_u_size
.nsets
,
468 arch
->d_u_size
.cachesize
);
472 if (l2x_cache
!= NULL
)
473 command_print(cmd_ctx
, "Outer unified cache Base Address 0x%" PRIx32
", %" PRId32
" ways",
474 l2x_cache
->base
, l2x_cache
->way
);
479 /* retrieve core id cluster id */
480 static int armv7a_read_mpidr(struct target
*target
)
482 int retval
= ERROR_FAIL
;
483 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
484 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
486 retval
= dpm
->prepare(dpm
);
487 if (retval
!= ERROR_OK
)
489 /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
491 retval
= dpm
->instr_read_data_r0(dpm
,
492 ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
494 if (retval
!= ERROR_OK
)
497 /* ARMv7R uses a different format for MPIDR.
498 * When configured uniprocessor (most R cores) it reads as 0.
499 * This will need to be implemented for multiprocessor ARMv7R cores. */
500 if (armv7a
->is_armv7r
) {
502 LOG_ERROR("MPIDR nonzero in ARMv7-R target");
507 armv7a
->multi_processor_system
= (mpidr
>> 30) & 1;
508 armv7a
->cluster_id
= (mpidr
>> 8) & 0xf;
509 armv7a
->cpu_id
= mpidr
& 0x3;
510 LOG_INFO("%s cluster %x core %x %s", target_name(target
),
513 armv7a
->multi_processor_system
== 0 ? "multi core" : "mono core");
516 LOG_ERROR("MPIDR not in multiprocessor format");
525 static int get_cache_info(struct arm_dpm
*dpm
, int cl
, int ct
, uint32_t *cache_reg
)
527 int retval
= ERROR_OK
;
529 /* select cache level */
530 retval
= dpm
->instr_write_data_r0(dpm
,
531 ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
532 (cl
<< 1) | (ct
== 1 ? 1 : 0));
533 if (retval
!= ERROR_OK
)
536 retval
= dpm
->instr_read_data_r0(dpm
,
537 ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
543 static struct armv7a_cachesize
decode_cache_reg(uint32_t cache_reg
)
545 struct armv7a_cachesize size
;
548 size
.linelen
= 16 << (cache_reg
& 0x7);
549 size
.associativity
= ((cache_reg
>> 3) & 0x3ff) + 1;
550 size
.nsets
= ((cache_reg
>> 13) & 0x7fff) + 1;
551 size
.cachesize
= size
.linelen
* size
.associativity
* size
.nsets
/ 1024;
553 /* compute info for set way operation on cache */
554 size
.index_shift
= (cache_reg
& 0x7) + 4;
555 size
.index
= (cache_reg
>> 13) & 0x7fff;
556 size
.way
= ((cache_reg
>> 3) & 0x3ff);
558 while (((size
.way
<< i
) & 0x80000000) == 0)
565 int armv7a_identify_cache(struct target
*target
)
567 /* read cache descriptor */
568 int retval
= ERROR_FAIL
;
569 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
570 struct arm_dpm
*dpm
= armv7a
->arm
.dpm
;
571 uint32_t csselr
, clidr
, ctr
;
574 struct armv7a_cache_common
*cache
=
575 &(armv7a
->armv7a_mmu
.armv7a_cache
);
577 if (!armv7a
->is_armv7r
)
578 armv7a_read_ttbcr(target
);
580 retval
= dpm
->prepare(dpm
);
581 if (retval
!= ERROR_OK
)
585 * mrc p15, 0, r0, c0, c0, 1 @ read ctr */
586 retval
= dpm
->instr_read_data_r0(dpm
,
587 ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
589 if (retval
!= ERROR_OK
)
592 cache
->iminline
= 4UL << (ctr
& 0xf);
593 cache
->dminline
= 4UL << ((ctr
& 0xf0000) >> 16);
594 LOG_DEBUG("ctr %" PRIx32
" ctr.iminline %" PRId32
" ctr.dminline %" PRId32
,
595 ctr
, cache
->iminline
, cache
->dminline
);
598 * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
599 retval
= dpm
->instr_read_data_r0(dpm
,
600 ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
602 if (retval
!= ERROR_OK
)
605 cache
->loc
= (clidr
& 0x7000000) >> 24;
606 LOG_DEBUG("Number of cache levels to PoC %" PRId32
, cache
->loc
);
608 /* retrieve selected cache for later restore
609 * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
610 retval
= dpm
->instr_read_data_r0(dpm
,
611 ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
613 if (retval
!= ERROR_OK
)
616 /* retrieve all available inner caches */
617 for (cl
= 0; cl
< cache
->loc
; clidr
>>= 3, cl
++) {
619 /* isolate cache type at current level */
622 /* skip reserved values */
623 if (ctype
> CACHE_LEVEL_HAS_UNIFIED_CACHE
)
626 /* separate d or unified d/i cache at this level ? */
627 if (ctype
& (CACHE_LEVEL_HAS_UNIFIED_CACHE
| CACHE_LEVEL_HAS_D_CACHE
)) {
628 /* retrieve d-cache info */
629 retval
= get_cache_info(dpm
, cl
, 0, &cache_reg
);
630 if (retval
!= ERROR_OK
)
632 cache
->arch
[cl
].d_u_size
= decode_cache_reg(cache_reg
);
634 LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
635 cache
->arch
[cl
].d_u_size
.index
,
636 cache
->arch
[cl
].d_u_size
.index_shift
,
637 cache
->arch
[cl
].d_u_size
.way
,
638 cache
->arch
[cl
].d_u_size
.way_shift
);
640 LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
641 cache
->arch
[cl
].d_u_size
.linelen
,
642 cache
->arch
[cl
].d_u_size
.cachesize
,
643 cache
->arch
[cl
].d_u_size
.associativity
);
646 /* separate i-cache at this level ? */
647 if (ctype
& CACHE_LEVEL_HAS_I_CACHE
) {
648 /* retrieve i-cache info */
649 retval
= get_cache_info(dpm
, cl
, 1, &cache_reg
);
650 if (retval
!= ERROR_OK
)
652 cache
->arch
[cl
].i_size
= decode_cache_reg(cache_reg
);
654 LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
655 cache
->arch
[cl
].i_size
.index
,
656 cache
->arch
[cl
].i_size
.index_shift
,
657 cache
->arch
[cl
].i_size
.way
,
658 cache
->arch
[cl
].i_size
.way_shift
);
660 LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
661 cache
->arch
[cl
].i_size
.linelen
,
662 cache
->arch
[cl
].i_size
.cachesize
,
663 cache
->arch
[cl
].i_size
.associativity
);
666 cache
->arch
[cl
].ctype
= ctype
;
669 /* restore selected cache */
670 dpm
->instr_write_data_r0(dpm
,
671 ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
674 if (retval
!= ERROR_OK
)
677 /* if no l2 cache initialize l1 data cache flush function function */
678 if (armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache
== NULL
) {
679 armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache
=
680 armv7a_cache_auto_flush_all_data
;
683 armv7a
->armv7a_mmu
.armv7a_cache
.info
= 1;
686 armv7a_read_mpidr(target
);
691 int armv7a_init_arch_info(struct target
*target
, struct armv7a_common
*armv7a
)
693 struct arm
*arm
= &armv7a
->arm
;
694 arm
->arch_info
= armv7a
;
695 target
->arch_info
= &armv7a
->arm
;
696 /* target is useful in all function arm v4 5 compatible */
697 armv7a
->arm
.target
= target
;
698 armv7a
->arm
.common_magic
= ARM_COMMON_MAGIC
;
699 armv7a
->common_magic
= ARMV7_COMMON_MAGIC
;
700 armv7a
->armv7a_mmu
.armv7a_cache
.info
= -1;
701 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= NULL
;
702 armv7a
->armv7a_mmu
.armv7a_cache
.flush_all_data_cache
= NULL
;
703 armv7a
->armv7a_mmu
.armv7a_cache
.auto_cache_enabled
= 1;
707 int armv7a_arch_state(struct target
*target
)
709 static const char *state
[] = {
710 "disabled", "enabled"
713 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
714 struct arm
*arm
= &armv7a
->arm
;
716 if (armv7a
->common_magic
!= ARMV7_COMMON_MAGIC
) {
717 LOG_ERROR("BUG: called for a non-ARMv7A target");
718 return ERROR_COMMAND_SYNTAX_ERROR
;
721 arm_arch_state(target
);
723 if (armv7a
->is_armv7r
) {
724 LOG_USER("D-Cache: %s, I-Cache: %s",
725 state
[armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
],
726 state
[armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
]);
728 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
729 state
[armv7a
->armv7a_mmu
.mmu_enabled
],
730 state
[armv7a
->armv7a_mmu
.armv7a_cache
.d_u_cache_enabled
],
731 state
[armv7a
->armv7a_mmu
.armv7a_cache
.i_cache_enabled
]);
734 if (arm
->core_mode
== ARM_MODE_ABT
)
735 armv7a_show_fault_registers(target
);
736 if (target
->debug_reason
== DBG_REASON_WATCHPOINT
)
737 LOG_USER("Watchpoint triggered at PC %#08x",
738 (unsigned) armv7a
->dpm
.wp_pc
);
743 static const struct command_registration l2_cache_commands
[] = {
746 .handler
= handle_cache_l2x
,
747 .mode
= COMMAND_EXEC
,
748 .help
= "configure l2x cache "
750 .usage
= "[base_addr] [number_of_way]",
752 COMMAND_REGISTRATION_DONE
756 const struct command_registration l2x_cache_command_handlers
[] = {
758 .name
= "cache_config",
759 .mode
= COMMAND_EXEC
,
760 .help
= "cache configuration for a target",
762 .chain
= l2_cache_commands
,
764 COMMAND_REGISTRATION_DONE
767 const struct command_registration armv7a_command_handlers
[] = {
769 .chain
= dap_command_handlers
,
772 .chain
= l2x_cache_command_handlers
,
775 .chain
= arm7a_cache_command_handlers
,
777 COMMAND_REGISTRATION_DONE