1 /***************************************************************************
2 * Copyright (C) 2016 by Matthias Welwarsky *
3 * matthias.welwarsky@sysgo.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include "armv8_cache.h"
24 #include "armv8_dpm.h"
25 #include "armv8_opcodes.h"
27 /* CLIDR cache types */
28 #define CACHE_LEVEL_HAS_UNIFIED_CACHE 0x4
29 #define CACHE_LEVEL_HAS_D_CACHE 0x2
30 #define CACHE_LEVEL_HAS_I_CACHE 0x1
32 static int armv8_d_cache_sanity_check(struct armv8_common
*armv8
)
34 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
36 if (armv8_cache
->d_u_cache_enabled
)
39 return ERROR_TARGET_INVALID
;
42 static int armv8_i_cache_sanity_check(struct armv8_common
*armv8
)
44 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
46 if (armv8_cache
->i_cache_enabled
)
49 return ERROR_TARGET_INVALID
;
52 static int armv8_cache_d_inner_flush_level(struct armv8_common
*armv8
, struct armv8_cachesize
*size
, int cl
)
54 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
55 int retval
= ERROR_OK
;
56 int32_t c_way
, c_index
= size
->index
;
58 LOG_DEBUG("cl %" PRId32
, cl
);
62 uint32_t value
= (c_index
<< size
->index_shift
)
63 | (c_way
<< size
->way_shift
) | (cl
<< 1);
65 * DC CISW - Clean and invalidate data cache
68 retval
= dpm
->instr_write_data_r0(dpm
,
69 armv8_opcode(armv8
, ARMV8_OPC_DCCISW
), value
);
70 if (retval
!= ERROR_OK
)
75 } while (c_index
>= 0);
81 static int armv8_cache_d_inner_clean_inval_all(struct armv8_common
*armv8
)
83 struct armv8_cache_common
*cache
= &(armv8
->armv8_mmu
.armv8_cache
);
84 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
88 retval
= armv8_d_cache_sanity_check(armv8
);
89 if (retval
!= ERROR_OK
)
92 retval
= dpm
->prepare(dpm
);
93 if (retval
!= ERROR_OK
)
96 for (cl
= 0; cl
< cache
->loc
; cl
++) {
97 /* skip i-only caches */
98 if (cache
->arch
[cl
].ctype
< CACHE_LEVEL_HAS_D_CACHE
)
101 armv8_cache_d_inner_flush_level(armv8
, &cache
->arch
[cl
].d_u_size
, cl
);
104 retval
= dpm
->finish(dpm
);
108 LOG_ERROR("clean invalidate failed");
114 int armv8_cache_d_inner_flush_virt(struct armv8_common
*armv8
, target_addr_t va
, size_t size
)
116 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
117 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
118 uint64_t linelen
= armv8_cache
->dminline
;
119 target_addr_t va_line
, va_end
;
122 retval
= armv8_d_cache_sanity_check(armv8
);
123 if (retval
!= ERROR_OK
)
126 retval
= dpm
->prepare(dpm
);
127 if (retval
!= ERROR_OK
)
130 va_line
= va
& (-linelen
);
133 while (va_line
< va_end
) {
135 /* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
136 retval
= dpm
->instr_write_data_r0_64(dpm
,
137 armv8_opcode(armv8
, ARMV8_OPC_DCCIVAC
), va_line
);
138 if (retval
!= ERROR_OK
)
147 LOG_ERROR("d-cache invalidate failed");
153 int armv8_cache_i_inner_inval_virt(struct armv8_common
*armv8
, target_addr_t va
, size_t size
)
155 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
156 struct armv8_cache_common
*armv8_cache
= &armv8
->armv8_mmu
.armv8_cache
;
157 uint64_t linelen
= armv8_cache
->iminline
;
158 target_addr_t va_line
, va_end
;
161 retval
= armv8_i_cache_sanity_check(armv8
);
162 if (retval
!= ERROR_OK
)
165 retval
= dpm
->prepare(dpm
);
166 if (retval
!= ERROR_OK
)
169 va_line
= va
& (-linelen
);
172 while (va_line
< va_end
) {
173 /* IC IVAU - Invalidate instruction cache by VA to PoU. */
174 retval
= dpm
->instr_write_data_r0_64(dpm
,
175 armv8_opcode(armv8
, ARMV8_OPC_ICIVAU
), va_line
);
176 if (retval
!= ERROR_OK
)
185 LOG_ERROR("d-cache invalidate failed");
191 static int armv8_handle_inner_cache_info_command(struct command_invocation
*cmd
,
192 struct armv8_cache_common
*armv8_cache
)
196 if (armv8_cache
->info
== -1) {
197 command_print(cmd
, "cache not yet identified");
201 for (cl
= 0; cl
< armv8_cache
->loc
; cl
++) {
202 struct armv8_arch_cache
*arch
= &(armv8_cache
->arch
[cl
]);
204 if (arch
->ctype
& 1) {
206 "L%d I-Cache: linelen %" PRIu32
207 ", associativity %" PRIu32
209 ", cachesize %" PRIu32
" KBytes",
211 arch
->i_size
.linelen
,
212 arch
->i_size
.associativity
,
214 arch
->i_size
.cachesize
);
217 if (arch
->ctype
>= 2) {
219 "L%d D-Cache: linelen %" PRIu32
220 ", associativity %" PRIu32
222 ", cachesize %" PRIu32
" KBytes",
224 arch
->d_u_size
.linelen
,
225 arch
->d_u_size
.associativity
,
226 arch
->d_u_size
.nsets
,
227 arch
->d_u_size
.cachesize
);
234 static int _armv8_flush_all_data(struct target
*target
)
236 return armv8_cache_d_inner_clean_inval_all(target_to_armv8(target
));
239 static int armv8_flush_all_data(struct target
*target
)
241 int retval
= ERROR_FAIL
;
242 /* check that armv8_cache is correctly identify */
243 struct armv8_common
*armv8
= target_to_armv8(target
);
244 if (armv8
->armv8_mmu
.armv8_cache
.info
== -1) {
245 LOG_ERROR("trying to flush un-identified cache");
250 /* look if all the other target have been flushed in order to flush level
252 struct target_list
*head
;
257 if (curr
->state
== TARGET_HALTED
) {
258 LOG_INFO("Wait flushing data l1 on core %" PRId32
, curr
->coreid
);
259 retval
= _armv8_flush_all_data(curr
);
264 retval
= _armv8_flush_all_data(target
);
268 static int get_cache_info(struct arm_dpm
*dpm
, int cl
, int ct
, uint32_t *cache_reg
)
270 struct armv8_common
*armv8
= dpm
->arm
->arch_info
;
271 int retval
= ERROR_OK
;
273 /* select cache level */
274 retval
= dpm
->instr_write_data_r0(dpm
,
275 armv8_opcode(armv8
, WRITE_REG_CSSELR
),
276 (cl
<< 1) | (ct
== 1 ? 1 : 0));
277 if (retval
!= ERROR_OK
)
280 retval
= dpm
->instr_read_data_r0(dpm
,
281 armv8_opcode(armv8
, READ_REG_CCSIDR
),
287 static struct armv8_cachesize
decode_cache_reg(uint32_t cache_reg
)
289 struct armv8_cachesize size
;
292 size
.linelen
= 16 << (cache_reg
& 0x7);
293 size
.associativity
= ((cache_reg
>> 3) & 0x3ff) + 1;
294 size
.nsets
= ((cache_reg
>> 13) & 0x7fff) + 1;
295 size
.cachesize
= size
.linelen
* size
.associativity
* size
.nsets
/ 1024;
297 /* compute info for set way operation on cache */
298 size
.index_shift
= (cache_reg
& 0x7) + 4;
299 size
.index
= (cache_reg
>> 13) & 0x7fff;
300 size
.way
= ((cache_reg
>> 3) & 0x3ff);
302 while (((size
.way
<< i
) & 0x80000000) == 0)
309 int armv8_identify_cache(struct armv8_common
*armv8
)
311 /* read cache descriptor */
312 int retval
= ERROR_FAIL
;
313 struct arm
*arm
= &armv8
->arm
;
314 struct arm_dpm
*dpm
= armv8
->arm
.dpm
;
315 uint32_t csselr
, clidr
, ctr
;
318 struct armv8_cache_common
*cache
= &(armv8
->armv8_mmu
.armv8_cache
);
320 retval
= dpm
->prepare(dpm
);
321 if (retval
!= ERROR_OK
)
324 /* check if we're in an unprivileged mode */
325 if (armv8_curel_from_core_mode(arm
->core_mode
) < SYSTEM_CUREL_EL1
) {
326 retval
= armv8_dpm_modeswitch(dpm
, ARMV8_64_EL1H
);
327 if (retval
!= ERROR_OK
)
332 retval
= dpm
->instr_read_data_r0(dpm
,
333 armv8_opcode(armv8
, READ_REG_CTR
), &ctr
);
334 if (retval
!= ERROR_OK
)
337 cache
->iminline
= 4UL << (ctr
& 0xf);
338 cache
->dminline
= 4UL << ((ctr
& 0xf0000) >> 16);
339 LOG_DEBUG("ctr %" PRIx32
" ctr.iminline %" PRIu32
" ctr.dminline %" PRIu32
,
340 ctr
, cache
->iminline
, cache
->dminline
);
343 retval
= dpm
->instr_read_data_r0(dpm
,
344 armv8_opcode(armv8
, READ_REG_CLIDR
), &clidr
);
345 if (retval
!= ERROR_OK
)
348 cache
->loc
= (clidr
& 0x7000000) >> 24;
349 LOG_DEBUG("Number of cache levels to PoC %" PRId32
, cache
->loc
);
351 /* retrieve selected cache for later restore
352 * MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
353 retval
= dpm
->instr_read_data_r0(dpm
,
354 armv8_opcode(armv8
, READ_REG_CSSELR
), &csselr
);
355 if (retval
!= ERROR_OK
)
358 /* retrieve all available inner caches */
359 for (cl
= 0; cl
< cache
->loc
; clidr
>>= 3, cl
++) {
361 /* isolate cache type at current level */
364 /* skip reserved values */
365 if (ctype
> CACHE_LEVEL_HAS_UNIFIED_CACHE
)
368 /* separate d or unified d/i cache at this level ? */
369 if (ctype
& (CACHE_LEVEL_HAS_UNIFIED_CACHE
| CACHE_LEVEL_HAS_D_CACHE
)) {
370 /* retrieve d-cache info */
371 retval
= get_cache_info(dpm
, cl
, 0, &cache_reg
);
372 if (retval
!= ERROR_OK
)
374 cache
->arch
[cl
].d_u_size
= decode_cache_reg(cache_reg
);
376 LOG_DEBUG("data/unified cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32
,
377 cache
->arch
[cl
].d_u_size
.index
,
378 cache
->arch
[cl
].d_u_size
.index_shift
,
379 cache
->arch
[cl
].d_u_size
.way
,
380 cache
->arch
[cl
].d_u_size
.way_shift
);
382 LOG_DEBUG("cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
383 cache
->arch
[cl
].d_u_size
.linelen
,
384 cache
->arch
[cl
].d_u_size
.cachesize
,
385 cache
->arch
[cl
].d_u_size
.associativity
);
388 /* separate i-cache at this level ? */
389 if (ctype
& CACHE_LEVEL_HAS_I_CACHE
) {
390 /* retrieve i-cache info */
391 retval
= get_cache_info(dpm
, cl
, 1, &cache_reg
);
392 if (retval
!= ERROR_OK
)
394 cache
->arch
[cl
].i_size
= decode_cache_reg(cache_reg
);
396 LOG_DEBUG("instruction cache index %" PRIu32
" << %" PRIu32
", way %" PRIu32
" << %" PRIu32
,
397 cache
->arch
[cl
].i_size
.index
,
398 cache
->arch
[cl
].i_size
.index_shift
,
399 cache
->arch
[cl
].i_size
.way
,
400 cache
->arch
[cl
].i_size
.way_shift
);
402 LOG_DEBUG("cacheline %" PRIu32
" bytes %" PRIu32
" KBytes asso %" PRIu32
" ways",
403 cache
->arch
[cl
].i_size
.linelen
,
404 cache
->arch
[cl
].i_size
.cachesize
,
405 cache
->arch
[cl
].i_size
.associativity
);
408 cache
->arch
[cl
].ctype
= ctype
;
411 /* restore selected cache */
412 dpm
->instr_write_data_r0(dpm
,
413 armv8_opcode(armv8
, WRITE_REG_CSSELR
), csselr
);
414 if (retval
!= ERROR_OK
)
417 armv8
->armv8_mmu
.armv8_cache
.info
= 1;
419 /* if no l2 cache initialize l1 data cache flush function function */
420 if (!armv8
->armv8_mmu
.armv8_cache
.flush_all_data_cache
) {
421 armv8
->armv8_mmu
.armv8_cache
.display_cache_info
=
422 armv8_handle_inner_cache_info_command
;
423 armv8
->armv8_mmu
.armv8_cache
.flush_all_data_cache
=
424 armv8_flush_all_data
;
428 armv8_dpm_modeswitch(dpm
, ARM_MODE_ANY
);