1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # http://cogcomp.com/csb_csb337.htm
6 source [find target/at91rm9200.cfg]
8 # boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
9 set _FLASHNAME $_CHIPNAME.flash
10 flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
12 # ETM9 trace port connector present on this board, 16 data pins.
13 if { [info exists ETM_DRIVER] } {
14 etm config $_TARGETNAME 16 normal half $ETM_DRIVER
15 # OpenOCD may someday support a real trace port driver...
16 # system config file would need to configure it.
18 etm config $_TARGETNAME 16 normal half dummy
19 etm_dummy config $_TARGETNAME
22 proc csb337_clk_init { } {
23 # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
26 # CKGR_MOR: start main oscillator (3.6864 MHz)
30 # CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
31 mww 0xfffffc28 0x20313e01
32 # CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
33 mww 0xfffffc2c 0x12703e18
37 # PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
41 # CPU is in Normal Mode ... allows faster JTAG clock speed
45 proc csb337_nor_init { } {
46 # SMC_CSR0: adjust timings (10 wait states)
47 mww 0xffffff70 0x1100318a
52 proc csb337_sdram_init { } {
55 # PC31..PC16 are D31..D16, with internal pullups like D15..D0
56 mww 0xfffff870 0xffff0000
58 mww 0xfffff804 0xffff0000
60 # SDRC_CR: set timings
61 mww 0xffffff98 0x2188b0d5
63 # SDRC_MR: issue all banks precharge to SDRAM
67 # SDRC_MR: 8 autorefresh cycles
78 # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
82 # SDRC_TR: set refresh rate
86 # SDRC_MR: normal mode, 32 bit bus
91 # The rm9200 chip has just been reset. Bring it up far enough
92 # that we can write flash or run code from SDRAM.
93 proc csb337_reset_init { } {
96 # EBI_CSA: CS0 = NOR, CS1 = SDRAM
102 # Update CP15 control register ... we don't seem to be able to
103 # read/modify/write its value through a TCL variable, so just
104 # write it. Fields are zero unless listed here ... and note
105 # that OpenOCD numbers this register "2", not "1" (!).
107 # - Core to use Async Clocking mode (so it uses 184 MHz most
108 # of the time instead of limiting to the master clock rate):
109 # iA(31) = 1, nF(30) = 1
110 # - Icache on (it's disabled now, slowing i-fetches)
114 arm920t cp15 2 0xc0001078
117 $_TARGETNAME configure -event reset-init {csb337_reset_init}
119 arm7_9 fast_memory_access enable