src/target/mips_m4k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "mips32.h"
  27 #include "mips_m4k.h"
  28 #include "mips32_dmaacc.h"
  29 #include "target_type.h"
  30
  31
  32 /* cli handling */
  33
  34 /* forward declarations */
  35 int mips_m4k_poll(target_t *target);
  36 int mips_m4k_halt(struct target_s *target);
  37 int mips_m4k_soft_reset_halt(struct target_s *target);
  38 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
  39 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
  40 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  41 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  42 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
  43 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  44 int mips_m4k_quit(void);
  45 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
  46
  47 int mips_m4k_examine(struct target_s *target);
  48 int mips_m4k_assert_reset(target_t *target);
  49 int mips_m4k_deassert_reset(target_t *target);
  50 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum);
  51
  52 target_type_t mips_m4k_target =
  53 {
  54         .name = "mips_m4k",
  55
  56         .poll = mips_m4k_poll,
  57         .arch_state = mips32_arch_state,
  58
  59         .target_request_data = NULL,
  60
  61         .halt = mips_m4k_halt,
  62         .resume = mips_m4k_resume,
  63         .step = mips_m4k_step,
  64
  65         .assert_reset = mips_m4k_assert_reset,
  66         .deassert_reset = mips_m4k_deassert_reset,
  67         .soft_reset_halt = mips_m4k_soft_reset_halt,
  68
  69         .get_gdb_reg_list = mips32_get_gdb_reg_list,
  70
  71         .read_memory = mips_m4k_read_memory,
  72         .write_memory = mips_m4k_write_memory,
  73         .bulk_write_memory = mips_m4k_bulk_write_memory,
  74         .checksum_memory = mips_m4k_checksum_memory,
  75         .blank_check_memory = NULL,
  76
  77         .run_algorithm = mips32_run_algorithm,
  78
  79         .add_breakpoint = mips_m4k_add_breakpoint,
  80         .remove_breakpoint = mips_m4k_remove_breakpoint,
  81         .add_watchpoint = mips_m4k_add_watchpoint,
  82         .remove_watchpoint = mips_m4k_remove_watchpoint,
  83
  84         .register_commands = mips_m4k_register_commands,
  85         .target_create = mips_m4k_target_create,
  86         .init_target = mips_m4k_init_target,
  87         .examine = mips_m4k_examine,
  88         .quit = mips_m4k_quit
  89 };
  90
  91 int mips_m4k_examine_debug_reason(target_t *target)
  92 {
  93         u32 break_status;
  94         int retval;
  95
  96         if ((target->debug_reason != DBG_REASON_DBGRQ)
  97                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
  98         {
  99                 /* get info about inst breakpoint support */
 100                 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
 101                         return retval;
 102                 if (break_status & 0x1f)
 103                 {
 104                         /* we have halted on a  breakpoint */
 105                         if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 106                                 return retval;
 107                         target->debug_reason = DBG_REASON_BREAKPOINT;
 108                 }
 109
 110                 /* get info about data breakpoint support */
 111                 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
 112                         return retval;
 113                 if (break_status & 0x1f)
 114                 {
 115                         /* we have halted on a  breakpoint */
 116                         if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
 117                                 return retval;
 118                         target->debug_reason = DBG_REASON_WATCHPOINT;
 119                 }
 120         }
 121
 122         return ERROR_OK;
 123 }
 124
 125 int mips_m4k_debug_entry(target_t *target)
 126 {
 127         mips32_common_t *mips32 = target->arch_info;
 128         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 129         u32 debug_reg;
 130
 131         /* read debug register */
 132         mips_ejtag_read_debug(ejtag_info, &debug_reg);
 133
 134         /* make sure break uit configured */
 135         mips32_configure_break_unit(target);
 136
 137         /* attempt to find halt reason */
 138         mips_m4k_examine_debug_reason(target);
 139
 140         /* clear single step if active */
 141         if (debug_reg & EJTAG_DEBUG_DSS)
 142         {
 143                 /* stopped due to single step - clear step bit */
 144                 mips_ejtag_config_step(ejtag_info, 0);
 145         }
 146
 147         mips32_save_context(target);
 148
 149         LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
 150                 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
 151                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 152
 153         return ERROR_OK;
 154 }
 155
 156 int mips_m4k_poll(target_t *target)
 157 {
 158         int retval;
 159         mips32_common_t *mips32 = target->arch_info;
 160         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 161         u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
 162
 163         /* read ejtag control reg */
 164         jtag_set_end_state(TAP_IDLE);
 165         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 166         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 167
 168         /* clear this bit before handling polling
 169          * as after reset registers will read zero */
 170         if (ejtag_ctrl & EJTAG_CTRL_ROCC)
 171         {
 172                 /* we have detected a reset, clear flag
 173                  * otherwise ejtag will not work */
 174                 jtag_set_end_state(TAP_IDLE);
 175                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 176
 177                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 178                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 179                 LOG_DEBUG("Reset Detected");
 180         }
 181
 182         /* check for processor halted */
 183         if (ejtag_ctrl & EJTAG_CTRL_BRKST)
 184         {
 185                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 186                 {
 187                         jtag_set_end_state(TAP_IDLE);
 188                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 189
 190                         target->state = TARGET_HALTED;
 191
 192                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 193                                 return retval;
 194
 195                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 196                 }
 197                 else if (target->state == TARGET_DEBUG_RUNNING)
 198                 {
 199                         target->state = TARGET_HALTED;
 200
 201                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 202                                 return retval;
 203
 204                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 205                 }
 206         }
 207         else
 208         {
 209                 target->state = TARGET_RUNNING;
 210         }
 211
 212 //      LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
 213
 214         return ERROR_OK;
 215 }
 216
 217 int mips_m4k_halt(struct target_s *target)
 218 {
 219         mips32_common_t *mips32 = target->arch_info;
 220         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 221
 222         LOG_DEBUG("target->state: %s",
 223                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 224
 225         if (target->state == TARGET_HALTED)
 226         {
 227                 LOG_DEBUG("target was already halted");
 228                 return ERROR_OK;
 229         }
 230
 231         if (target->state == TARGET_UNKNOWN)
 232         {
 233                 LOG_WARNING("target was in unknown state when halt was requested");
 234         }
 235
 236         if (target->state == TARGET_RESET)
 237         {
 238                 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 239                 {
 240                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 241                         return ERROR_TARGET_FAILURE;
 242                 }
 243                 else
 244                 {
 245                         /* we came here in a reset_halt or reset_init sequence
 246                          * debug entry was already prepared in mips32_prepare_reset_halt()
 247                          */
 248                         target->debug_reason = DBG_REASON_DBGRQ;
 249
 250                         return ERROR_OK;
 251                 }
 252         }
 253
 254         /* break processor */
 255         mips_ejtag_enter_debug(ejtag_info);
 256
 257         target->debug_reason = DBG_REASON_DBGRQ;
 258
 259         return ERROR_OK;
 260 }
 261
 262 int mips_m4k_assert_reset(target_t *target)
 263 {
 264         mips32_common_t *mips32 = target->arch_info;
 265         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 266
 267         LOG_DEBUG("target->state: %s",
 268                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 269
 270         if (!(jtag_reset_config & RESET_HAS_SRST))
 271         {
 272                 LOG_ERROR("Can't assert SRST");
 273                 return ERROR_FAIL;
 274         }
 275
 276         if (target->reset_halt)
 277         {
 278                 /* use hardware to catch reset */
 279                 jtag_set_end_state(TAP_IDLE);
 280                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
 281         }
 282         else
 283         {
 284                 jtag_set_end_state(TAP_IDLE);
 285                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 286         }
 287
 288         if (strcmp(target->variant, "ejtag_srst") == 0)
 289         {
 290                 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 291                 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 292                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 293                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 294         }
 295         else
 296         {
 297                 /* here we should issue a srst only, but we may have to assert trst as well */
 298                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 299                 {
 300                         jtag_add_reset(1, 1);
 301                 }
 302                 else
 303                 {
 304                         jtag_add_reset(0, 1);
 305                 }
 306         }
 307
 308         target->state = TARGET_RESET;
 309         jtag_add_sleep(50000);
 310
 311         mips32_invalidate_core_regs(target);
 312
 313         if (target->reset_halt)
 314         {
 315                 int retval;
 316                 if ((retval = target_halt(target))!=ERROR_OK)
 317                         return retval;
 318         }
 319
 320         return ERROR_OK;
 321 }
 322
 323 int mips_m4k_deassert_reset(target_t *target)
 324 {
 325         LOG_DEBUG("target->state: %s",
 326                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 327
 328         /* deassert reset lines */
 329         jtag_add_reset(0, 0);
 330
 331         return ERROR_OK;
 332 }
 333
 334 int mips_m4k_soft_reset_halt(struct target_s *target)
 335 {
 336         /* TODO */
 337         return ERROR_OK;
 338 }
 339
 340 int mips_m4k_single_step_core(target_t *target)
 341 {
 342         mips32_common_t *mips32 = target->arch_info;
 343         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 344
 345         /* configure single step mode */
 346         mips_ejtag_config_step(ejtag_info, 1);
 347
 348         /* disable interrupts while stepping */
 349         mips32_enable_interrupts(target, 0);
 350
 351         /* exit debug mode */
 352         mips_ejtag_exit_debug(ejtag_info);
 353
 354         mips_m4k_debug_entry(target);
 355
 356         return ERROR_OK;
 357 }
 358
 359 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 360 {
 361         mips32_common_t *mips32 = target->arch_info;
 362         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 363         breakpoint_t *breakpoint = NULL;
 364         u32 resume_pc;
 365
 366         if (target->state != TARGET_HALTED)
 367         {
 368                 LOG_WARNING("target not halted");
 369                 return ERROR_TARGET_NOT_HALTED;
 370         }
 371
 372         if (!debug_execution)
 373         {
 374                 target_free_all_working_areas(target);
 375                 mips_m4k_enable_breakpoints(target);
 376                 mips_m4k_enable_watchpoints(target);
 377         }
 378
 379         /* current = 1: continue on current pc, otherwise continue at <address> */
 380         if (!current)
 381         {
 382                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 383                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 384                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 385         }
 386
 387         resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 388
 389         mips32_restore_context(target);
 390
 391         /* the front-end may request us not to handle breakpoints */
 392         if (handle_breakpoints)
 393         {
 394                 /* Single step past breakpoint at current address */
 395                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 396                 {
 397                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 398                         mips_m4k_unset_breakpoint(target, breakpoint);
 399                         mips_m4k_single_step_core(target);
 400                         mips_m4k_set_breakpoint(target, breakpoint);
 401                 }
 402         }
 403
 404         /* enable interrupts if we are running */
 405         mips32_enable_interrupts(target, !debug_execution);
 406
 407         /* exit debug mode */
 408         mips_ejtag_exit_debug(ejtag_info);
 409         target->debug_reason = DBG_REASON_NOTHALTED;
 410
 411         /* registers are now invalid */
 412         mips32_invalidate_core_regs(target);
 413
 414         if (!debug_execution)
 415         {
 416                 target->state = TARGET_RUNNING;
 417                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 418                 LOG_DEBUG("target resumed at 0x%x", resume_pc);
 419         }
 420         else
 421         {
 422                 target->state = TARGET_DEBUG_RUNNING;
 423                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 424                 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
 425         }
 426
 427         return ERROR_OK;
 428 }
 429
 430 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 431 {
 432         /* get pointers to arch-specific information */
 433         mips32_common_t *mips32 = target->arch_info;
 434         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 435         breakpoint_t *breakpoint = NULL;
 436
 437         if (target->state != TARGET_HALTED)
 438         {
 439                 LOG_WARNING("target not halted");
 440                 return ERROR_TARGET_NOT_HALTED;
 441         }
 442
 443         /* current = 1: continue on current pc, otherwise continue at <address> */
 444         if (!current)
 445                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 446
 447         /* the front-end may request us not to handle breakpoints */
 448         if (handle_breakpoints)
 449                 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
 450                         mips_m4k_unset_breakpoint(target, breakpoint);
 451
 452         /* restore context */
 453         mips32_restore_context(target);
 454
 455         /* configure single step mode */
 456         mips_ejtag_config_step(ejtag_info, 1);
 457
 458         target->debug_reason = DBG_REASON_SINGLESTEP;
 459
 460         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 461
 462         /* disable interrupts while stepping */
 463         mips32_enable_interrupts(target, 0);
 464
 465         /* exit debug mode */
 466         mips_ejtag_exit_debug(ejtag_info);
 467
 468         /* registers are now invalid */
 469         mips32_invalidate_core_regs(target);
 470
 471         if (breakpoint)
 472                 mips_m4k_set_breakpoint(target, breakpoint);
 473
 474         LOG_DEBUG("target stepped ");
 475
 476         mips_m4k_debug_entry(target);
 477         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 478
 479         return ERROR_OK;
 480 }
 481
 482 void mips_m4k_enable_breakpoints(struct target_s *target)
 483 {
 484         breakpoint_t *breakpoint = target->breakpoints;
 485
 486         /* set any pending breakpoints */
 487         while (breakpoint)
 488         {
 489                 if (breakpoint->set == 0)
 490                         mips_m4k_set_breakpoint(target, breakpoint);
 491                 breakpoint = breakpoint->next;
 492         }
 493 }
 494
 495 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 496 {
 497         mips32_common_t *mips32 = target->arch_info;
 498         mips32_comparator_t * comparator_list = mips32->inst_break_list;
 499         int retval;
 500
 501         if (breakpoint->set)
 502         {
 503                 LOG_WARNING("breakpoint already set");
 504                 return ERROR_OK;
 505         }
 506
 507         if (breakpoint->type == BKPT_HARD)
 508         {
 509                 int bp_num = 0;
 510
 511                 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 512                         bp_num++;
 513                 if (bp_num >= mips32->num_inst_bpoints)
 514                 {
 515                         LOG_DEBUG("ERROR Can not find free FP Comparator");
 516                         LOG_WARNING("ERROR Can not find free FP Comparator");
 517                         exit(-1);
 518                 }
 519                 breakpoint->set = bp_num + 1;
 520                 comparator_list[bp_num].used = 1;
 521                 comparator_list[bp_num].bp_value = breakpoint->address;
 522                 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
 523                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
 524                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
 525                 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
 526         }
 527         else if (breakpoint->type == BKPT_SOFT)
 528         {
 529                 if (breakpoint->length == 4)
 530                 {
 531                         u32 verify = 0xffffffff;
 532
 533                         if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 534                         {
 535                                 return retval;
 536                         }
 537                         if ((retval = target_write_u32(target, breakpoint->address, MIPS32_SDBBP)) != ERROR_OK)
 538                         {
 539                                 return retval;
 540                         }
 541
 542                         if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
 543                         {
 544                                 return retval;
 545                         }
 546                         if (verify != MIPS32_SDBBP)
 547                         {
 548                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
 549                                 return ERROR_OK;
 550                         }
 551                 }
 552                 else
 553                 {
 554                         u16 verify = 0xffff;
 555
 556                         if((retval = target_read_memory(target, breakpoint->address, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
 557                         {
 558                                 return retval;
 559                         }
 560                         if ((retval = target_write_u16(target, breakpoint->address, MIPS16_SDBBP)) != ERROR_OK)
 561                         {
 562                                 return retval;
 563                         }
 564
 565                         if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
 566                         {
 567                                 return retval;
 568                         }
 569                         if (verify != MIPS16_SDBBP)
 570                         {
 571                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
 572                                 return ERROR_OK;
 573                         }
 574                 }
 575
 576                 breakpoint->set = 20; /* Any nice value but 0 */
 577         }
 578
 579         return ERROR_OK;
 580 }
 581
 582 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 583 {
 584         /* get pointers to arch-specific information */
 585         mips32_common_t *mips32 = target->arch_info;
 586         mips32_comparator_t * comparator_list = mips32->inst_break_list;
 587         int retval;
 588
 589         if (!breakpoint->set)
 590         {
 591                 LOG_WARNING("breakpoint not set");
 592                 return ERROR_OK;
 593         }
 594
 595         if (breakpoint->type == BKPT_HARD)
 596         {
 597                 int bp_num = breakpoint->set - 1;
 598                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
 599                 {
 600                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 601                         return ERROR_OK;
 602                 }
 603                 comparator_list[bp_num].used = 0;
 604                 comparator_list[bp_num].bp_value = 0;
 605                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
 606         }
 607         else
 608         {
 609                 /* restore original instruction (kept in target endianness) */
 610                 if (breakpoint->length == 4)
 611                 {
 612                         u32 current_instr;
 613
 614                         /* check that user program has not modified breakpoint instruction */
 615                         if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
 616                         {
 617                                 return retval;
 618                         }
 619                         if (current_instr == MIPS32_SDBBP)
 620                         {
 621                                 if((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 622                                 {
 623                                         return retval;
 624                                 }
 625                         }
 626                 }
 627                 else
 628                 {
 629                         u16 current_instr;
 630
 631                         /* check that user program has not modified breakpoint instruction */
 632                         if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
 633                         {
 634                                 return retval;
 635                         }
 636
 637                         if (current_instr == MIPS16_SDBBP)
 638                         {
 639                                 if((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 640                                 {
 641                                         return retval;
 642                                 }
 643                         }
 644                 }
 645         }
 646         breakpoint->set = 0;
 647
 648         return ERROR_OK;
 649 }
 650
 651 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 652 {
 653         mips32_common_t *mips32 = target->arch_info;
 654
 655         if (breakpoint->type == BKPT_HARD)
 656         {
 657                 if (mips32->num_inst_bpoints_avail < 1)
 658                 {
 659                         LOG_INFO("no hardware breakpoint available");
 660                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 661                 }
 662
 663                 mips32->num_inst_bpoints_avail--;
 664         }
 665
 666         mips_m4k_set_breakpoint(target, breakpoint);
 667
 668         return ERROR_OK;
 669 }
 670
 671 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 672 {
 673         /* get pointers to arch-specific information */
 674         mips32_common_t *mips32 = target->arch_info;
 675
 676         if (target->state != TARGET_HALTED)
 677         {
 678                 LOG_WARNING("target not halted");
 679                 return ERROR_TARGET_NOT_HALTED;
 680         }
 681
 682         if (breakpoint->set)
 683         {
 684                 mips_m4k_unset_breakpoint(target, breakpoint);
 685         }
 686
 687         if (breakpoint->type == BKPT_HARD)
 688                 mips32->num_inst_bpoints_avail++;
 689
 690         return ERROR_OK;
 691 }
 692
 693 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 694 {
 695         /* TODO */
 696         return ERROR_OK;
 697 }
 698
 699 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 700 {
 701         /* TODO */
 702         return ERROR_OK;
 703 }
 704
 705 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 706 {
 707         /* TODO */
 708         return ERROR_OK;
 709 }
 710
 711 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 712 {
 713         /* TODO */
 714         return ERROR_OK;
 715 }
 716
 717 void mips_m4k_enable_watchpoints(struct target_s *target)
 718 {
 719         watchpoint_t *watchpoint = target->watchpoints;
 720
 721         /* set any pending watchpoints */
 722         while (watchpoint)
 723         {
 724                 if (watchpoint->set == 0)
 725                         mips_m4k_set_watchpoint(target, watchpoint);
 726                 watchpoint = watchpoint->next;
 727         }
 728 }
 729
 730 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 731 {
 732         mips32_common_t *mips32 = target->arch_info;
 733         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 734
 735         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 736
 737         if (target->state != TARGET_HALTED)
 738         {
 739                 LOG_WARNING("target not halted");
 740                 return ERROR_TARGET_NOT_HALTED;
 741         }
 742
 743         /* sanitize arguments */
 744         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 745                 return ERROR_INVALID_ARGUMENTS;
 746
 747         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 748                 return ERROR_TARGET_UNALIGNED_ACCESS;
 749
 750         switch (size)
 751         {
 752                 case 4:
 753                 case 2:
 754                 case 1:
 755                         /* if noDMA off, use DMAACC mode for memory read */
 756                         if(ejtag_info->impcode & EJTAG_IMP_NODMA)
 757                                 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 758                         else
 759                                 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 760                 default:
 761                         LOG_ERROR("BUG: we shouldn't get here");
 762                         exit(-1);
 763                         break;
 764         }
 765
 766         return ERROR_OK;
 767 }
 768
 769 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 770 {
 771         mips32_common_t *mips32 = target->arch_info;
 772         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 773
 774         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 775
 776         if (target->state != TARGET_HALTED)
 777         {
 778                 LOG_WARNING("target not halted");
 779                 return ERROR_TARGET_NOT_HALTED;
 780         }
 781
 782         /* sanitize arguments */
 783         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 784                 return ERROR_INVALID_ARGUMENTS;
 785
 786         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 787                 return ERROR_TARGET_UNALIGNED_ACCESS;
 788
 789         switch (size)
 790         {
 791                 case 4:
 792                 case 2:
 793                 case 1:
 794                         /* if noDMA off, use DMAACC mode for memory write */
 795                         if(ejtag_info->impcode & EJTAG_IMP_NODMA)
 796                                 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 797                         else
 798                                 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 799                         break;
 800                 default:
 801                         LOG_ERROR("BUG: we shouldn't get here");
 802                         exit(-1);
 803                         break;
 804         }
 805
 806         return ERROR_OK;
 807 }
 808
 809 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
 810 {
 811         int retval;
 812
 813         retval = mips32_register_commands(cmd_ctx);
 814         return retval;
 815 }
 816
 817 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 818 {
 819         mips32_build_reg_cache(target);
 820
 821         return ERROR_OK;
 822 }
 823
 824 int mips_m4k_quit(void)
 825 {
 826         return ERROR_OK;
 827 }
 828
 829 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
 830 {
 831         mips32_common_t *mips32 = &mips_m4k->mips32_common;
 832
 833         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 834
 835         /* initialize mips4k specific info */
 836         mips32_init_arch_info(target, mips32, tap);
 837         mips32->arch_info = mips_m4k;
 838
 839         return ERROR_OK;
 840 }
 841
 842 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
 843 {
 844         mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
 845
 846         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 847
 848         return ERROR_OK;
 849 }
 850
 851 int mips_m4k_examine(struct target_s *target)
 852 {
 853         int retval;
 854         mips32_common_t *mips32 = target->arch_info;
 855         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 856         u32 idcode = 0;
 857
 858         if (!target_was_examined(target))
 859         {
 860                 mips_ejtag_get_idcode(ejtag_info, &idcode);
 861                 ejtag_info->idcode = idcode;
 862
 863                 if (((idcode >> 1) & 0x7FF) == 0x29)
 864                 {
 865                         /* we are using a pic32mx so select ejtag port
 866                          * as it is not selected by default */
 867                         mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
 868                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 869                 }
 870         }
 871
 872         /* init rest of ejtag interface */
 873         if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
 874                 return retval;
 875
 876         if ((retval = mips32_examine(target)) != ERROR_OK)
 877                 return retval;
 878
 879         return ERROR_OK;
 880 }
 881
 882 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
 883 {
 884         return mips_m4k_write_memory(target, address, 4, count, buffer);
 885 }
 886
 887 int mips_m4k_checksum_memory(target_t *target, u32 address, u32 size, u32 *checksum)
 888 {
 889         return ERROR_FAIL; /* use bulk read method */
 890 }