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tcl: add ASUS RT-N66U config
[openocd.git] / src / flash / nand / mxc.c
blobb91460ef236b208a06269fb752b33b3da19d4ab1
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * Copyright (C) 2011 by Erik Ahlen *
10 * Avalon Innovation, Sweden *
11 * *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
16 * *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
21 * *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
26 ***************************************************************************/
27
28 /*
29 * Freescale iMX OpenOCD NAND Flash controller support.
30 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
31 */
32
33 /*
34 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
35 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
36 * "nand write # file 0", "nand verify"
37 *
38 * get_next_halfword_from_sram_buffer() not tested
39 * !! all function only tested with 2k page nand device; mxc_write_page
40 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
41 * !! oob must be be used due to NFS bug
42 * !! oob must be 64 bytes per 2KiB page
43 */
44 #ifdef HAVE_CONFIG_H
45 #include "config.h"
46 #endif
47
48 #include "imp.h"
49 #include "mxc.h"
50 #include <target/target.h>
51
52 #define OOB_SIZE 64
53
54 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
55 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
56 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
57 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
58
59 /* This permits to print (in LOG_INFO) how much bytes
60 * has been written after a page read or write.
61 * This is useful when OpenOCD is used with a graphical
62 * front-end to estimate progression of the global read/write
63 */
64 #undef _MXC_PRINT_STAT
65 /* #define _MXC_PRINT_STAT */
66
67 static const char target_not_halted_err_msg[] =
68 "target must be halted to use mxc NAND flash controller";
69 static const char data_block_size_err_msg[] =
70 "minimal granularity is one half-word, %" PRId32 " is incorrect";
71 static const char sram_buffer_bounds_err_msg[] =
72 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
73 static const char get_status_register_err_msg[] = "can't get NAND status";
74 static uint32_t in_sram_address;
75 static unsigned char sign_of_sequental_byte_read;
76
77 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr);
78 static int initialize_nf_controller(struct nand_device *nand);
79 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
80 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
81 static int poll_for_complete_op(struct nand_device *nand, const char *text);
82 static int validate_target_state(struct nand_device *nand);
83 static int do_data_output(struct nand_device *nand);
84
85 static int mxc_command(struct nand_device *nand, uint8_t command);
86 static int mxc_address(struct nand_device *nand, uint8_t address);
87
88 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
89 {
90 struct mxc_nf_controller *mxc_nf_info;
91 int hwecc_needed;
92
93 mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
94 if (mxc_nf_info == NULL) {
95 LOG_ERROR("no memory for nand controller");
96 return ERROR_FAIL;
97 }
98 nand->controller_priv = mxc_nf_info;
99
100 if (CMD_ARGC < 4) {
101 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
102 return ERROR_FAIL;
103 }
104
105 /*
106 * check board type
107 */
108 if (strcmp(CMD_ARGV[2], "mx25") == 0) {
109 mxc_nf_info->mxc_version = MXC_VERSION_MX25;
110 mxc_nf_info->mxc_base_addr = 0xBB000000;
111 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
112 } else if (strcmp(CMD_ARGV[2], "mx27") == 0) {
113 mxc_nf_info->mxc_version = MXC_VERSION_MX27;
114 mxc_nf_info->mxc_base_addr = 0xD8000000;
115 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
116 } else if (strcmp(CMD_ARGV[2], "mx31") == 0) {
117 mxc_nf_info->mxc_version = MXC_VERSION_MX31;
118 mxc_nf_info->mxc_base_addr = 0xB8000000;
119 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x0E00;
120 } else if (strcmp(CMD_ARGV[2], "mx35") == 0) {
121 mxc_nf_info->mxc_version = MXC_VERSION_MX35;
122 mxc_nf_info->mxc_base_addr = 0xBB000000;
123 mxc_nf_info->mxc_regs_addr = mxc_nf_info->mxc_base_addr + 0x1E00;
124 }
125
126 /*
127 * check hwecc requirements
128 */
129 hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
130 if (hwecc_needed == 0)
131 mxc_nf_info->flags.hw_ecc_enabled = 1;
132 else
133 mxc_nf_info->flags.hw_ecc_enabled = 0;
134
135 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
136 mxc_nf_info->fin = MXC_NF_FIN_NONE;
137 mxc_nf_info->flags.target_little_endian =
138 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
139
140 /*
141 * should factory bad block indicator be swaped
142 * as a workaround for how the nfc handles pages.
143 */
144 if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
145 LOG_DEBUG("BI-swap enabled");
146 mxc_nf_info->flags.biswap_enabled = 1;
147 }
148
149 return ERROR_OK;
150 }
151
152 COMMAND_HANDLER(handle_mxc_biswap_command)
153 {
154 struct nand_device *nand = NULL;
155 struct mxc_nf_controller *mxc_nf_info = NULL;
156
157 if (CMD_ARGC < 1 || CMD_ARGC > 2)
158 return ERROR_COMMAND_SYNTAX_ERROR;
159
160 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
161 if (retval != ERROR_OK) {
162 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
163 return ERROR_COMMAND_ARGUMENT_INVALID;
164 }
165
166 mxc_nf_info = nand->controller_priv;
167 if (CMD_ARGC == 2) {
168 if (strcmp(CMD_ARGV[1], "enable") == 0)
169 mxc_nf_info->flags.biswap_enabled = true;
170 else
171 mxc_nf_info->flags.biswap_enabled = false;
172 }
173 if (mxc_nf_info->flags.biswap_enabled)
174 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
175 else
176 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
177
178 return ERROR_OK;
179 }
180
181 static const struct command_registration mxc_sub_command_handlers[] = {
182 {
183 .name = "biswap",
184 .handler = handle_mxc_biswap_command,
185 .help = "Turns on/off bad block information swaping from main area, "
186 "without parameter query status.",
187 .usage = "bank_id ['enable'|'disable']",
188 },
189 COMMAND_REGISTRATION_DONE
190 };
191
192 static const struct command_registration mxc_nand_command_handler[] = {
193 {
194 .name = "mxc",
195 .mode = COMMAND_ANY,
196 .help = "MXC NAND flash controller commands",
197 .chain = mxc_sub_command_handlers
198 },
199 COMMAND_REGISTRATION_DONE
200 };
201
202 static int mxc_init(struct nand_device *nand)
203 {
204 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
205 struct target *target = nand->target;
206
207 int validate_target_result;
208 uint16_t buffsize_register_content;
209 uint32_t sreg_content;
210 uint32_t SREG = MX2_FMCR;
211 uint32_t SEL_16BIT = MX2_FMCR_NF_16BIT_SEL;
212 uint32_t SEL_FMS = MX2_FMCR_NF_FMS;
213 int retval;
214 uint16_t nand_status_content;
215 /*
216 * validate target state
217 */
218 validate_target_result = validate_target_state(nand);
219 if (validate_target_result != ERROR_OK)
220 return validate_target_result;
221
222 if (nfc_is_v1()) {
223 target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
224 mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
225 } else
226 mxc_nf_info->flags.one_kb_sram = 0;
227
228 if (mxc_nf_info->mxc_version == MXC_VERSION_MX31) {
229 SREG = MX3_PCSR;
230 SEL_16BIT = MX3_PCSR_NF_16BIT_SEL;
231 SEL_FMS = MX3_PCSR_NF_FMS;
232 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX25) {
233 SREG = MX25_RCSR;
234 SEL_16BIT = MX25_RCSR_NF_16BIT_SEL;
235 SEL_FMS = MX25_RCSR_NF_FMS;
236 } else if (mxc_nf_info->mxc_version == MXC_VERSION_MX35) {
237 SREG = MX35_RCSR;
238 SEL_16BIT = MX35_RCSR_NF_16BIT_SEL;
239 SEL_FMS = MX35_RCSR_NF_FMS;
240 }
241
242 target_read_u32(target, SREG, &sreg_content);
243 if (!nand->bus_width) {
244 /* bus_width not yet defined. Read it from MXC_FMCR */
245 nand->bus_width = (sreg_content & SEL_16BIT) ? 16 : 8;
246 } else {
247 /* bus_width forced in soft. Sync it to MXC_FMCR */
248 sreg_content |= ((nand->bus_width == 16) ? SEL_16BIT : 0x00000000);
249 target_write_u32(target, SREG, sreg_content);
250 }
251 if (nand->bus_width == 16)
252 LOG_DEBUG("MXC_NF : bus is 16-bit width");
253 else
254 LOG_DEBUG("MXC_NF : bus is 8-bit width");
255
256 if (!nand->page_size)
257 nand->page_size = (sreg_content & SEL_FMS) ? 2048 : 512;
258 else {
259 sreg_content |= ((nand->page_size == 2048) ? SEL_FMS : 0x00000000);
260 target_write_u32(target, SREG, sreg_content);
261 }
262 if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
263 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
264 "pagesize 2048 is incompatible with it");
265 } else
266 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
267
268 if (nfc_is_v2() && sreg_content & MX35_RCSR_NF_4K)
269 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
270
271 initialize_nf_controller(nand);
272
273 retval = ERROR_OK;
274 retval |= mxc_command(nand, NAND_CMD_STATUS);
275 retval |= mxc_address(nand, 0x00);
276 retval |= do_data_output(nand);
277 if (retval != ERROR_OK) {
278 LOG_ERROR(get_status_register_err_msg);
279 return ERROR_FAIL;
280 }
281 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
282 if (!(nand_status_content & 0x0080)) {
283 LOG_INFO("NAND read-only");
284 mxc_nf_info->flags.nand_readonly = 1;
285 } else
286 mxc_nf_info->flags.nand_readonly = 0;
287 return ERROR_OK;
288 }
289
290 static int mxc_read_data(struct nand_device *nand, void *data)
291 {
292 int validate_target_result;
293 int try_data_output_from_nand_chip;
294 /*
295 * validate target state
296 */
297 validate_target_result = validate_target_state(nand);
298 if (validate_target_result != ERROR_OK)
299 return validate_target_result;
300
301 /*
302 * get data from nand chip
303 */
304 try_data_output_from_nand_chip = do_data_output(nand);
305 if (try_data_output_from_nand_chip != ERROR_OK) {
306 LOG_ERROR("mxc_read_data : read data failed : '%x'",
307 try_data_output_from_nand_chip);
308 return try_data_output_from_nand_chip;
309 }
310
311 if (nand->bus_width == 16)
312 get_next_halfword_from_sram_buffer(nand, data);
313 else
314 get_next_byte_from_sram_buffer(nand, data);
315
316 return ERROR_OK;
317 }
318
319 static int mxc_write_data(struct nand_device *nand, uint16_t data)
320 {
321 LOG_ERROR("write_data() not implemented");
322 return ERROR_NAND_OPERATION_FAILED;
323 }
324
325 static int mxc_reset(struct nand_device *nand)
326 {
327 /*
328 * validate target state
329 */
330 int validate_target_result;
331 validate_target_result = validate_target_state(nand);
332 if (validate_target_result != ERROR_OK)
333 return validate_target_result;
334 initialize_nf_controller(nand);
335 return ERROR_OK;
336 }
337
338 static int mxc_command(struct nand_device *nand, uint8_t command)
339 {
340 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
341 struct target *target = nand->target;
342 int validate_target_result;
343 int poll_result;
344 /*
345 * validate target state
346 */
347 validate_target_result = validate_target_state(nand);
348 if (validate_target_result != ERROR_OK)
349 return validate_target_result;
350
351 switch (command) {
352 case NAND_CMD_READOOB:
353 command = NAND_CMD_READ0;
354 /* set read point for data_read() and read_block_data() to
355 * spare area in SRAM buffer
356 */
357 if (nfc_is_v1())
358 in_sram_address = MXC_NF_V1_SPARE_BUFFER0;
359 else
360 in_sram_address = MXC_NF_V2_SPARE_BUFFER0;
361 break;
362 case NAND_CMD_READ1:
363 command = NAND_CMD_READ0;
364 /*
365 * offset == one half of page size
366 */
367 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
368 break;
369 default:
370 in_sram_address = MXC_NF_MAIN_BUFFER0;
371 break;
372 }
373
374 target_write_u16(target, MXC_NF_FCMD, command);
375 /*
376 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
377 */
378 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
379 poll_result = poll_for_complete_op(nand, "command");
380 if (poll_result != ERROR_OK)
381 return poll_result;
382 /*
383 * reset cursor to begin of the buffer
384 */
385 sign_of_sequental_byte_read = 0;
386 /* Handle special read command and adjust NF_CFG2(FDO) */
387 switch (command) {
388 case NAND_CMD_READID:
389 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
390 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
391 break;
392 case NAND_CMD_STATUS:
393 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
394 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
395 target_write_u16 (target, MXC_NF_BUFADDR, 0);
396 in_sram_address = 0;
397 break;
398 case NAND_CMD_READ0:
399 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
400 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
401 break;
402 default:
403 /* Ohter command use the default 'One page data out' FDO */
404 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
405 break;
406 }
407 return ERROR_OK;
408 }
409
410 static int mxc_address(struct nand_device *nand, uint8_t address)
411 {
412 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
413 struct target *target = nand->target;
414 int validate_target_result;
415 int poll_result;
416 /*
417 * validate target state
418 */
419 validate_target_result = validate_target_state(nand);
420 if (validate_target_result != ERROR_OK)
421 return validate_target_result;
422
423 target_write_u16(target, MXC_NF_FADDR, address);
424 /*
425 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
426 */
427 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
428 poll_result = poll_for_complete_op(nand, "address");
429 if (poll_result != ERROR_OK)
430 return poll_result;
431
432 return ERROR_OK;
433 }
434
435 static int mxc_nand_ready(struct nand_device *nand, int tout)
436 {
437 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
438 struct target *target = nand->target;
439 uint16_t poll_complete_status;
440 int validate_target_result;
441
442 /*
443 * validate target state
444 */
445 validate_target_result = validate_target_state(nand);
446 if (validate_target_result != ERROR_OK)
447 return validate_target_result;
448
449 do {
450 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
451 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
452 return tout;
453
454 alive_sleep(1);
455 } while (tout-- > 0);
456 return tout;
457 }
458
459 static int mxc_write_page(struct nand_device *nand, uint32_t page,
460 uint8_t *data, uint32_t data_size,
461 uint8_t *oob, uint32_t oob_size)
462 {
463 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
464 struct target *target = nand->target;
465 int retval;
466 uint16_t nand_status_content;
467 uint16_t swap1, swap2, new_swap1;
468 uint8_t bufs;
469 int poll_result;
470
471 if (data_size % 2) {
472 LOG_ERROR(data_block_size_err_msg, data_size);
473 return ERROR_NAND_OPERATION_FAILED;
474 }
475 if (oob_size % 2) {
476 LOG_ERROR(data_block_size_err_msg, oob_size);
477 return ERROR_NAND_OPERATION_FAILED;
478 }
479 if (!data) {
480 LOG_ERROR("nothing to program");
481 return ERROR_NAND_OPERATION_FAILED;
482 }
483
484 /*
485 * validate target state
486 */
487 retval = validate_target_state(nand);
488 if (retval != ERROR_OK)
489 return retval;
490
491 in_sram_address = MXC_NF_MAIN_BUFFER0;
492 sign_of_sequental_byte_read = 0;
493 retval = ERROR_OK;
494 retval |= mxc_command(nand, NAND_CMD_SEQIN);
495 retval |= mxc_address(nand, 0); /* col */
496 retval |= mxc_address(nand, 0); /* col */
497 retval |= mxc_address(nand, page & 0xff); /* page address */
498 retval |= mxc_address(nand, (page >> 8) & 0xff);/* page address */
499 retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
500
501 target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
502 if (oob) {
503 if (mxc_nf_info->flags.hw_ecc_enabled) {
504 /*
505 * part of spare block will be overrided by hardware
506 * ECC generator
507 */
508 LOG_DEBUG("part of spare block will be overrided "
509 "by hardware ECC generator");
510 }
511 if (nfc_is_v1())
512 target_write_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
513 else {
514 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
515 while (oob_size > 0) {
516 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
517 target_write_buffer(target, addr, len, oob);
518 addr = align_address_v2(nand, addr + len);
519 oob += len;
520 oob_size -= len;
521 }
522 }
523 }
524
525 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
526 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
527 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
528 if (oob) {
529 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
530 return ERROR_NAND_OPERATION_FAILED;
531 }
532 swap2 = 0xffff; /* Spare buffer unused forced to 0xffff */
533 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
534 swap2 = (swap1 << 8) | (swap2 & 0xFF);
535 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
536 if (nfc_is_v1())
537 target_write_u16(target, MXC_NF_V1_SPARE_BUFFER3 + 4, swap2);
538 else
539 target_write_u16(target, MXC_NF_V2_SPARE_BUFFER3, swap2);
540 }
541
542 /*
543 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
544 */
545 if (nfc_is_v1() && nand->page_size > 512)
546 bufs = 4;
547 else
548 bufs = 1;
549
550 for (uint8_t i = 0; i < bufs; ++i) {
551 target_write_u16(target, MXC_NF_BUFADDR, i);
552 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
553 poll_result = poll_for_complete_op(nand, "data input");
554 if (poll_result != ERROR_OK)
555 return poll_result;
556 }
557
558 retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
559 if (retval != ERROR_OK)
560 return retval;
561
562 /*
563 * check status register
564 */
565 retval = ERROR_OK;
566 retval |= mxc_command(nand, NAND_CMD_STATUS);
567 target_write_u16 (target, MXC_NF_BUFADDR, 0);
568 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
569 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
570 retval |= do_data_output(nand);
571 if (retval != ERROR_OK) {
572 LOG_ERROR(get_status_register_err_msg);
573 return retval;
574 }
575 target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
576 if (nand_status_content & 0x0001) {
577 /*
578 * page not correctly written
579 */
580 return ERROR_NAND_OPERATION_FAILED;
581 }
582 #ifdef _MXC_PRINT_STAT
583 LOG_INFO("%d bytes newly written", data_size);
584 #endif
585 return ERROR_OK;
586 }
587
588 static int mxc_read_page(struct nand_device *nand, uint32_t page,
589 uint8_t *data, uint32_t data_size,
590 uint8_t *oob, uint32_t oob_size)
591 {
592 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
593 struct target *target = nand->target;
594 int retval;
595 uint8_t bufs;
596 uint16_t swap1, swap2, new_swap1;
597
598 if (data_size % 2) {
599 LOG_ERROR(data_block_size_err_msg, data_size);
600 return ERROR_NAND_OPERATION_FAILED;
601 }
602 if (oob_size % 2) {
603 LOG_ERROR(data_block_size_err_msg, oob_size);
604 return ERROR_NAND_OPERATION_FAILED;
605 }
606
607 /*
608 * validate target state
609 */
610 retval = validate_target_state(nand);
611 if (retval != ERROR_OK)
612 return retval;
613 /* Reset address_cycles before mxc_command ?? */
614 retval = mxc_command(nand, NAND_CMD_READ0);
615 if (retval != ERROR_OK)
616 return retval;
617 retval = mxc_address(nand, 0); /* col */
618 if (retval != ERROR_OK)
619 return retval;
620 retval = mxc_address(nand, 0); /* col */
621 if (retval != ERROR_OK)
622 return retval;
623 retval = mxc_address(nand, page & 0xff);/* page address */
624 if (retval != ERROR_OK)
625 return retval;
626 retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
627 if (retval != ERROR_OK)
628 return retval;
629 retval = mxc_address(nand, (page >> 16) & 0xff);/* page address */
630 if (retval != ERROR_OK)
631 return retval;
632 retval = mxc_command(nand, NAND_CMD_READSTART);
633 if (retval != ERROR_OK)
634 return retval;
635
636 if (nfc_is_v1() && nand->page_size > 512)
637 bufs = 4;
638 else
639 bufs = 1;
640
641 for (uint8_t i = 0; i < bufs; ++i) {
642 target_write_u16(target, MXC_NF_BUFADDR, i);
643 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
644 retval = do_data_output(nand);
645 if (retval != ERROR_OK) {
646 LOG_ERROR("MXC_NF : Error reading page %d", i);
647 return retval;
648 }
649 }
650
651 if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
652 uint32_t SPARE_BUFFER3;
653 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
654 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
655 if (nfc_is_v1())
656 SPARE_BUFFER3 = MXC_NF_V1_SPARE_BUFFER3 + 4;
657 else
658 SPARE_BUFFER3 = MXC_NF_V2_SPARE_BUFFER3;
659 target_read_u16(target, SPARE_BUFFER3, &swap2);
660 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
661 swap2 = (swap1 << 8) | (swap2 & 0xFF);
662 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
663 target_write_u16(target, SPARE_BUFFER3, swap2);
664 }
665
666 if (data)
667 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
668 if (oob) {
669 if (nfc_is_v1())
670 target_read_buffer(target, MXC_NF_V1_SPARE_BUFFER0, oob_size, oob);
671 else {
672 uint32_t addr = MXC_NF_V2_SPARE_BUFFER0;
673 while (oob_size > 0) {
674 uint8_t len = MIN(oob_size, MXC_NF_SPARE_BUFFER_LEN);
675 target_read_buffer(target, addr, len, oob);
676 addr = align_address_v2(nand, addr + len);
677 oob += len;
678 oob_size -= len;
679 }
680 }
681 }
682
683 #ifdef _MXC_PRINT_STAT
684 if (data_size > 0) {
685 /* When Operation Status is read (when page is erased),
686 * this function is used but data_size is null.
687 */
688 LOG_INFO("%d bytes newly read", data_size);
689 }
690 #endif
691 return ERROR_OK;
692 }
693
694 static uint32_t align_address_v2(struct nand_device *nand, uint32_t addr)
695 {
696 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
697 uint32_t ret = addr;
698 if (addr > MXC_NF_V2_SPARE_BUFFER0 &&
699 (addr & 0x1F) == MXC_NF_SPARE_BUFFER_LEN)
700 ret += MXC_NF_SPARE_BUFFER_MAX - MXC_NF_SPARE_BUFFER_LEN;
701 else if (addr >= (mxc_nf_info->mxc_base_addr + (uint32_t)nand->page_size))
702 ret = MXC_NF_V2_SPARE_BUFFER0;
703 return ret;
704 }
705
706 static int initialize_nf_controller(struct nand_device *nand)
707 {
708 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
709 struct target *target = nand->target;
710 uint16_t work_mode = 0;
711 uint16_t temp;
712 /*
713 * resets NAND flash controller in zero time ? I dont know.
714 */
715 target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
716 if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
717 work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
718
719 if (target->endianness == TARGET_BIG_ENDIAN) {
720 LOG_DEBUG("MXC_NF : work in Big Endian mode");
721 work_mode |= MXC_NF_BIT_BE_EN;
722 } else
723 LOG_DEBUG("MXC_NF : work in Little Endian mode");
724 if (mxc_nf_info->flags.hw_ecc_enabled) {
725 LOG_DEBUG("MXC_NF : work with ECC mode");
726 work_mode |= MXC_NF_BIT_ECC_EN;
727 } else
728 LOG_DEBUG("MXC_NF : work without ECC mode");
729 if (nfc_is_v2()) {
730 target_write_u16(target, MXC_NF_V2_SPAS, OOB_SIZE / 2);
731 if (nand->page_size) {
732 uint16_t pages_per_block = nand->erase_size / nand->page_size;
733 work_mode |= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block) - 6);
734 }
735 work_mode |= MXC_NF_BIT_ECC_4BIT;
736 }
737 target_write_u16(target, MXC_NF_CFG1, work_mode);
738
739 /*
740 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
741 */
742 target_write_u16(target, MXC_NF_BUFCFG, 2);
743 target_read_u16(target, MXC_NF_FWP, &temp);
744 if ((temp & 0x0007) == 1) {
745 LOG_ERROR("NAND flash is tight-locked, reset needed");
746 return ERROR_FAIL;
747 }
748
749 /*
750 * unlock NAND flash for write
751 */
752 if (nfc_is_v1()) {
753 target_write_u16(target, MXC_NF_V1_UNLOCKSTART, 0x0000);
754 target_write_u16(target, MXC_NF_V1_UNLOCKEND, 0xFFFF);
755 } else {
756 target_write_u16(target, MXC_NF_V2_UNLOCKSTART0, 0x0000);
757 target_write_u16(target, MXC_NF_V2_UNLOCKSTART1, 0x0000);
758 target_write_u16(target, MXC_NF_V2_UNLOCKSTART2, 0x0000);
759 target_write_u16(target, MXC_NF_V2_UNLOCKSTART3, 0x0000);
760 target_write_u16(target, MXC_NF_V2_UNLOCKEND0, 0xFFFF);
761 target_write_u16(target, MXC_NF_V2_UNLOCKEND1, 0xFFFF);
762 target_write_u16(target, MXC_NF_V2_UNLOCKEND2, 0xFFFF);
763 target_write_u16(target, MXC_NF_V2_UNLOCKEND3, 0xFFFF);
764 }
765 target_write_u16(target, MXC_NF_FWP, 4);
766
767 /*
768 * 0x0000 means that first SRAM buffer @base_addr will be used
769 */
770 target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
771 /*
772 * address of SRAM buffer
773 */
774 in_sram_address = MXC_NF_MAIN_BUFFER0;
775 sign_of_sequental_byte_read = 0;
776 return ERROR_OK;
777 }
778
779 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
780 {
781 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
782 struct target *target = nand->target;
783 static uint8_t even_byte;
784 uint16_t temp;
785 /*
786 * host-big_endian ??
787 */
788 if (sign_of_sequental_byte_read == 0)
789 even_byte = 0;
790
791 if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
792 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
793 *value = 0;
794 sign_of_sequental_byte_read = 0;
795 even_byte = 0;
796 return ERROR_NAND_OPERATION_FAILED;
797 } else {
798 if (nfc_is_v2())
799 in_sram_address = align_address_v2(nand, in_sram_address);
800
801 target_read_u16(target, in_sram_address, &temp);
802 if (even_byte) {
803 *value = temp >> 8;
804 even_byte = 0;
805 in_sram_address += 2;
806 } else {
807 *value = temp & 0xff;
808 even_byte = 1;
809 }
810 }
811 sign_of_sequental_byte_read = 1;
812 return ERROR_OK;
813 }
814
815 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
816 {
817 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
818 struct target *target = nand->target;
819
820 if (in_sram_address > (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR : MXC_NF_V2_LAST_BUFFADDR)) {
821 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
822 *value = 0;
823 return ERROR_NAND_OPERATION_FAILED;
824 } else {
825 if (nfc_is_v2())
826 in_sram_address = align_address_v2(nand, in_sram_address);
827
828 target_read_u16(target, in_sram_address, value);
829 in_sram_address += 2;
830 }
831 return ERROR_OK;
832 }
833
834 static int poll_for_complete_op(struct nand_device *nand, const char *text)
835 {
836 if (mxc_nand_ready(nand, 1000) == -1) {
837 LOG_ERROR("%s sending timeout", text);
838 return ERROR_NAND_OPERATION_FAILED;
839 }
840 return ERROR_OK;
841 }
842
843 static int validate_target_state(struct nand_device *nand)
844 {
845 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
846 struct target *target = nand->target;
847
848 if (target->state != TARGET_HALTED) {
849 LOG_ERROR(target_not_halted_err_msg);
850 return ERROR_NAND_OPERATION_FAILED;
851 }
852
853 if (mxc_nf_info->flags.target_little_endian !=
854 (target->endianness == TARGET_LITTLE_ENDIAN)) {
855 /*
856 * endianness changed after NAND controller probed
857 */
858 return ERROR_NAND_OPERATION_FAILED;
859 }
860 return ERROR_OK;
861 }
862
863 int ecc_status_v1(struct nand_device *nand)
864 {
865 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
866 struct target *target = nand->target;
867 uint16_t ecc_status;
868
869 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
870 switch (ecc_status & 0x000c) {
871 case 1 << 2:
872 LOG_INFO("main area read with 1 (correctable) error");
873 break;
874 case 2 << 2:
875 LOG_INFO("main area read with more than 1 (incorrectable) error");
876 return ERROR_NAND_OPERATION_FAILED;
877 break;
878 }
879 switch (ecc_status & 0x0003) {
880 case 1:
881 LOG_INFO("spare area read with 1 (correctable) error");
882 break;
883 case 2:
884 LOG_INFO("main area read with more than 1 (incorrectable) error");
885 return ERROR_NAND_OPERATION_FAILED;
886 break;
887 }
888 return ERROR_OK;
889 }
890
891 int ecc_status_v2(struct nand_device *nand)
892 {
893 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
894 struct target *target = nand->target;
895 uint16_t ecc_status;
896 uint8_t no_subpages;
897 uint8_t err;
898
899 no_subpages = nand->page_size >> 9;
900
901 target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
902 do {
903 err = ecc_status & 0xF;
904 if (err > 4) {
905 LOG_INFO("UnCorrectable RS-ECC Error");
906 return ERROR_NAND_OPERATION_FAILED;
907 } else if (err > 0)
908 LOG_INFO("%d Symbol Correctable RS-ECC Error", err);
909 ecc_status >>= 4;
910 } while (--no_subpages);
911 return ERROR_OK;
912 }
913
914 static int do_data_output(struct nand_device *nand)
915 {
916 struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
917 struct target *target = nand->target;
918 int poll_result;
919 switch (mxc_nf_info->fin) {
920 case MXC_NF_FIN_DATAOUT:
921 /*
922 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
923 */
924 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
925 poll_result = poll_for_complete_op(nand, "data output");
926 if (poll_result != ERROR_OK)
927 return poll_result;
928
929 mxc_nf_info->fin = MXC_NF_FIN_NONE;
930 /*
931 * ECC stuff
932 */
933 if (mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE && mxc_nf_info->flags.hw_ecc_enabled) {
934 int ecc_status;
935 if (nfc_is_v1())
936 ecc_status = ecc_status_v1(nand);
937 else
938 ecc_status = ecc_status_v2(nand);
939 if (ecc_status != ERROR_OK)
940 return ecc_status;
941 }
942 break;
943 case MXC_NF_FIN_NONE:
944 break;
945 }
946 return ERROR_OK;
947 }
948
949 struct nand_flash_controller mxc_nand_flash_controller = {
950 .name = "mxc",
951 .nand_device_command = &mxc_nand_device_command,
952 .commands = mxc_nand_command_handler,
953 .init = &mxc_init,
954 .reset = &mxc_reset,
955 .command = &mxc_command,
956 .address = &mxc_address,
957 .write_data = &mxc_write_data,
958 .read_data = &mxc_read_data,
959 .write_page = &mxc_write_page,
960 .read_page = &mxc_read_page,
961 .nand_ready = &mxc_nand_ready,
962 };
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