1 /***************************************************************************
2 * Copyright (C) 2011 by Broadcom Corporation *
3 * Evan Hunter - ehunter@broadcom.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include "target/armv7m.h"
26 static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets
[ARMV7M_NUM_CORE_REGS
] = {
27 { 0x20, 32 }, /* r0 */
28 { 0x24, 32 }, /* r1 */
29 { 0x28, 32 }, /* r2 */
30 { 0x2c, 32 }, /* r3 */
31 { 0x00, 32 }, /* r4 */
32 { 0x04, 32 }, /* r5 */
33 { 0x08, 32 }, /* r6 */
34 { 0x0c, 32 }, /* r7 */
35 { 0x10, 32 }, /* r8 */
36 { 0x14, 32 }, /* r9 */
37 { 0x18, 32 }, /* r10 */
38 { 0x1c, 32 }, /* r11 */
39 { 0x30, 32 }, /* r12 */
41 { 0x34, 32 }, /* lr */
42 { 0x38, 32 }, /* pc */
43 { 0x3c, 32 }, /* xPSR */
46 static const struct stack_register_offset rtos_standard_Cortex_M4F_stack_offsets
[] = {
47 { 0x24, 32 }, /* r0 */
48 { 0x28, 32 }, /* r1 */
49 { 0x2c, 32 }, /* r2 */
50 { 0x30, 32 }, /* r3 */
51 { 0x00, 32 }, /* r4 */
52 { 0x04, 32 }, /* r5 */
53 { 0x08, 32 }, /* r6 */
54 { 0x0c, 32 }, /* r7 */
55 { 0x10, 32 }, /* r8 */
56 { 0x14, 32 }, /* r9 */
57 { 0x18, 32 }, /* r10 */
58 { 0x1c, 32 }, /* r11 */
59 { 0x34, 32 }, /* r12 */
61 { 0x38, 32 }, /* lr */
62 { 0x3c, 32 }, /* pc */
63 { 0x40, 32 }, /* xPSR */
66 static const struct stack_register_offset rtos_standard_Cortex_M4F_FPU_stack_offsets
[] = {
67 { 0x64, 32 }, /* r0 */
68 { 0x68, 32 }, /* r1 */
69 { 0x6c, 32 }, /* r2 */
70 { 0x70, 32 }, /* r3 */
71 { 0x00, 32 }, /* r4 */
72 { 0x04, 32 }, /* r5 */
73 { 0x08, 32 }, /* r6 */
74 { 0x0c, 32 }, /* r7 */
75 { 0x10, 32 }, /* r8 */
76 { 0x14, 32 }, /* r9 */
77 { 0x18, 32 }, /* r10 */
78 { 0x1c, 32 }, /* r11 */
79 { 0x74, 32 }, /* r12 */
81 { 0x78, 32 }, /* lr */
82 { 0x7c, 32 }, /* pc */
83 { 0x80, 32 }, /* xPSR */
87 static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets
[] = {
88 { 0x08, 32 }, /* r0 (a1) */
89 { 0x0c, 32 }, /* r1 (a2) */
90 { 0x10, 32 }, /* r2 (a3) */
91 { 0x14, 32 }, /* r3 (a4) */
92 { 0x18, 32 }, /* r4 (v1) */
93 { 0x1c, 32 }, /* r5 (v2) */
94 { 0x20, 32 }, /* r6 (v3) */
95 { 0x24, 32 }, /* r7 (v4) */
96 { 0x28, 32 }, /* r8 (a1) */
97 { 0x2c, 32 }, /* r9 (sb) */
98 { 0x30, 32 }, /* r10 (sl) */
99 { 0x34, 32 }, /* r11 (fp) */
100 { 0x38, 32 }, /* r12 (ip) */
102 { 0x3c, 32 }, /* lr */
103 { 0x40, 32 }, /* pc */
104 { -1, 96 }, /* FPA1 */
105 { -1, 96 }, /* FPA2 */
106 { -1, 96 }, /* FPA3 */
107 { -1, 96 }, /* FPA4 */
108 { -1, 96 }, /* FPA5 */
109 { -1, 96 }, /* FPA6 */
110 { -1, 96 }, /* FPA7 */
111 { -1, 96 }, /* FPA8 */
112 { -1, 32 }, /* FPS */
113 { 0x04, 32 }, /* CSPR */
116 static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets
[] = {
117 { 0x88, 32 }, /* R0 */
118 { 0x8C, 32 }, /* R1 */
119 { 0x14, 32 }, /* R2 */
120 { 0x18, 32 }, /* R3 */
121 { 0x1C, 32 }, /* R4 */
122 { 0x20, 32 }, /* R5 */
123 { 0x24, 32 }, /* R6 */
124 { 0x28, 32 }, /* R7 */
125 { 0x2C, 32 }, /* R8 */
126 { 0x30, 32 }, /* R9 */
127 { 0x34, 32 }, /* R10 */
128 { 0x38, 32 }, /* R11 */
129 { 0x3C, 32 }, /* R12 */
130 { 0x40, 32 }, /* R13 */
131 { 0x44, 32 }, /* R14 */
132 { 0x48, 32 }, /* R15 */
133 { 0x4C, 32 }, /* R16 */
134 { 0x50, 32 }, /* R17 */
135 { 0x54, 32 }, /* R18 */
136 { 0x58, 32 }, /* R19 */
137 { 0x5C, 32 }, /* R20 */
138 { 0x60, 32 }, /* R21 */
139 { 0x64, 32 }, /* R22 */
140 { 0x68, 32 }, /* R23 */
141 { 0x6C, 32 }, /* R24 */
142 { 0x70, 32 }, /* R25 */
143 { 0x74, 32 }, /* R26 */
144 { 0x78, 32 }, /* R27 */
145 { 0x7C, 32 }, /* R28 */
146 { 0x80, 32 }, /* R29 */
147 { 0x84, 32 }, /* R30 (LP) */
148 { 0x00, 32 }, /* R31 (SP) */
149 { 0x04, 32 }, /* PSW */
150 { 0x08, 32 }, /* IPC */
151 { 0x0C, 32 }, /* IPSW */
152 { 0x10, 32 }, /* IFC_LP */
155 static int64_t rtos_generic_stack_align(struct target
*target
,
156 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
157 int64_t stack_ptr
, int align
)
159 int64_t new_stack_ptr
;
160 int64_t aligned_stack_ptr
;
161 new_stack_ptr
= stack_ptr
- stacking
->stack_growth_direction
*
162 stacking
->stack_registers_size
;
163 aligned_stack_ptr
= new_stack_ptr
& ~((int64_t)align
- 1);
164 if (aligned_stack_ptr
!= new_stack_ptr
&&
165 stacking
->stack_growth_direction
== -1) {
166 /* If we have a downward growing stack, the simple alignment code
167 * above results in a wrong result (since it rounds down to nearest
168 * alignment). We want to round up so add an extra align.
170 aligned_stack_ptr
+= (int64_t)align
;
172 return aligned_stack_ptr
;
175 int64_t rtos_generic_stack_align8(struct target
*target
,
176 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
179 return rtos_generic_stack_align(target
, stack_data
,
180 stacking
, stack_ptr
, 8);
183 /* The Cortex-M3 will indicate that an alignment adjustment
184 * has been done on the stack by setting bit 9 of the stacked xPSR
185 * register. In this case, we can just add an extra 4 bytes to get
186 * to the program stack. Note that some places in the ARM documentation
187 * make this a little unclear but the padding takes place before the
188 * normal exception stacking - so xPSR is always available at a fixed
191 * Relevant documentation:
192 * Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
193 * Cortex-M3 Devices Generic User Guide -> The Cortex-M3 Processor ->
194 * Exception Model -> Exception entry and return -> Exception entry
195 * Cortex-M series processors -> Cortex-M3 -> Revision: xxx ->
196 * Cortex-M3 Devices Generic User Guide -> Cortex-M3 Peripherals ->
197 * System control block -> Configuration and Control Register (STKALIGN)
199 * This is just a helper function for use in the calculate_process_stack
200 * function for a given architecture/rtos.
202 int64_t rtos_Cortex_M_stack_align(struct target
*target
,
203 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
204 int64_t stack_ptr
, size_t xpsr_offset
)
206 const uint32_t ALIGN_NEEDED
= (1 << 9);
208 int64_t new_stack_ptr
;
210 new_stack_ptr
= stack_ptr
- stacking
->stack_growth_direction
*
211 stacking
->stack_registers_size
;
212 xpsr
= (target
->endianness
== TARGET_LITTLE_ENDIAN
) ?
213 le_to_h_u32(&stack_data
[xpsr_offset
]) :
214 be_to_h_u32(&stack_data
[xpsr_offset
]);
215 if ((xpsr
& ALIGN_NEEDED
) != 0) {
216 LOG_DEBUG("XPSR(0x%08" PRIx32
") indicated stack alignment was necessary\r\n",
218 new_stack_ptr
-= (stacking
->stack_growth_direction
* 4);
220 return new_stack_ptr
;
223 static int64_t rtos_standard_Cortex_M3_stack_align(struct target
*target
,
224 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
227 const int XPSR_OFFSET
= 0x3c;
228 return rtos_Cortex_M_stack_align(target
, stack_data
, stacking
,
229 stack_ptr
, XPSR_OFFSET
);
232 static int64_t rtos_standard_Cortex_M4F_stack_align(struct target
*target
,
233 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
236 const int XPSR_OFFSET
= 0x40;
237 return rtos_Cortex_M_stack_align(target
, stack_data
, stacking
,
238 stack_ptr
, XPSR_OFFSET
);
241 static int64_t rtos_standard_Cortex_M4F_FPU_stack_align(struct target
*target
,
242 const uint8_t *stack_data
, const struct rtos_register_stacking
*stacking
,
245 const int XPSR_OFFSET
= 0x80;
246 return rtos_Cortex_M_stack_align(target
, stack_data
, stacking
,
247 stack_ptr
, XPSR_OFFSET
);
251 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking
= {
252 0x40, /* stack_registers_size */
253 -1, /* stack_growth_direction */
254 ARMV7M_NUM_CORE_REGS
, /* num_output_registers */
255 rtos_standard_Cortex_M3_stack_align
, /* stack_alignment */
256 rtos_standard_Cortex_M3_stack_offsets
/* register_offsets */
259 const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking
= {
260 0x44, /* stack_registers_size 4 more for LR*/
261 -1, /* stack_growth_direction */
262 ARMV7M_NUM_CORE_REGS
, /* num_output_registers */
263 rtos_standard_Cortex_M4F_stack_align
, /* stack_alignment */
264 rtos_standard_Cortex_M4F_stack_offsets
/* register_offsets */
267 const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking
= {
268 0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
269 -1, /* stack_growth_direction */
270 ARMV7M_NUM_CORE_REGS
, /* num_output_registers */
271 rtos_standard_Cortex_M4F_FPU_stack_align
, /* stack_alignment */
272 rtos_standard_Cortex_M4F_FPU_stack_offsets
/* register_offsets */
275 const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking
= {
276 0x48, /* stack_registers_size */
277 -1, /* stack_growth_direction */
278 26, /* num_output_registers */
279 rtos_generic_stack_align8
, /* stack_alignment */
280 rtos_standard_Cortex_R4_stack_offsets
/* register_offsets */
283 const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking
= {
284 0x90, /* stack_registers_size */
285 -1, /* stack_growth_direction */
286 32, /* num_output_registers */
287 rtos_generic_stack_align8
, /* stack_alignment */
288 rtos_standard_NDS32_N1068_stack_offsets
/* register_offsets */