2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 #include <target/target.h>
42 static const char target_not_halted_err_msg
[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg
[] =
45 "minimal granularity is one half-word, %" PRId32
" is incorrect";
46 static const char sram_buffer_bounds_err_msg
[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
48 static const char get_status_register_err_msg
[] = "can't get NAND status";
49 static uint32_t in_sram_address
;
50 static unsigned char sign_of_sequental_byte_read
;
52 static int test_iomux_settings(struct target
*target
, uint32_t value
,
53 uint32_t mask
, const char *text
);
54 static int initialize_nf_controller(struct nand_device
*nand
);
55 static int get_next_byte_from_sram_buffer(struct target
*target
, uint8_t *value
);
56 static int get_next_halfword_from_sram_buffer(struct target
*target
,
58 static int poll_for_complete_op(struct target
*target
, const char *text
);
59 static int validate_target_state(struct nand_device
*nand
);
60 static int do_data_output(struct nand_device
*nand
);
62 static int imx31_command(struct nand_device
*nand
, uint8_t command
);
63 static int imx31_address(struct nand_device
*nand
, uint8_t address
);
65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command
)
67 struct mx3_nf_controller
*mx3_nf_info
;
68 mx3_nf_info
= malloc(sizeof(struct mx3_nf_controller
));
69 if (mx3_nf_info
== NULL
) {
70 LOG_ERROR("no memory for nand controller");
74 nand
->controller_priv
= mx3_nf_info
;
77 return ERROR_COMMAND_SYNTAX_ERROR
;
79 * check hwecc requirements
83 hwecc_needed
= strcmp(CMD_ARGV
[2], "hwecc");
84 if (hwecc_needed
== 0)
85 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
87 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
90 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
91 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
92 mx3_nf_info
->flags
.target_little_endian
=
93 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
98 static int imx31_init(struct nand_device
*nand
)
100 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
101 struct target
*target
= nand
->target
;
105 * validate target state
107 int validate_target_result
;
108 validate_target_result
= validate_target_state(nand
);
109 if (validate_target_result
!= ERROR_OK
)
110 return validate_target_result
;
114 uint16_t buffsize_register_content
;
115 target_read_u16(target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
116 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
120 uint32_t pcsr_register_content
;
121 target_read_u32(target
, MX3_PCSR
, &pcsr_register_content
);
122 if (!nand
->bus_width
) {
123 nand
->bus_width
= (pcsr_register_content
& 0x80000000) ? 16 : 8;
125 pcsr_register_content
|= ((nand
->bus_width
== 16) ? 0x80000000 : 0x00000000);
126 target_write_u32(target
, MX3_PCSR
, pcsr_register_content
);
129 if (!nand
->page_size
) {
130 nand
->page_size
= (pcsr_register_content
& 0x40000000) ? 2048 : 512;
132 pcsr_register_content
|= ((nand
->page_size
== 2048) ? 0x40000000 : 0x00000000);
133 target_write_u32(target
, MX3_PCSR
, pcsr_register_content
);
135 if (mx3_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
136 LOG_ERROR("NAND controller have only 1 kb SRAM, "
137 "so pagesize 2048 is incompatible with it");
142 uint32_t cgr_register_content
;
143 target_read_u32(target
, MX3_CCM_CGR2
, &cgr_register_content
);
144 if (!(cgr_register_content
& 0x00000300)) {
145 LOG_ERROR("clock gating to EMI disabled");
151 uint32_t gpr_register_content
;
152 target_read_u32(target
, MX3_GPR
, &gpr_register_content
);
153 if (gpr_register_content
& 0x00000060) {
154 LOG_ERROR("pins mode overrided by GPR");
161 * testing IOMUX settings; must be in "functional-mode output and
162 * functional-mode input" mode
165 test_iomux
= ERROR_OK
;
166 test_iomux
|= test_iomux_settings(target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
167 test_iomux
|= test_iomux_settings(target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
168 test_iomux
|= test_iomux_settings(target
, 0x43fac0c8, 0x0000007f, "d7");
169 if (nand
->bus_width
== 16) {
170 test_iomux
|= test_iomux_settings(target
, 0x43fac0c8, 0x7f7f7f00, "d8,d9,d10");
171 test_iomux
|= test_iomux_settings(target
, 0x43fac0cc, 0x7f7f7f7f, "d11,d12,d13,d14");
172 test_iomux
|= test_iomux_settings(target
, 0x43fac0d0, 0x0000007f, "d15");
174 test_iomux
|= test_iomux_settings(target
, 0x43fac0d0, 0x7f7f7f00, "nfwp,nfce,nfrb");
175 test_iomux
|= test_iomux_settings(target
, 0x43fac0d4, 0x7f7f7f7f,
176 "nfwe,nfre,nfale,nfcle");
177 if (test_iomux
!= ERROR_OK
)
181 initialize_nf_controller(nand
);
185 uint16_t nand_status_content
;
187 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
188 retval
|= imx31_address(nand
, 0x00);
189 retval
|= do_data_output(nand
);
190 if (retval
!= ERROR_OK
) {
191 LOG_ERROR(get_status_register_err_msg
);
194 target_read_u16(target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
195 if (!(nand_status_content
& 0x0080)) {
197 * is host-big-endian correctly ??
199 LOG_INFO("NAND read-only");
200 mx3_nf_info
->flags
.nand_readonly
= 1;
202 mx3_nf_info
->flags
.nand_readonly
= 0;
207 static int imx31_read_data(struct nand_device
*nand
, void *data
)
209 struct target
*target
= nand
->target
;
212 * validate target state
214 int validate_target_result
;
215 validate_target_result
= validate_target_state(nand
);
216 if (validate_target_result
!= ERROR_OK
)
217 return validate_target_result
;
222 * get data from nand chip
224 int try_data_output_from_nand_chip
;
225 try_data_output_from_nand_chip
= do_data_output(nand
);
226 if (try_data_output_from_nand_chip
!= ERROR_OK
)
227 return try_data_output_from_nand_chip
;
230 if (nand
->bus_width
== 16)
231 get_next_halfword_from_sram_buffer(target
, data
);
233 get_next_byte_from_sram_buffer(target
, data
);
238 static int imx31_write_data(struct nand_device
*nand
, uint16_t data
)
240 LOG_ERROR("write_data() not implemented");
241 return ERROR_NAND_OPERATION_FAILED
;
244 static int imx31_reset(struct nand_device
*nand
)
247 * validate target state
249 int validate_target_result
;
250 validate_target_result
= validate_target_state(nand
);
251 if (validate_target_result
!= ERROR_OK
)
252 return validate_target_result
;
253 initialize_nf_controller(nand
);
257 static int imx31_command(struct nand_device
*nand
, uint8_t command
)
259 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
260 struct target
*target
= nand
->target
;
263 * validate target state
265 int validate_target_result
;
266 validate_target_result
= validate_target_state(nand
);
267 if (validate_target_result
!= ERROR_OK
)
268 return validate_target_result
;
272 case NAND_CMD_READOOB
:
273 command
= NAND_CMD_READ0
;
274 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
276 * read_block_data() to
281 command
= NAND_CMD_READ0
;
283 * offset == one half of page size
285 in_sram_address
= MX3_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
287 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
290 target_write_u16(target
, MX3_NF_FCMD
, command
);
292 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
294 target_write_u16(target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
297 poll_result
= poll_for_complete_op(target
, "command");
298 if (poll_result
!= ERROR_OK
)
302 * reset cursor to begin of the buffer
304 sign_of_sequental_byte_read
= 0;
306 case NAND_CMD_READID
:
307 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
308 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
310 case NAND_CMD_STATUS
:
311 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
312 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
315 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
316 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
319 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
324 static int imx31_address(struct nand_device
*nand
, uint8_t address
)
326 struct target
*target
= nand
->target
;
329 * validate target state
331 int validate_target_result
;
332 validate_target_result
= validate_target_state(nand
);
333 if (validate_target_result
!= ERROR_OK
)
334 return validate_target_result
;
337 target_write_u16(target
, MX3_NF_FADDR
, address
);
339 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
341 target_write_u16(target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
344 poll_result
= poll_for_complete_op(target
, "address");
345 if (poll_result
!= ERROR_OK
)
351 static int imx31_nand_ready(struct nand_device
*nand
, int tout
)
353 uint16_t poll_complete_status
;
354 struct target
*target
= nand
->target
;
358 * validate target state
360 int validate_target_result
;
361 validate_target_result
= validate_target_state(nand
);
362 if (validate_target_result
!= ERROR_OK
)
363 return validate_target_result
;
367 target_read_u16(target
, MX3_NF_CFG2
, &poll_complete_status
);
368 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
371 } while (tout
-- > 0);
375 static int imx31_write_page(struct nand_device
*nand
, uint32_t page
,
376 uint8_t *data
, uint32_t data_size
, uint8_t *oob
,
379 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
380 struct target
*target
= nand
->target
;
383 LOG_ERROR(data_block_size_err_msg
, data_size
);
384 return ERROR_NAND_OPERATION_FAILED
;
387 LOG_ERROR(data_block_size_err_msg
, oob_size
);
388 return ERROR_NAND_OPERATION_FAILED
;
391 LOG_ERROR("nothing to program");
392 return ERROR_NAND_OPERATION_FAILED
;
396 * validate target state
399 retval
= validate_target_state(nand
);
400 if (retval
!= ERROR_OK
)
404 int retval
= ERROR_OK
;
405 retval
|= imx31_command(nand
, NAND_CMD_SEQIN
);
406 retval
|= imx31_address(nand
, 0x00);
407 retval
|= imx31_address(nand
, page
& 0xff);
408 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
409 if (nand
->address_cycles
>= 4) {
410 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
411 if (nand
->address_cycles
>= 5)
412 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
414 target_write_buffer(target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
416 if (mx3_nf_info
->flags
.hw_ecc_enabled
) {
418 * part of spare block will be overrided by hardware
421 LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
423 target_write_buffer(target
, MX3_NF_SPARE_BUFFER0
, oob_size
, oob
);
426 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
428 target_write_u16(target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
431 poll_result
= poll_for_complete_op(target
, "data input");
432 if (poll_result
!= ERROR_OK
)
435 retval
|= imx31_command(nand
, NAND_CMD_PAGEPROG
);
436 if (retval
!= ERROR_OK
)
440 * check status register
443 uint16_t nand_status_content
;
445 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
446 retval
|= imx31_address(nand
, 0x00);
447 retval
|= do_data_output(nand
);
448 if (retval
!= ERROR_OK
) {
449 LOG_ERROR(get_status_register_err_msg
);
452 target_read_u16(target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
453 if (nand_status_content
& 0x0001) {
455 * is host-big-endian correctly ??
457 return ERROR_NAND_OPERATION_FAILED
;
464 static int imx31_read_page(struct nand_device
*nand
, uint32_t page
,
465 uint8_t *data
, uint32_t data_size
, uint8_t *oob
,
468 struct target
*target
= nand
->target
;
471 LOG_ERROR(data_block_size_err_msg
, data_size
);
472 return ERROR_NAND_OPERATION_FAILED
;
475 LOG_ERROR(data_block_size_err_msg
, oob_size
);
476 return ERROR_NAND_OPERATION_FAILED
;
481 * validate target state
484 retval
= validate_target_state(nand
);
485 if (retval
!= ERROR_OK
)
489 int retval
= ERROR_OK
;
490 retval
|= imx31_command(nand
, NAND_CMD_READ0
);
491 retval
|= imx31_address(nand
, 0x00);
492 retval
|= imx31_address(nand
, page
& 0xff);
493 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
494 if (nand
->address_cycles
>= 4) {
495 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
496 if (nand
->address_cycles
>= 5) {
497 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
498 retval
|= imx31_command(nand
, NAND_CMD_READSTART
);
501 retval
|= do_data_output(nand
);
502 if (retval
!= ERROR_OK
)
506 target_read_buffer(target
, MX3_NF_MAIN_BUFFER0
, data_size
,
510 target_read_buffer(target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
517 static int test_iomux_settings(struct target
*target
, uint32_t address
,
518 uint32_t mask
, const char *text
)
520 uint32_t register_content
;
521 target_read_u32(target
, address
, ®ister_content
);
522 if ((register_content
& mask
) != (0x12121212 & mask
)) {
523 LOG_ERROR("IOMUX for {%s} is bad", text
);
529 static int initialize_nf_controller(struct nand_device
*nand
)
531 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
532 struct target
*target
= nand
->target
;
534 * resets NAND flash controller in zero time ? I dont know.
536 target_write_u16(target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
539 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
540 if (target
->endianness
== TARGET_BIG_ENDIAN
)
541 work_mode
|= MX3_NF_BIT_BE_EN
;
542 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
543 work_mode
|= MX3_NF_BIT_ECC_EN
;
544 target_write_u16(target
, MX3_NF_CFG1
, work_mode
);
547 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
549 target_write_u16(target
, MX3_NF_BUFCFG
, 2);
552 target_read_u16(target
, MX3_NF_FWP
, &temp
);
553 if ((temp
& 0x0007) == 1) {
554 LOG_ERROR("NAND flash is tight-locked, reset needed");
560 * unlock NAND flash for write
562 target_write_u16(target
, MX3_NF_FWP
, 4);
563 target_write_u16(target
, MX3_NF_LOCKSTART
, 0x0000);
564 target_write_u16(target
, MX3_NF_LOCKEND
, 0xFFFF);
566 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
568 target_write_u16(target
, MX3_NF_BUFADDR
, 0x0000);
570 * address of SRAM buffer
572 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
573 sign_of_sequental_byte_read
= 0;
577 static int get_next_byte_from_sram_buffer(struct target
*target
, uint8_t *value
)
579 static uint8_t even_byte
;
583 if (sign_of_sequental_byte_read
== 0)
585 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
) {
586 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
588 sign_of_sequental_byte_read
= 0;
590 return ERROR_NAND_OPERATION_FAILED
;
593 target_read_u16(target
, in_sram_address
, &temp
);
597 in_sram_address
+= 2;
599 *value
= temp
& 0xff;
603 sign_of_sequental_byte_read
= 1;
607 static int get_next_halfword_from_sram_buffer(struct target
*target
,
610 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
) {
611 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
613 return ERROR_NAND_OPERATION_FAILED
;
615 target_read_u16(target
, in_sram_address
, value
);
616 in_sram_address
+= 2;
621 static int poll_for_complete_op(struct target
*target
, const char *text
)
623 uint16_t poll_complete_status
;
624 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++) {
626 target_read_u16(target
, MX3_NF_CFG2
, &poll_complete_status
);
627 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
630 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
)) {
631 LOG_ERROR("%s sending timeout", text
);
632 return ERROR_NAND_OPERATION_FAILED
;
637 static int validate_target_state(struct nand_device
*nand
)
639 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
640 struct target
*target
= nand
->target
;
642 if (target
->state
!= TARGET_HALTED
) {
643 LOG_ERROR(target_not_halted_err_msg
);
644 return ERROR_NAND_OPERATION_FAILED
;
647 if (mx3_nf_info
->flags
.target_little_endian
!=
648 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
650 * endianness changed after NAND controller probed
652 return ERROR_NAND_OPERATION_FAILED
;
657 static int do_data_output(struct nand_device
*nand
)
659 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
660 struct target
*target
= nand
->target
;
661 switch (mx3_nf_info
->fin
) {
662 case MX3_NF_FIN_DATAOUT
:
664 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
666 target_write_u16 (target
, MX3_NF_CFG2
,
667 MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info
->optype
));
670 poll_result
= poll_for_complete_op(target
, "data output");
671 if (poll_result
!= ERROR_OK
)
674 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
678 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
679 && mx3_nf_info
->flags
.hw_ecc_enabled
) {
681 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
682 switch (ecc_status
& 0x000c) {
684 LOG_DEBUG("main area readed with 1 (correctable) error");
687 LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
688 return ERROR_NAND_OPERATION_FAILED
;
691 switch (ecc_status
& 0x0003) {
693 LOG_DEBUG("spare area readed with 1 (correctable) error");
696 LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
697 return ERROR_NAND_OPERATION_FAILED
;
702 case MX3_NF_FIN_NONE
:
708 struct nand_flash_controller imx31_nand_flash_controller
= {
710 .usage
= "nand device imx31 target noecc|hwecc",
711 .nand_device_command
= &imx31_nand_device_command
,
713 .reset
= &imx31_reset
,
714 .command
= &imx31_command
,
715 .address
= &imx31_address
,
716 .write_data
= &imx31_write_data
,
717 .read_data
= &imx31_read_data
,
718 .write_page
= &imx31_write_page
,
719 .read_page
= &imx31_read_page
,
720 .nand_ready
= &imx31_nand_ready
,