src/target/arm_adi_v5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifndef ARM_ADI_V5_H
  24 #define ARM_ADI_V5_H
  25
  26 #include "arm_jtag.h"
  27
  28 #define DAP_IR_DPACC    0xA
  29 #define DAP_IR_APACC    0xB
  30
  31 #define DPAP_WRITE              0
  32 #define DPAP_READ               1
  33 #define DP_ZERO                 0
  34 #define DP_CTRL_STAT    0x4
  35 #define DP_SELECT               0x8
  36 #define DP_RDBUFF               0xC
  37
  38 #define CORUNDETECT             (1 << 0)
  39 #define SSTICKYORUN             (1 << 1)
  40 #define SSTICKYERR              (1 << 5)
  41 #define CDBGRSTREQ              (1 << 26)
  42 #define CDBGRSTACK              (1 << 27)
  43 #define CDBGPWRUPREQ    (1 << 28)
  44 #define CDBGPWRUPACK    (1 << 29)
  45 #define CSYSPWRUPREQ    (1 << 30)
  46 #define CSYSPWRUPACK    (1 << 31)
  47
  48 #define AP_REG_CSW              0x00
  49 #define AP_REG_TAR              0x04
  50 #define AP_REG_DRW              0x0C
  51 #define AP_REG_BD0              0x10
  52 #define AP_REG_BD1              0x14
  53 #define AP_REG_BD2              0x18
  54 #define AP_REG_BD3              0x1C
  55 #define AP_REG_DBGROMA  0xF8
  56 #define AP_REG_IDR              0xFC
  57
  58 #define CSW_8BIT                0
  59 #define CSW_16BIT               1
  60 #define CSW_32BIT               2
  61
  62 #define CSW_ADDRINC_MASK        (3 << 4)
  63 #define CSW_ADDRINC_OFF         0
  64 #define CSW_ADDRINC_SINGLE      (1 << 4)
  65 #define CSW_ADDRINC_PACKED      (2 << 4)
  66 #define CSW_HPROT                       (1 << 25)
  67 #define CSW_MASTER_DEBUG        (1 << 29)
  68 #define CSW_DBGSWENABLE         (1 << 31)
  69
  70 /* transaction mode */
  71 #define TRANS_MODE_NONE                 0
  72 /* Transaction waits for previous to complete */
  73 #define TRANS_MODE_ATOMIC               1
  74 /* Freerunning transactions with delays and overrun checking */
  75 #define TRANS_MODE_COMPOSITE    2
  76
  77 struct swjdp_reg
  78 {
  79         int addr;
  80         struct arm_jtag *jtag_info;
  81 };
  82
  83 struct swjdp_common
  84 {
  85         struct arm_jtag *jtag_info;
  86         /* Control config */
  87         uint32_t dp_ctrl_stat;
  88         /* Support for several AP's in one DAP */
  89         uint32_t apsel;
  90         /* Register select cache */
  91         uint32_t dp_select_value;
  92         uint32_t ap_csw_value;
  93         uint32_t ap_tar_value;
  94         /* information about current pending SWjDP-AHBAP transaction */
  95         uint8_t  trans_mode;
  96         uint8_t  trans_rw;
  97         uint8_t  ack;
  98         /* extra tck clocks for memory bus access */
  99         uint32_t        memaccess_tck;
 100         /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 101         uint32_t tar_autoincr_block;
 102
 103 };
 104
 105 /* Accessor function for currently selected DAP-AP number */
 106 static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
 107 {
 108         return (uint8_t)(swjdp ->apsel >> 24);
 109 }
 110
 111 /* Internal functions used in the module, partial transactions, use with caution */
 112 int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr);
 113 /* int swjdp_write_apacc(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr); */
 114 int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr);
 115 /* int swjdp_read_apacc(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr); */
 116 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar);
 117 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel);
 118
 119 int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t addr, uint8_t* out_buf);
 120 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t addr, uint32_t value);
 121 int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t addr, uint8_t *in_buf);
 122 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t addr, uint32_t *value);
 123
 124 /* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
 125 int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
 126
 127 /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
 128 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
 129 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
 130
 131 /* MEM-AP memory mapped bus transfers, single registers, complete transactions */
 132 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
 133                 uint32_t address, uint32_t *value);
 134 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
 135                 uint32_t address, uint32_t value);
 136
 137 /* MEM-AP memory mapped bus block transfers */
 138 int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
 139                 uint8_t *buffer, int count, uint32_t address);
 140 int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
 141                 uint8_t *buffer, int count, uint32_t address);
 142 int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
 143                 uint8_t *buffer, int count, uint32_t address);
 144
 145 int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
 146                 uint8_t *buffer, int count, uint32_t address);
 147 int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
 148                 uint8_t *buffer, int count, uint32_t address);
 149 int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
 150                 uint8_t *buffer, int count, uint32_t address);
 151
 152 /* Initialisation of the debug system, power domains and registers */
 153 int ahbap_debugport_init(struct swjdp_common *swjdp);
 154
 155
 156 /* Commands for user dap access */
 157 int dap_info_command(struct command_context *cmd_ctx,
 158                 struct swjdp_common *swjdp, int apsel);
 159
 160 #define DAP_COMMAND_HANDLER(name) \
 161                 COMMAND_HELPER(name, struct swjdp_common *swjdp)
 162 DAP_COMMAND_HANDLER(dap_baseaddr_command);
 163 DAP_COMMAND_HANDLER(dap_memaccess_command);
 164 DAP_COMMAND_HANDLER(dap_apsel_command);
 165 DAP_COMMAND_HANDLER(dap_apid_command);
 166
 167 #endif