jtag/core, target: unregister JTAG events
[openocd.git] / src / target / armv8_opcodes.c
blob6887b295399da30c841f72df7ab92ede0c3d61ee
1 /*
2 * Copyright (C) 2015 by Matthias Welwarsky <matthias.welwarsky@sysgo.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifdef HAVE_CONFIG_H
17 #include "config.h"
18 #endif
20 #include <stdint.h>
21 #include <stdbool.h>
23 #include "armv8.h"
24 #include "armv8_opcodes.h"
26 static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
27 [READ_REG_CTR] = ARMV8_MRS(SYSTEM_CTR, 0),
28 [READ_REG_CLIDR] = ARMV8_MRS(SYSTEM_CLIDR, 0),
29 [READ_REG_CSSELR] = ARMV8_MRS(SYSTEM_CSSELR, 0),
30 [READ_REG_CCSIDR] = ARMV8_MRS(SYSTEM_CCSIDR, 0),
31 [WRITE_REG_CSSELR] = ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
32 [READ_REG_MPIDR] = ARMV8_MRS(SYSTEM_MPIDR, 0),
33 [READ_REG_DTRRX] = ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
34 [WRITE_REG_DTRTX] = ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0),
35 [WRITE_REG_DSPSR] = ARMV8_MSR_DSPSR(0),
36 [READ_REG_DSPSR] = ARMV8_MRS_DSPSR(0),
37 [ARMV8_OPC_DSB_SY] = ARMV8_DSB_SY,
38 [ARMV8_OPC_DCPS] = ARMV8_DCPS(0, 11),
39 [ARMV8_OPC_DRPS] = ARMV8_DRPS,
40 [ARMV8_OPC_ISB_SY] = ARMV8_ISB,
41 [ARMV8_OPC_DCCISW] = ARMV8_SYS(SYSTEM_DCCISW, 0),
42 [ARMV8_OPC_DCCIVAC] = ARMV8_SYS(SYSTEM_DCCIVAC, 0),
43 [ARMV8_OPC_ICIVAU] = ARMV8_SYS(SYSTEM_ICIVAU, 0),
44 [ARMV8_OPC_HLT] = ARMV8_HLT(11),
45 [ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP(1, 0),
46 [ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP(1, 0),
47 [ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP(1, 0),
48 [ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP(1, 0),
49 [ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP(1, 0),
50 [ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP(1, 0),
53 static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
54 [READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1),
55 [READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
56 [READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
57 [READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
58 [WRITE_REG_CSSELR] = ARMV4_5_MCR(15, 2, 0, 0, 0, 0),
59 [READ_REG_MPIDR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
60 [READ_REG_DTRRX] = ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
61 [WRITE_REG_DTRTX] = ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
62 [WRITE_REG_DSPSR] = ARMV8_MCR_DSPSR(0),
63 [READ_REG_DSPSR] = ARMV8_MRC_DSPSR(0),
64 [ARMV8_OPC_DSB_SY] = ARMV8_DSB_SY_T1,
65 [ARMV8_OPC_DCPS] = ARMV8_DCPS_T1(0),
66 [ARMV8_OPC_DRPS] = ARMV8_ERET_T1,
67 [ARMV8_OPC_ISB_SY] = ARMV8_ISB_SY_T1,
68 [ARMV8_OPC_DCCISW] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
69 [ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
70 [ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
71 [ARMV8_OPC_HLT] = ARMV8_HLT_A1(11),
72 [ARMV8_OPC_LDRB_IP] = ARMV4_5_LDRB_IP(1, 0),
73 [ARMV8_OPC_LDRH_IP] = ARMV4_5_LDRH_IP(1, 0),
74 [ARMV8_OPC_LDRW_IP] = ARMV4_5_LDRW_IP(1, 0),
75 [ARMV8_OPC_STRB_IP] = ARMV4_5_STRB_IP(1, 0),
76 [ARMV8_OPC_STRH_IP] = ARMV4_5_STRH_IP(1, 0),
77 [ARMV8_OPC_STRW_IP] = ARMV4_5_STRW_IP(1, 0),
80 void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
82 if (state_is_aarch64)
83 armv8->opcodes = &a64_opcodes[0];
84 else
85 armv8->opcodes = &t32_opcodes[0];
88 uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode code)
90 if ((int)code >= ARMV8_OPC_NUM)
91 return -1;
93 return *(armv8->opcodes + code);