src/target/armv4_5_mmu.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifndef OPENOCD_TARGET_ARMV4_5_MMU_H
  20 #define OPENOCD_TARGET_ARMV4_5_MMU_H
  21
  22 #include "armv4_5_cache.h"
  23
  24 struct target;
  25
  26 struct armv4_5_mmu_common {
  27         int (*get_ttb)(struct target *target, uint32_t *result);
  28         int (*read_memory)(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  29         int (*write_memory)(struct target *target, target_addr_t address,
  30                             uint32_t size, uint32_t count, const uint8_t *buffer);
  31         int (*disable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
  32         int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
  33         struct armv4_5_cache_common armv4_5_cache;
  34         int has_tiny_pages;
  35         int mmu_enabled;
  36 };
  37
  38 int armv4_5_mmu_translate_va(struct target *target,
  39                 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va,
  40                 uint32_t *cb, uint32_t *val);
  41
  42 int armv4_5_mmu_read_physical(struct target *target,
  43                 struct armv4_5_mmu_common *armv4_5_mmu,
  44                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
  45
  46 int armv4_5_mmu_write_physical(struct target *target,
  47                 struct armv4_5_mmu_common *armv4_5_mmu,
  48                 uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
  49
  50 enum {
  51         ARMV4_5_MMU_ENABLED = 0x1,
  52         ARMV4_5_ALIGNMENT_CHECK = 0x2,
  53         ARMV4_5_MMU_S_BIT = 0x100,
  54         ARMV4_5_MMU_R_BIT = 0x200
  55 };
  56
  57 #endif /* OPENOCD_TARGET_ARMV4_5_MMU_H */