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drivers/ulink: Group adapter commands
[openocd.git] / src / target / nds32_cmd.c
blob69c28ac783d1af399a885dabc36bc7efd04b5487
1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
18
19 #ifdef HAVE_CONFIG_H
20 #include "config.h"
21 #endif
22
23 #include <helper/command.h>
24 #include "nds32.h"
25 #include "nds32_aice.h"
26 #include "nds32_disassembler.h"
27
28 extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
29 extern uint32_t nds32_edm_ops_num;
30
31 static const char *const nds_memory_access_name[] = {
32 "BUS",
33 "CPU",
34 };
35
36 static const char *const nds_memory_select_name[] = {
37 "AUTO",
38 "MEM",
39 "ILM",
40 "DLM",
41 };
42
43 COMMAND_HANDLER(handle_nds32_dssim_command)
44 {
45 struct target *target = get_current_target(CMD_CTX);
46 struct nds32 *nds32 = target_to_nds32(target);
47
48 if (!is_nds32(nds32)) {
49 command_print(CMD, "current target isn't an Andes core");
50 return ERROR_FAIL;
51 }
52
53 if (CMD_ARGC > 0) {
54 if (strcmp(CMD_ARGV[0], "on") == 0)
55 nds32->step_isr_enable = true;
56 if (strcmp(CMD_ARGV[0], "off") == 0)
57 nds32->step_isr_enable = false;
58 }
59
60 command_print(CMD, "%s: $INT_MASK.DSSIM: %d", target_name(target),
61 nds32->step_isr_enable);
62
63 return ERROR_OK;
64 }
65
66 COMMAND_HANDLER(handle_nds32_memory_access_command)
67 {
68 struct target *target = get_current_target(CMD_CTX);
69 struct nds32 *nds32 = target_to_nds32(target);
70 struct aice_port_s *aice = target_to_aice(target);
71 struct nds32_memory *memory = &(nds32->memory);
72
73 if (!is_nds32(nds32)) {
74 command_print(CMD, "current target isn't an Andes core");
75 return ERROR_FAIL;
76 }
77
78 if (CMD_ARGC > 0) {
79 if (strcmp(CMD_ARGV[0], "bus") == 0)
80 memory->access_channel = NDS_MEMORY_ACC_BUS;
81 else if (strcmp(CMD_ARGV[0], "cpu") == 0)
82 memory->access_channel = NDS_MEMORY_ACC_CPU;
83 else /* default access channel is NDS_MEMORY_ACC_CPU */
84 memory->access_channel = NDS_MEMORY_ACC_CPU;
85
86 LOG_DEBUG("memory access channel is changed to %s",
87 nds_memory_access_name[memory->access_channel]);
88
89 aice_memory_access(aice, memory->access_channel);
90 } else {
91 command_print(CMD, "%s: memory access channel: %s",
92 target_name(target),
93 nds_memory_access_name[memory->access_channel]);
94 }
95
96 return ERROR_OK;
97 }
98
99 COMMAND_HANDLER(handle_nds32_memory_mode_command)
100 {
101 struct target *target = get_current_target(CMD_CTX);
102 struct nds32 *nds32 = target_to_nds32(target);
103 struct aice_port_s *aice = target_to_aice(target);
104
105 if (!is_nds32(nds32)) {
106 command_print(CMD, "current target isn't an Andes core");
107 return ERROR_FAIL;
108 }
109
110 if (CMD_ARGC > 0) {
111
112 if (nds32->edm.access_control == false) {
113 command_print(CMD, "%s does not support ACC_CTL. "
114 "Set memory mode to MEMORY", target_name(target));
115 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
116 } else if (nds32->edm.direct_access_local_memory == false) {
117 command_print(CMD, "%s does not support direct access "
118 "local memory. Set memory mode to MEMORY",
119 target_name(target));
120 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
121
122 /* set to ACC_CTL */
123 aice_memory_mode(aice, nds32->memory.mode);
124 } else {
125 if (strcmp(CMD_ARGV[0], "auto") == 0) {
126 nds32->memory.mode = NDS_MEMORY_SELECT_AUTO;
127 } else if (strcmp(CMD_ARGV[0], "mem") == 0) {
128 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
129 } else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
130 if (nds32->memory.ilm_base == 0)
131 command_print(CMD, "%s does not support ILM",
132 target_name(target));
133 else
134 nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
135 } else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
136 if (nds32->memory.dlm_base == 0)
137 command_print(CMD, "%s does not support DLM",
138 target_name(target));
139 else
140 nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
141 }
142
143 /* set to ACC_CTL */
144 aice_memory_mode(aice, nds32->memory.mode);
145 }
146 }
147
148 command_print(CMD, "%s: memory mode: %s",
149 target_name(target),
150 nds_memory_select_name[nds32->memory.mode]);
151
152 return ERROR_OK;
153 }
154
155 COMMAND_HANDLER(handle_nds32_cache_command)
156 {
157 struct target *target = get_current_target(CMD_CTX);
158 struct nds32 *nds32 = target_to_nds32(target);
159 struct aice_port_s *aice = target_to_aice(target);
160 struct nds32_cache *icache = &(nds32->memory.icache);
161 struct nds32_cache *dcache = &(nds32->memory.dcache);
162 int result;
163
164 if (!is_nds32(nds32)) {
165 command_print(CMD, "current target isn't an Andes core");
166 return ERROR_FAIL;
167 }
168
169 if (CMD_ARGC > 0) {
170
171 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
172 if ((dcache->line_size != 0) && (dcache->enable == true)) {
173 /* D$ write back */
174 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
175 if (result != ERROR_OK) {
176 command_print(CMD, "%s: Write back data cache...failed",
177 target_name(target));
178 return result;
179 }
180
181 command_print(CMD, "%s: Write back data cache...done",
182 target_name(target));
183
184 /* D$ invalidate */
185 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
186 if (result != ERROR_OK) {
187 command_print(CMD, "%s: Invalidate data cache...failed",
188 target_name(target));
189 return result;
190 }
191
192 command_print(CMD, "%s: Invalidate data cache...done",
193 target_name(target));
194 } else {
195 if (dcache->line_size == 0)
196 command_print(CMD, "%s: No data cache",
197 target_name(target));
198 else
199 command_print(CMD, "%s: Data cache disabled",
200 target_name(target));
201 }
202
203 if ((icache->line_size != 0) && (icache->enable == true)) {
204 /* I$ invalidate */
205 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
206 if (result != ERROR_OK) {
207 command_print(CMD, "%s: Invalidate instruction cache...failed",
208 target_name(target));
209 return result;
210 }
211
212 command_print(CMD, "%s: Invalidate instruction cache...done",
213 target_name(target));
214 } else {
215 if (icache->line_size == 0)
216 command_print(CMD, "%s: No instruction cache",
217 target_name(target));
218 else
219 command_print(CMD, "%s: Instruction cache disabled",
220 target_name(target));
221 }
222 } else
223 command_print(CMD, "No valid parameter");
224 }
225
226 return ERROR_OK;
227 }
228
229 COMMAND_HANDLER(handle_nds32_icache_command)
230 {
231 struct target *target = get_current_target(CMD_CTX);
232 struct nds32 *nds32 = target_to_nds32(target);
233 struct aice_port_s *aice = target_to_aice(target);
234 struct nds32_cache *icache = &(nds32->memory.icache);
235 int result;
236
237 if (!is_nds32(nds32)) {
238 command_print(CMD, "current target isn't an Andes core");
239 return ERROR_FAIL;
240 }
241
242 if (CMD_ARGC > 0) {
243
244 if (icache->line_size == 0) {
245 command_print(CMD, "%s: No instruction cache",
246 target_name(target));
247 return ERROR_OK;
248 }
249
250 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
251 if (icache->enable == true) {
252 /* I$ invalidate */
253 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
254 if (result != ERROR_OK) {
255 command_print(CMD, "%s: Invalidate instruction cache...failed",
256 target_name(target));
257 return result;
258 }
259
260 command_print(CMD, "%s: Invalidate instruction cache...done",
261 target_name(target));
262 } else {
263 command_print(CMD, "%s: Instruction cache disabled",
264 target_name(target));
265 }
266 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
267 uint32_t value;
268 nds32_get_mapped_reg(nds32, IR8, &value);
269 nds32_set_mapped_reg(nds32, IR8, value | 0x1);
270 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
271 uint32_t value;
272 nds32_get_mapped_reg(nds32, IR8, &value);
273 nds32_set_mapped_reg(nds32, IR8, value & ~0x1);
274 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
275 /* TODO: dump cache content */
276 } else {
277 command_print(CMD, "%s: No valid parameter", target_name(target));
278 }
279 }
280
281 return ERROR_OK;
282 }
283
284 COMMAND_HANDLER(handle_nds32_dcache_command)
285 {
286 struct target *target = get_current_target(CMD_CTX);
287 struct nds32 *nds32 = target_to_nds32(target);
288 struct aice_port_s *aice = target_to_aice(target);
289 struct nds32_cache *dcache = &(nds32->memory.dcache);
290 int result;
291
292 if (!is_nds32(nds32)) {
293 command_print(CMD, "current target isn't an Andes core");
294 return ERROR_FAIL;
295 }
296
297 if (CMD_ARGC > 0) {
298
299 if (dcache->line_size == 0) {
300 command_print(CMD, "%s: No data cache", target_name(target));
301 return ERROR_OK;
302 }
303
304 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
305 if (dcache->enable == true) {
306 /* D$ write back */
307 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
308 if (result != ERROR_OK) {
309 command_print(CMD, "%s: Write back data cache...failed",
310 target_name(target));
311 return result;
312 }
313
314 command_print(CMD, "%s: Write back data cache...done",
315 target_name(target));
316
317 /* D$ invalidate */
318 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
319 if (result != ERROR_OK) {
320 command_print(CMD, "%s: Invalidate data cache...failed",
321 target_name(target));
322 return result;
323 }
324
325 command_print(CMD, "%s: Invalidate data cache...done",
326 target_name(target));
327 } else {
328 command_print(CMD, "%s: Data cache disabled",
329 target_name(target));
330 }
331 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
332 uint32_t value;
333 nds32_get_mapped_reg(nds32, IR8, &value);
334 nds32_set_mapped_reg(nds32, IR8, value | 0x2);
335 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
336 uint32_t value;
337 nds32_get_mapped_reg(nds32, IR8, &value);
338 nds32_set_mapped_reg(nds32, IR8, value & ~0x2);
339 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
340 /* TODO: dump cache content */
341 } else {
342 command_print(CMD, "%s: No valid parameter", target_name(target));
343 }
344 }
345
346 return ERROR_OK;
347 }
348
349 COMMAND_HANDLER(handle_nds32_auto_break_command)
350 {
351 struct target *target = get_current_target(CMD_CTX);
352 struct nds32 *nds32 = target_to_nds32(target);
353
354 if (!is_nds32(nds32)) {
355 command_print(CMD, "current target isn't an Andes core");
356 return ERROR_FAIL;
357 }
358
359 if (CMD_ARGC > 0) {
360 if (strcmp(CMD_ARGV[0], "on") == 0)
361 nds32->auto_convert_hw_bp = true;
362 if (strcmp(CMD_ARGV[0], "off") == 0)
363 nds32->auto_convert_hw_bp = false;
364 }
365
366 if (nds32->auto_convert_hw_bp)
367 command_print(CMD, "%s: convert sw break to hw break on ROM: on",
368 target_name(target));
369 else
370 command_print(CMD, "%s: convert sw break to hw break on ROM: off",
371 target_name(target));
372
373 return ERROR_OK;
374 }
375
376 COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
377 {
378 struct target *target = get_current_target(CMD_CTX);
379 struct nds32 *nds32 = target_to_nds32(target);
380
381 if (!is_nds32(nds32)) {
382 command_print(CMD, "current target isn't an Andes core");
383 return ERROR_FAIL;
384 }
385
386 if (CMD_ARGC > 0) {
387 if (strcmp(CMD_ARGV[0], "on") == 0)
388 nds32->virtual_hosting = true;
389 if (strcmp(CMD_ARGV[0], "off") == 0)
390 nds32->virtual_hosting = false;
391 }
392
393 if (nds32->virtual_hosting)
394 command_print(CMD, "%s: virtual hosting: on", target_name(target));
395 else
396 command_print(CMD, "%s: virtual hosting: off", target_name(target));
397
398 return ERROR_OK;
399 }
400
401 COMMAND_HANDLER(handle_nds32_global_stop_command)
402 {
403 struct target *target = get_current_target(CMD_CTX);
404 struct nds32 *nds32 = target_to_nds32(target);
405
406 if (!is_nds32(nds32)) {
407 command_print(CMD, "current target isn't an Andes core");
408 return ERROR_FAIL;
409 }
410
411 if (CMD_ARGC > 0) {
412 if (strcmp(CMD_ARGV[0], "on") == 0)
413 nds32->global_stop = true;
414 if (strcmp(CMD_ARGV[0], "off") == 0)
415 nds32->global_stop = false;
416 }
417
418 if (nds32->global_stop)
419 LOG_INFO("%s: global stop: on", target_name(target));
420 else
421 LOG_INFO("%s: global stop: off", target_name(target));
422
423 return ERROR_OK;
424 }
425
426 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
427 {
428 struct target *target = get_current_target(CMD_CTX);
429 struct nds32 *nds32 = target_to_nds32(target);
430
431 if (!is_nds32(nds32)) {
432 command_print(CMD, "current target isn't an Andes core");
433 return ERROR_FAIL;
434 }
435
436 if (CMD_ARGC > 0) {
437 if (strcmp(CMD_ARGV[0], "on") == 0)
438 nds32->soft_reset_halt = true;
439 if (strcmp(CMD_ARGV[0], "off") == 0)
440 nds32->soft_reset_halt = false;
441 }
442
443 if (nds32->soft_reset_halt)
444 LOG_INFO("%s: soft-reset-halt: on", target_name(target));
445 else
446 LOG_INFO("%s: soft-reset-halt: off", target_name(target));
447
448 return ERROR_OK;
449 }
450
451 COMMAND_HANDLER(handle_nds32_boot_time_command)
452 {
453 struct target *target = get_current_target(CMD_CTX);
454 struct nds32 *nds32 = target_to_nds32(target);
455
456 if (!is_nds32(nds32)) {
457 command_print(CMD, "current target isn't an Andes core");
458 return ERROR_FAIL;
459 }
460
461 if (CMD_ARGC > 0)
462 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time);
463
464 return ERROR_OK;
465 }
466
467 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
468 {
469 struct target *target = get_current_target(CMD_CTX);
470 struct nds32 *nds32 = target_to_nds32(target);
471
472 if (!is_nds32(nds32)) {
473 command_print(CMD, "current target isn't an Andes core");
474 return ERROR_FAIL;
475 }
476
477 nds32->edm_passcode = strdup(CMD_ARGV[0]);
478
479 return ERROR_OK;
480 }
481
482 COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
483 {
484 struct target *target = get_current_target(CMD_CTX);
485 struct nds32 *nds32 = target_to_nds32(target);
486
487 if (!is_nds32(nds32)) {
488 command_print(CMD, "current target isn't an Andes core");
489 return ERROR_FAIL;
490 }
491
492 if (CMD_ARGC > 1) {
493
494 uint32_t misc_reg_no;
495 uint32_t data;
496
497 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no);
498 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data);
499
500 if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM)
501 return ERROR_FAIL;
502
503 /* Just save the operation. Execute it in nds32_login() */
504 nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no;
505 nds32_edm_ops[nds32_edm_ops_num].value = data;
506 nds32_edm_ops_num++;
507 } else
508 return ERROR_FAIL;
509
510 return ERROR_OK;
511 }
512
513 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
514 {
515 struct target *target = get_current_target(CMD_CTX);
516 struct nds32 *nds32 = target_to_nds32(target);
517
518 if (!is_nds32(nds32)) {
519 command_print(CMD, "current target isn't an Andes core");
520 return ERROR_FAIL;
521 }
522
523 if (CMD_ARGC > 0) {
524 if (strcmp(CMD_ARGV[0], "on") == 0)
525 nds32->reset_halt_as_examine = true;
526 if (strcmp(CMD_ARGV[0], "off") == 0)
527 nds32->reset_halt_as_examine = false;
528 }
529
530 return ERROR_OK;
531 }
532
533 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
534 {
535 struct target *target = get_current_target(CMD_CTX);
536 struct nds32 *nds32 = target_to_nds32(target);
537
538 if (!is_nds32(nds32)) {
539 command_print(CMD, "current target isn't an Andes core");
540 return ERROR_FAIL;
541 }
542
543 if (CMD_ARGC > 0) {
544 if (strcmp(CMD_ARGV[0], "on") == 0)
545 nds32->keep_target_edm_ctl = true;
546 if (strcmp(CMD_ARGV[0], "off") == 0)
547 nds32->keep_target_edm_ctl = false;
548 }
549
550 return ERROR_OK;
551 }
552
553 COMMAND_HANDLER(handle_nds32_decode_command)
554 {
555 struct target *target = get_current_target(CMD_CTX);
556 struct nds32 *nds32 = target_to_nds32(target);
557
558 if (!is_nds32(nds32)) {
559 command_print(CMD, "current target isn't an Andes core");
560 return ERROR_FAIL;
561 }
562
563 if (CMD_ARGC > 1) {
564
565 uint32_t addr;
566 uint32_t insn_count;
567 uint32_t opcode;
568 uint32_t read_addr;
569 uint32_t i;
570 struct nds32_instruction instruction;
571
572 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
573 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count);
574
575 read_addr = addr;
576 i = 0;
577 while (i < insn_count) {
578 if (nds32_read_opcode(nds32, read_addr, &opcode) != ERROR_OK)
579 return ERROR_FAIL;
580 if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK)
581 return ERROR_FAIL;
582
583 command_print(CMD, "%s", instruction.text);
584
585 read_addr += instruction.instruction_size;
586 i++;
587 }
588 } else if (CMD_ARGC == 1) {
589
590 uint32_t addr;
591 uint32_t opcode;
592 struct nds32_instruction instruction;
593
594 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
595
596 if (nds32_read_opcode(nds32, addr, &opcode) != ERROR_OK)
597 return ERROR_FAIL;
598 if (nds32_evaluate_opcode(nds32, opcode, addr, &instruction) != ERROR_OK)
599 return ERROR_FAIL;
600
601 command_print(CMD, "%s", instruction.text);
602 } else
603 return ERROR_FAIL;
604
605 return ERROR_OK;
606 }
607
608 COMMAND_HANDLER(handle_nds32_word_access_mem_command)
609 {
610 struct target *target = get_current_target(CMD_CTX);
611 struct nds32 *nds32 = target_to_nds32(target);
612
613 if (!is_nds32(nds32)) {
614 command_print(CMD, "current target isn't an Andes core");
615 return ERROR_FAIL;
616 }
617
618 if (CMD_ARGC > 0) {
619 if (strcmp(CMD_ARGV[0], "on") == 0)
620 nds32->word_access_mem = true;
621 if (strcmp(CMD_ARGV[0], "off") == 0)
622 nds32->word_access_mem = false;
623 }
624
625 return ERROR_OK;
626 }
627
628 COMMAND_HANDLER(handle_nds32_query_target_command)
629 {
630 struct target *target = get_current_target(CMD_CTX);
631 struct nds32 *nds32 = target_to_nds32(target);
632
633 if (!is_nds32(nds32)) {
634 command_print(CMD, "current target isn't an Andes core");
635 return ERROR_FAIL;
636 }
637
638 command_print(CMD, "OCD");
639
640 return ERROR_OK;
641 }
642
643 COMMAND_HANDLER(handle_nds32_query_endian_command)
644 {
645 struct target *target = get_current_target(CMD_CTX);
646 struct nds32 *nds32 = target_to_nds32(target);
647
648 if (!is_nds32(nds32)) {
649 command_print(CMD, "current target isn't an Andes core");
650 return ERROR_FAIL;
651 }
652
653 uint32_t value_psw;
654 nds32_get_mapped_reg(nds32, IR0, &value_psw);
655
656 if (value_psw & 0x20)
657 command_print(CMD, "%s: BE", target_name(target));
658 else
659 command_print(CMD, "%s: LE", target_name(target));
660
661 return ERROR_OK;
662 }
663
664 COMMAND_HANDLER(handle_nds32_query_cpuid_command)
665 {
666 struct target *target = get_current_target(CMD_CTX);
667 struct nds32 *nds32 = target_to_nds32(target);
668
669 if (!is_nds32(nds32)) {
670 command_print(CMD, "current target isn't an Andes core");
671 return ERROR_FAIL;
672 }
673
674 command_print(CMD, "CPUID: %s", target_name(target));
675
676 return ERROR_OK;
677 }
678
679 static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
680 {
681 const char *cmd_name = Jim_GetString(argv[0], NULL);
682
683 struct jim_getopt_info goi;
684 jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
685
686 if (goi.argc < 3) {
687 Jim_SetResultFormatted(goi.interp,
688 "usage: %s <address> <count> <data>", cmd_name);
689 return JIM_ERR;
690 }
691
692 int e;
693 jim_wide address;
694 e = jim_getopt_wide(&goi, &address);
695 if (e != JIM_OK)
696 return e;
697
698 jim_wide count;
699 e = jim_getopt_wide(&goi, &count);
700 if (e != JIM_OK)
701 return e;
702
703 uint32_t *data = malloc(count * sizeof(uint32_t));
704 if (!data)
705 return JIM_ERR;
706
707 jim_wide i;
708 for (i = 0; i < count; i++) {
709 jim_wide tmp;
710 e = jim_getopt_wide(&goi, &tmp);
711 if (e != JIM_OK) {
712 free(data);
713 return e;
714 }
715 data[i] = (uint32_t)tmp;
716 }
717
718 /* all args must be consumed */
719 if (goi.argc != 0) {
720 free(data);
721 return JIM_ERR;
722 }
723
724 struct command_context *cmd_ctx = current_command_context(interp);
725 assert(cmd_ctx);
726 struct target *target = get_current_target(cmd_ctx);
727 int result;
728
729 result = target_write_buffer(target, address, count * 4, (const uint8_t *)data);
730
731 free(data);
732
733 return result;
734 }
735
736 static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
737 {
738 const char *cmd_name = Jim_GetString(argv[0], NULL);
739
740 struct jim_getopt_info goi;
741 jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
742
743 if (goi.argc < 3) {
744 Jim_SetResultFormatted(goi.interp,
745 "usage: %s # of pairs [<address> <data>]+", cmd_name);
746 return JIM_ERR;
747 }
748
749 int e;
750 jim_wide num_of_pairs;
751 e = jim_getopt_wide(&goi, &num_of_pairs);
752 if (e != JIM_OK)
753 return e;
754
755 struct command_context *cmd_ctx = current_command_context(interp);
756 assert(cmd_ctx);
757 struct target *target = get_current_target(cmd_ctx);
758 struct aice_port_s *aice = target_to_aice(target);
759 int result;
760 uint32_t address;
761 uint32_t data;
762 jim_wide i;
763
764 aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK);
765 for (i = 0; i < num_of_pairs; i++) {
766 jim_wide tmp;
767 e = jim_getopt_wide(&goi, &tmp);
768 if (e != JIM_OK)
769 break;
770 address = (uint32_t)tmp;
771
772 e = jim_getopt_wide(&goi, &tmp);
773 if (e != JIM_OK)
774 break;
775 data = (uint32_t)tmp;
776
777 result = target_write_buffer(target, address, 4, (const uint8_t *)&data);
778 if (result != ERROR_OK)
779 break;
780 }
781 aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL);
782
783 /* all args must be consumed */
784 if (goi.argc != 0)
785 return JIM_ERR;
786
787 return ERROR_OK;
788 }
789
790 static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
791 {
792 const char *cmd_name = Jim_GetString(argv[0], NULL);
793
794 struct jim_getopt_info goi;
795 jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
796
797 if (goi.argc < 2) {
798 Jim_SetResultFormatted(goi.interp,
799 "usage: %s <address> <count>", cmd_name);
800 return JIM_ERR;
801 }
802
803 int e;
804 jim_wide address;
805 e = jim_getopt_wide(&goi, &address);
806 if (e != JIM_OK)
807 return e;
808
809 jim_wide count;
810 e = jim_getopt_wide(&goi, &count);
811 if (e != JIM_OK)
812 return e;
813
814 /* all args must be consumed */
815 if (goi.argc != 0)
816 return JIM_ERR;
817
818 struct command_context *cmd_ctx = current_command_context(interp);
819 assert(cmd_ctx);
820 struct target *target = get_current_target(cmd_ctx);
821 uint32_t *data = malloc(count * sizeof(uint32_t));
822 int result;
823 result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
824 char data_str[12];
825
826 jim_wide i;
827 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
828 for (i = 0; i < count; i++) {
829 sprintf(data_str, "0x%08" PRIx32 " ", data[i]);
830 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
831 }
832
833 free(data);
834
835 return result;
836 }
837
838 static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
839 {
840 const char *cmd_name = Jim_GetString(argv[0], NULL);
841
842 struct jim_getopt_info goi;
843 jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
844
845 if (goi.argc < 1) {
846 Jim_SetResultFormatted(goi.interp,
847 "usage: %s <edm_sr_name>", cmd_name);
848 return JIM_ERR;
849 }
850
851 int e;
852 const char *edm_sr_name;
853 int edm_sr_name_len;
854 e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len);
855 if (e != JIM_OK)
856 return e;
857
858 /* all args must be consumed */
859 if (goi.argc != 0)
860 return JIM_ERR;
861
862 uint32_t edm_sr_number;
863 uint32_t edm_sr_value;
864 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
865 edm_sr_number = NDS_EDM_SR_EDM_DTR;
866 else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0)
867 edm_sr_number = NDS_EDM_SR_EDMSW;
868 else
869 return ERROR_FAIL;
870
871 struct command_context *cmd_ctx = current_command_context(interp);
872 assert(cmd_ctx);
873 struct target *target = get_current_target(cmd_ctx);
874 struct aice_port_s *aice = target_to_aice(target);
875 char data_str[11];
876
877 aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value);
878
879 sprintf(data_str, "0x%08" PRIx32, edm_sr_value);
880 Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
881 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
882
883 return ERROR_OK;
884 }
885
886 static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
887 {
888 const char *cmd_name = Jim_GetString(argv[0], NULL);
889
890 struct jim_getopt_info goi;
891 jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
892
893 if (goi.argc < 2) {
894 Jim_SetResultFormatted(goi.interp,
895 "usage: %s <edm_sr_name> <value>", cmd_name);
896 return JIM_ERR;
897 }
898
899 int e;
900 const char *edm_sr_name;
901 int edm_sr_name_len;
902 e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len);
903 if (e != JIM_OK)
904 return e;
905
906 jim_wide value;
907 e = jim_getopt_wide(&goi, &value);
908 if (e != JIM_OK)
909 return e;
910
911 /* all args must be consumed */
912 if (goi.argc != 0)
913 return JIM_ERR;
914
915 uint32_t edm_sr_number;
916 if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
917 edm_sr_number = NDS_EDM_SR_EDM_DTR;
918 else
919 return ERROR_FAIL;
920
921 struct command_context *cmd_ctx = current_command_context(interp);
922 assert(cmd_ctx);
923 struct target *target = get_current_target(cmd_ctx);
924 struct aice_port_s *aice = target_to_aice(target);
925
926 aice_write_debug_reg(aice, edm_sr_number, value);
927
928 return ERROR_OK;
929 }
930
931 static const struct command_registration nds32_query_command_handlers[] = {
932 {
933 .name = "target",
934 .handler = handle_nds32_query_target_command,
935 .mode = COMMAND_EXEC,
936 .usage = "",
937 .help = "reply 'OCD' for gdb to identify server-side is OpenOCD",
938 },
939 {
940 .name = "endian",
941 .handler = handle_nds32_query_endian_command,
942 .mode = COMMAND_EXEC,
943 .usage = "",
944 .help = "query target endian",
945 },
946 {
947 .name = "cpuid",
948 .handler = handle_nds32_query_cpuid_command,
949 .mode = COMMAND_EXEC,
950 .usage = "",
951 .help = "query CPU ID",
952 },
953
954 COMMAND_REGISTRATION_DONE
955 };
956
957 static const struct command_registration nds32_exec_command_handlers[] = {
958 {
959 .name = "dssim",
960 .handler = handle_nds32_dssim_command,
961 .mode = COMMAND_EXEC,
962 .usage = "['on'|'off']",
963 .help = "display/change $INT_MASK.DSSIM status",
964 },
965 {
966 .name = "mem_access",
967 .handler = handle_nds32_memory_access_command,
968 .mode = COMMAND_EXEC,
969 .usage = "['bus'|'cpu']",
970 .help = "display/change memory access channel",
971 },
972 {
973 .name = "mem_mode",
974 .handler = handle_nds32_memory_mode_command,
975 .mode = COMMAND_EXEC,
976 .usage = "['auto'|'mem'|'ilm'|'dlm']",
977 .help = "display/change memory mode",
978 },
979 {
980 .name = "cache",
981 .handler = handle_nds32_cache_command,
982 .mode = COMMAND_EXEC,
983 .usage = "['invalidate']",
984 .help = "cache control",
985 },
986 {
987 .name = "icache",
988 .handler = handle_nds32_icache_command,
989 .mode = COMMAND_EXEC,
990 .usage = "['invalidate'|'enable'|'disable'|'dump']",
991 .help = "icache control",
992 },
993 {
994 .name = "dcache",
995 .handler = handle_nds32_dcache_command,
996 .mode = COMMAND_EXEC,
997 .usage = "['invalidate'|'enable'|'disable'|'dump']",
998 .help = "dcache control",
999 },
1000 {
1001 .name = "auto_break",
1002 .handler = handle_nds32_auto_break_command,
1003 .mode = COMMAND_EXEC,
1004 .usage = "['on'|'off']",
1005 .help = "convert software breakpoints to hardware breakpoints if needed",
1006 },
1007 {
1008 .name = "virtual_hosting",
1009 .handler = handle_nds32_virtual_hosting_command,
1010 .mode = COMMAND_ANY,
1011 .usage = "['on'|'off']",
1012 .help = "turn on/off virtual hosting",
1013 },
1014 {
1015 .name = "global_stop",
1016 .handler = handle_nds32_global_stop_command,
1017 .mode = COMMAND_ANY,
1018 .usage = "['on'|'off']",
1019 .help = "turn on/off global stop. After turning on, every load/store "
1020 "instructions will be stopped to check memory access.",
1021 },
1022 {
1023 .name = "soft_reset_halt",
1024 .handler = handle_nds32_soft_reset_halt_command,
1025 .mode = COMMAND_ANY,
1026 .usage = "['on'|'off']",
1027 .help = "as issuing rest-halt, to use soft-reset-halt or not."
1028 "the feature is for backward-compatible.",
1029 },
1030 {
1031 .name = "boot_time",
1032 .handler = handle_nds32_boot_time_command,
1033 .mode = COMMAND_CONFIG,
1034 .usage = "milliseconds",
1035 .help = "set the period to wait after srst.",
1036 },
1037 {
1038 .name = "login_edm_passcode",
1039 .handler = handle_nds32_login_edm_passcode_command,
1040 .mode = COMMAND_CONFIG,
1041 .usage = "passcode",
1042 .help = "set EDM passcode for secure MCU debugging.",
1043 },
1044 {
1045 .name = "login_edm_operation",
1046 .handler = handle_nds32_login_edm_operation_command,
1047 .mode = COMMAND_CONFIG,
1048 .usage = "misc_reg_no value",
1049 .help = "add EDM operations for secure MCU debugging.",
1050 },
1051 {
1052 .name = "reset_halt_as_init",
1053 .handler = handle_nds32_reset_halt_as_init_command,
1054 .mode = COMMAND_CONFIG,
1055 .usage = "['on'|'off']",
1056 .help = "reset halt as openocd init.",
1057 },
1058 {
1059 .name = "keep_target_edm_ctl",
1060 .handler = handle_nds32_keep_target_edm_ctl_command,
1061 .mode = COMMAND_CONFIG,
1062 .usage = "['on'|'off']",
1063 .help = "Backup/Restore target EDM_CTL register.",
1064 },
1065 {
1066 .name = "decode",
1067 .handler = handle_nds32_decode_command,
1068 .mode = COMMAND_EXEC,
1069 .usage = "address icount",
1070 .help = "decode instruction.",
1071 },
1072 {
1073 .name = "word_access_mem",
1074 .handler = handle_nds32_word_access_mem_command,
1075 .mode = COMMAND_ANY,
1076 .usage = "['on'|'off']",
1077 .help = "Always use word-aligned address to access memory.",
1078 },
1079 {
1080 .name = "bulk_write",
1081 .jim_handler = jim_nds32_bulk_write,
1082 .mode = COMMAND_EXEC,
1083 .help = "Write multiple 32-bit words to target memory",
1084 .usage = "address count data",
1085 },
1086 {
1087 .name = "multi_write",
1088 .jim_handler = jim_nds32_multi_write,
1089 .mode = COMMAND_EXEC,
1090 .help = "Write multiple addresses/words to target memory",
1091 .usage = "num_of_pairs [address data]+",
1092 },
1093 {
1094 .name = "bulk_read",
1095 .jim_handler = jim_nds32_bulk_read,
1096 .mode = COMMAND_EXEC,
1097 .help = "Read multiple 32-bit words from target memory",
1098 .usage = "address count",
1099 },
1100 {
1101 .name = "read_edmsr",
1102 .jim_handler = jim_nds32_read_edm_sr,
1103 .mode = COMMAND_EXEC,
1104 .help = "Read EDM system register",
1105 .usage = "['edmsw'|'edm_dtr']",
1106 },
1107 {
1108 .name = "write_edmsr",
1109 .jim_handler = jim_nds32_write_edm_sr,
1110 .mode = COMMAND_EXEC,
1111 .help = "Write EDM system register",
1112 .usage = "['edm_dtr'] value",
1113 },
1114 {
1115 .name = "query",
1116 .mode = COMMAND_EXEC,
1117 .help = "Andes query command group",
1118 .usage = "",
1119 .chain = nds32_query_command_handlers,
1120 },
1121
1122 COMMAND_REGISTRATION_DONE
1123 };
1124
1125 const struct command_registration nds32_command_handlers[] = {
1126 {
1127 .name = "nds",
1128 .mode = COMMAND_ANY,
1129 .help = "Andes command group",
1130 .usage = "",
1131 .chain = nds32_exec_command_handlers,
1132 },
1133 COMMAND_REGISTRATION_DONE
1134 };
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