src/flash/nor/ambiqmicro.c

   1 /******************************************************************************
   2  *
   3  * @file ambiqmicro.c
   4  *
   5  * @brief Ambiq Micro flash driver.
   6  *
   7  *****************************************************************************/
   8
   9 /******************************************************************************
  10  * Copyright (c) 2015, David Racine <dracine at ambiqmicro.com>
  11  *
  12  * Copyright (c) 2016, Rick Foos <rfoos at solengtech.com>
  13  *
  14  * Copyright (c) 2015-2016, Ambiq Micro, Inc.
  15  *
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are met:
  20  *
  21  * 1. Redistributions of source code must retain the above copyright notice,
  22  * this list of conditions and the following disclaimer.
  23  *
  24  * 2. Redistributions in binary form must reproduce the above copyright
  25  * notice, this list of conditions and the following disclaimer in the
  26  * documentation and/or other materials provided with the distribution.
  27  *
  28  * 3. Neither the name of the copyright holder nor the names of its
  29  * contributors may be used to endorse or promote products derived from this
  30  * software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  35  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  36  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  37  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  38  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  39  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  40  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  41  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  42  * POSSIBILITY OF SUCH DAMAGE.
  43  *
  44  *****************************************************************************/
  45 #ifdef HAVE_CONFIG_H
  46 #include "config.h"
  47 #endif
  48
  49 #include "jtag/interface.h"
  50 #include "imp.h"
  51 #include "target/algorithm.h"
  52 #include "target/armv7m.h"
  53 #include "target/cortex_m.h"
  54
  55 /** Check error, log error. */
  56 #define CHECK_STATUS(rc, msg) { \
  57                 if (rc != ERROR_OK) { \
  58                         LOG_ERROR("status(%d):%s\n", rc, msg); } }
  59
  60 /*
  61  * Address and Key defines.
  62  */
  63 #define PROGRAM_KEY      (0x12344321)
  64 #define OTP_PROGRAM_KEY  (0x87655678)
  65
  66 #define FLASH_PROGRAM_MAIN_FROM_SRAM                0x0800005d
  67 #define FLASH_PROGRAM_OTP_FROM_SRAM                 0x08000061
  68 #define FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM       0x08000065
  69 #define FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM       0x08000069
  70
  71
  72 static const uint32_t apollo_flash_size[] = {
  73         1 << 15,
  74         1 << 16,
  75         1 << 17,
  76         1 << 18,
  77         1 << 19,
  78         1 << 20,
  79         1 << 21
  80 };
  81
  82 static const uint32_t apollo_sram_size[] = {
  83         1 << 15,
  84         1 << 16,
  85         1 << 17,
  86         1 << 18,
  87         1 << 19,
  88         1 << 20,
  89         1 << 21
  90 };
  91
  92 struct ambiqmicro_flash_bank {
  93         /* chip id register */
  94
  95         uint32_t probed;
  96
  97         const char *target_name;
  98         uint8_t target_class;
  99
 100         uint32_t sramsiz;
 101         uint32_t flshsiz;
 102
 103         /* flash geometry */
 104         uint32_t num_pages;
 105         uint32_t pagesize;
 106         uint32_t pages_in_lockregion;
 107
 108         /* nv memory bits */
 109         uint16_t num_lockbits;
 110
 111         /* main clock status */
 112         uint32_t rcc;
 113         uint32_t rcc2;
 114         uint8_t mck_valid;
 115         uint8_t xtal_mask;
 116         uint32_t iosc_freq;
 117         uint32_t mck_freq;
 118         const char *iosc_desc;
 119         const char *mck_desc;
 120 };
 121
 122 static struct {
 123         uint8_t class;
 124         uint8_t partno;
 125         const char *partname;
 126 } ambiqmicroParts[6] = {
 127         {0xFF, 0x00, "Unknown"},
 128         {0x01, 0x00, "Apollo"},
 129         {0x02, 0x00, "Apollo2"},
 130         {0x03, 0x00, "Unknown"},
 131         {0x04, 0x00, "Unknown"},
 132         {0x05, 0x00, "Apollo"},
 133 };
 134
 135 static char *ambiqmicroClassname[6] = {
 136         "Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
 137 };
 138
 139 /***************************************************************************
 140 *       openocd command interface                                              *
 141 ***************************************************************************/
 142
 143 /* flash_bank ambiqmicro <base> <size> 0 0 <target#>
 144  */
 145 FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
 146 {
 147         struct ambiqmicro_flash_bank *ambiqmicro_info;
 148
 149         if (CMD_ARGC < 6)
 150                 return ERROR_COMMAND_SYNTAX_ERROR;
 151
 152         ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
 153
 154         bank->driver_priv = ambiqmicro_info;
 155
 156         ambiqmicro_info->target_name = "Unknown target";
 157
 158         /* part wasn't probed yet */
 159         ambiqmicro_info->probed = 0;
 160
 161         return ERROR_OK;
 162 }
 163
 164 static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
 165 {
 166         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 167         int printed;
 168         char *classname;
 169
 170         if (ambiqmicro_info->probed == 0) {
 171                 LOG_ERROR("Target not probed");
 172                 return ERROR_FLASH_BANK_NOT_PROBED;
 173         }
 174
 175         /* Check class name in range. */
 176         if (ambiqmicro_info->target_class < sizeof(ambiqmicroClassname))
 177                 classname = ambiqmicroClassname[ambiqmicro_info->target_class];
 178         else
 179                 classname = ambiqmicroClassname[0];
 180
 181         printed = snprintf(buf,
 182                 buf_size,
 183                 "\nAmbiq Micro information: Chip is "
 184                 "class %d (%s) %s\n",
 185                 ambiqmicro_info->target_class,
 186                 classname,
 187                 ambiqmicro_info->target_name);
 188
 189         if ((printed < 0))
 190                 return ERROR_BUF_TOO_SMALL;
 191         return ERROR_OK;
 192 }
 193
 194 /***************************************************************************
 195 *       chip identification and status                                         *
 196 ***************************************************************************/
 197
 198 /* Fill in driver info structure */
 199 static int ambiqmicro_read_part_info(struct flash_bank *bank)
 200 {
 201         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 202         struct target *target = bank->target;
 203         uint32_t PartNum = 0;
 204         int retval;
 205
 206         /*
 207          * Read Part Number.
 208          */
 209         retval = target_read_u32(target, 0x40020000, &PartNum);
 210         if (retval != ERROR_OK) {
 211                 LOG_ERROR("status(0x%x):Could not read PartNum.\n", retval);
 212                 /* Set PartNum to default device */
 213                 PartNum = 0;
 214         }
 215         LOG_DEBUG("Part number: 0x%x", PartNum);
 216
 217         /*
 218          * Determine device class.
 219          */
 220         ambiqmicro_info->target_class = (PartNum & 0xFF000000) >> 24;
 221
 222         switch (ambiqmicro_info->target_class) {
 223                 case 1:         /* 1 - Apollo */
 224                 case 5:         /* 5 - Apollo Bootloader */
 225                         bank->base = bank->bank_number * 0x40000;
 226                         ambiqmicro_info->pagesize = 2048;
 227                         ambiqmicro_info->flshsiz =
 228                         apollo_flash_size[(PartNum & 0x00F00000) >> 20];
 229                         ambiqmicro_info->sramsiz =
 230                         apollo_sram_size[(PartNum & 0x000F0000) >> 16];
 231                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 232                         ambiqmicro_info->pagesize;
 233                         if (ambiqmicro_info->num_pages > 128) {
 234                                 ambiqmicro_info->num_pages = 128;
 235                                 ambiqmicro_info->flshsiz = 1024 * 256;
 236                         }
 237                         break;
 238
 239                 default:
 240                         LOG_INFO("Unknown Class. Using Apollo-64 as default.");
 241
 242                         bank->base = bank->bank_number * 0x40000;
 243                         ambiqmicro_info->pagesize = 2048;
 244                         ambiqmicro_info->flshsiz = apollo_flash_size[1];
 245                         ambiqmicro_info->sramsiz = apollo_sram_size[0];
 246                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 247                         ambiqmicro_info->pagesize;
 248                         if (ambiqmicro_info->num_pages > 128) {
 249                                 ambiqmicro_info->num_pages = 128;
 250                                 ambiqmicro_info->flshsiz = 1024 * 256;
 251                         }
 252                         break;
 253
 254         }
 255
 256         if (ambiqmicro_info->target_class <
 257                 (sizeof(ambiqmicroParts)/sizeof(ambiqmicroParts[0])))
 258                 ambiqmicro_info->target_name =
 259                         ambiqmicroParts[ambiqmicro_info->target_class].partname;
 260         else
 261                 ambiqmicro_info->target_name =
 262                         ambiqmicroParts[0].partname;
 263
 264         LOG_DEBUG("num_pages: %d, pagesize: %d, flash: %d, sram: %d",
 265                 ambiqmicro_info->num_pages,
 266                 ambiqmicro_info->pagesize,
 267                 ambiqmicro_info->flshsiz,
 268                 ambiqmicro_info->sramsiz);
 269
 270         return ERROR_OK;
 271 }
 272
 273 /***************************************************************************
 274 *       flash operations                                                       *
 275 ***************************************************************************/
 276
 277 static int ambiqmicro_protect_check(struct flash_bank *bank)
 278 {
 279         struct ambiqmicro_flash_bank *ambiqmicro = bank->driver_priv;
 280         int status = ERROR_OK;
 281         uint32_t i;
 282
 283
 284         if (ambiqmicro->probed == 0) {
 285                 LOG_ERROR("Target not probed");
 286                 return ERROR_FLASH_BANK_NOT_PROBED;
 287         }
 288
 289         for (i = 0; i < (unsigned) bank->num_sectors; i++)
 290                 bank->sectors[i].is_protected = -1;
 291
 292         return status;
 293 }
 294 /** Read flash status from bootloader. */
 295 static int check_flash_status(struct target *target, uint32_t address)
 296 {
 297         uint32_t retflash;
 298         int rc;
 299         rc = target_read_u32(target, address, &retflash);
 300         /* target connection failed. */
 301         if (rc != ERROR_OK) {
 302                 LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
 303                         __FILE__, __LINE__, __func__, rc);
 304                 return rc;
 305         }
 306         /* target flash failed, unknown cause. */
 307         if (retflash != 0) {
 308                 LOG_ERROR("Flash not happy: status(0x%x)", retflash);
 309                 return ERROR_FLASH_OPERATION_FAILED;
 310         }
 311         return ERROR_OK;
 312 }
 313
 314 static int ambiqmicro_exec_command(struct target *target,
 315         uint32_t command,
 316         uint32_t flash_return_address)
 317 {
 318         int retval, retflash;
 319
 320         retval = target_resume(
 321                 target,
 322                 false,
 323                 command,
 324                 true,
 325                 true);
 326
 327         CHECK_STATUS(retval, "error executing ambiqmicro command");
 328
 329         /*
 330          * Wait for halt.
 331          */
 332         for (;; ) {
 333                 target_poll(target);
 334                 if (target->state == TARGET_HALTED)
 335                         break;
 336                 else if (target->state == TARGET_RUNNING ||
 337                         target->state == TARGET_DEBUG_RUNNING) {
 338                         /*
 339                          * Keep polling until target halts.
 340                          */
 341                         target_poll(target);
 342                         alive_sleep(100);
 343                         LOG_DEBUG("state = %d", target->state);
 344                 } else {
 345                         LOG_ERROR("Target not halted or running %d", target->state);
 346                         break;
 347                 }
 348         }
 349
 350         /*
 351          * Read return value, flash error takes precedence.
 352          */
 353         retflash = check_flash_status(target, flash_return_address);
 354         if (retflash != ERROR_OK)
 355                 retval = retflash;
 356
 357         /* Return code from target_resume OR flash. */
 358         return retval;
 359 }
 360
 361 static int ambiqmicro_mass_erase(struct flash_bank *bank)
 362 {
 363         struct target *target = NULL;
 364         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 365         int retval = ERROR_OK;
 366
 367         ambiqmicro_info = bank->driver_priv;
 368         target = bank->target;
 369
 370         if (target->state != TARGET_HALTED) {
 371                 LOG_ERROR("Target not halted");
 372                 return ERROR_TARGET_NOT_HALTED;
 373         }
 374
 375         if (ambiqmicro_info->probed == 0) {
 376                 LOG_ERROR("Target not probed");
 377                 return ERROR_FLASH_BANK_NOT_PROBED;
 378         }
 379
 380         /*
 381          * Clear Bootloader bit.
 382          */
 383         retval = target_write_u32(target, 0x400201a0, 0x0);
 384         CHECK_STATUS(retval, "error clearing bootloader bit.");
 385
 386         /*
 387          * Set up the SRAM.
 388          */
 389
 390         /*
 391          * Bank.
 392          */
 393         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 394         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 395
 396         /*
 397          * Write Key.
 398          */
 399         retval = target_write_u32(target, 0x10000004, PROGRAM_KEY);
 400         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 401
 402         /*
 403          * Breakpoint.
 404          */
 405         retval = target_write_u32(target, 0x10000008, 0xfffffffe);
 406         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 407
 408         /*
 409          * Erase the main array.
 410          */
 411         LOG_INFO("Mass erase on bank %d.", bank->bank_number);
 412
 413         /*
 414          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 415          */
 416         retval = ambiqmicro_exec_command(target, FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM, 0x10000008);
 417         CHECK_STATUS(retval, "error executing ambiqmicro flash mass erase.");
 418         if (retval != ERROR_OK)
 419                 return retval;
 420
 421         /*
 422          * Set Bootloader bit, regardless of command execution.
 423          */
 424         retval = target_write_u32(target, 0x400201a0, 0x1);
 425         CHECK_STATUS(retval, "error setting bootloader bit.");
 426
 427         return retval;
 428 }
 429
 430
 431 static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
 432 {
 433         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 434         struct target *target = bank->target;
 435         uint32_t retval = ERROR_OK;
 436
 437         if (bank->target->state != TARGET_HALTED) {
 438                 LOG_ERROR("Target not halted");
 439                 return ERROR_TARGET_NOT_HALTED;
 440         }
 441
 442         if (ambiqmicro_info->probed == 0) {
 443                 LOG_ERROR("Target not probed");
 444                 return ERROR_FLASH_BANK_NOT_PROBED;
 445         }
 446
 447         /*
 448          * Check pages.
 449          * Fix num_pages for the device.
 450          */
 451         if ((first < 0) || (last < first) || (last >= (int)ambiqmicro_info->num_pages))
 452                 return ERROR_FLASH_SECTOR_INVALID;
 453
 454         /*
 455          * Just Mass Erase if all pages are given.
 456          * TODO: Fix num_pages for the device
 457          */
 458         if ((first == 0) && (last == ((int)ambiqmicro_info->num_pages-1)))
 459                 return ambiqmicro_mass_erase(bank);
 460
 461         /*
 462          * Clear Bootloader bit.
 463          */
 464         retval = target_write_u32(target, 0x400201a0, 0x0);
 465         CHECK_STATUS(retval, "error clearing bootloader bit.");
 466
 467         /*
 468          * Set up the SRAM.
 469          */
 470
 471         /*
 472          * Bank.
 473          */
 474         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 475         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 476
 477         /*
 478          * Number of pages to erase.
 479          */
 480         retval = target_write_u32(target, 0x10000004, 1 + (last-first));
 481         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 482
 483         /*
 484          * Write Key.
 485          */
 486         retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 487         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 488
 489         /*
 490          * Breakpoint.
 491          */
 492         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 493         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 494
 495         /*
 496          * Pointer to flash address.
 497          */
 498         retval = target_write_u32(target, 0x10000010, first);
 499         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 500         if (retval != ERROR_OK)
 501                 return retval;
 502
 503         /*
 504          * Erase the pages.
 505          */
 506         LOG_INFO("Erasing pages %d to %d on bank %d", first, last, bank->bank_number);
 507
 508         /*
 509          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 510          */
 511         retval = ambiqmicro_exec_command(target, FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM, 0x1000000C);
 512         CHECK_STATUS(retval, "error executing flash page erase");
 513         if (retval != ERROR_OK)
 514                 return retval;
 515
 516         LOG_INFO("%d pages erased!", 1+(last-first));
 517
 518         if (first == 0) {
 519                 /*
 520                  * Set Bootloader bit.
 521                  */
 522                 retval = target_write_u32(target, 0x400201a0, 0x1);
 523                 CHECK_STATUS(retval, "error setting bootloader bit.");
 524                 if (retval != ERROR_OK)
 525                         return retval;
 526         }
 527
 528         return retval;
 529 }
 530
 531 static int ambiqmicro_protect(struct flash_bank *bank, int set, int first, int last)
 532 {
 533         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 534          * struct target *target = bank->target; */
 535
 536         /*
 537          * TODO
 538          */
 539         LOG_INFO("Not yet implemented");
 540
 541         if (bank->target->state != TARGET_HALTED) {
 542                 LOG_ERROR("Target not halted");
 543                 return ERROR_TARGET_NOT_HALTED;
 544         }
 545
 546         return ERROR_OK;
 547 }
 548
 549 static int ambiqmicro_write_block(struct flash_bank *bank,
 550         const uint8_t *buffer, uint32_t offset, uint32_t count)
 551 {
 552         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv; */
 553         struct target *target = bank->target;
 554         uint32_t address = bank->base + offset;
 555         uint32_t buffer_pointer = 0x10000010;
 556         uint32_t maxbuffer;
 557         uint32_t thisrun_count;
 558         int retval = ERROR_OK;
 559
 560         if (((count%4) != 0) || ((offset%4) != 0)) {
 561                 LOG_ERROR("write block must be multiple of 4 bytes in offset & length");
 562                 return ERROR_FAIL;
 563         }
 564
 565         /*
 566          * Max buffer size for this device.
 567          * Hard code 6kB for the buffer.
 568          */
 569         maxbuffer = 0x1800;
 570
 571         LOG_INFO("Flashing main array");
 572
 573         while (count > 0) {
 574                 if (count > maxbuffer)
 575                         thisrun_count = maxbuffer;
 576                 else
 577                         thisrun_count = count;
 578
 579                 /*
 580                  * Set up the SRAM.
 581                  */
 582
 583                 /*
 584                  * Pointer to flash.
 585                  */
 586                 retval = target_write_u32(target, 0x10000000, address);
 587                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 588
 589                 /*
 590                  * Number of 32-bit words to program.
 591                  */
 592                 retval = target_write_u32(target, 0x10000004, thisrun_count/4);
 593                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 594
 595                 /*
 596                  * Write Key.
 597                  */
 598                 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 599                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 600
 601                 /*
 602                  * Breakpoint.
 603                  */
 604                 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 605                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 606
 607                 /*
 608                  * Write Buffer.
 609                  */
 610                 retval = target_write_buffer(target, buffer_pointer, thisrun_count, buffer);
 611
 612                 if (retval != ERROR_OK) {
 613                         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 614                         break;
 615                 }
 616
 617                 LOG_DEBUG("address = 0x%08x", address);
 618
 619                 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
 620                 CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
 621                 if (retval != ERROR_OK)
 622                         break;
 623                 buffer += thisrun_count;
 624                 address += thisrun_count;
 625                 count -= thisrun_count;
 626         }
 627
 628
 629         LOG_INFO("Main array flashed");
 630
 631         /*
 632          * Clear Bootloader bit.
 633          */
 634         retval = target_write_u32(target, 0x400201a0, 0x0);
 635         CHECK_STATUS(retval, "error clearing bootloader bit");
 636
 637         return retval;
 638 }
 639
 640 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
 641         uint32_t offset, uint32_t count)
 642 {
 643         uint32_t retval;
 644
 645         /* try using a block write */
 646         retval = ambiqmicro_write_block(bank, buffer, offset, count);
 647         if (retval != ERROR_OK)
 648                 LOG_ERROR("write failed");
 649
 650         return retval;
 651 }
 652
 653 static int ambiqmicro_probe(struct flash_bank *bank)
 654 {
 655         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 656         uint32_t retval;
 657
 658         /* If this is a ambiqmicro chip, it has flash; probe() is just
 659          * to figure out how much is present.  Only do it once.
 660          */
 661         if (ambiqmicro_info->probed == 1) {
 662                 LOG_INFO("Target already probed");
 663                 return ERROR_OK;
 664         }
 665
 666         /* ambiqmicro_read_part_info() already handled error checking and
 667          * reporting.  Note that it doesn't write, so we don't care about
 668          * whether the target is halted or not.
 669          */
 670         retval = ambiqmicro_read_part_info(bank);
 671         if (retval != ERROR_OK)
 672                 return retval;
 673
 674         if (bank->sectors) {
 675                 free(bank->sectors);
 676                 bank->sectors = NULL;
 677         }
 678
 679         /* provide this for the benefit of the NOR flash framework */
 680         bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
 681         bank->num_sectors = ambiqmicro_info->num_pages;
 682         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 683         for (int i = 0; i < bank->num_sectors; i++) {
 684                 bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
 685                 bank->sectors[i].size = ambiqmicro_info->pagesize;
 686                 bank->sectors[i].is_erased = -1;
 687                 bank->sectors[i].is_protected = -1;
 688         }
 689
 690         /*
 691          * Part has been probed.
 692          */
 693         ambiqmicro_info->probed = 1;
 694
 695         return retval;
 696 }
 697
 698 static int ambiqmicro_otp_program(struct flash_bank *bank,
 699         uint32_t offset, uint32_t count)
 700 {
 701         struct target *target = NULL;
 702         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 703         uint32_t retval = ERROR_OK;
 704
 705         ambiqmicro_info = bank->driver_priv;
 706         target = bank->target;
 707
 708         if (target->state != TARGET_HALTED) {
 709                 LOG_ERROR("Target not halted");
 710                 return ERROR_TARGET_NOT_HALTED;
 711         }
 712
 713         if (ambiqmicro_info->probed == 0) {
 714                 LOG_ERROR("Target not probed");
 715                 return ERROR_FLASH_BANK_NOT_PROBED;
 716         }
 717
 718         if (count > 256) {
 719                 LOG_ERROR("Count must be < 256");
 720                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 721         }
 722
 723         /*
 724          * Clear Bootloader bit.
 725          */
 726         retval = target_write_u32(target, 0x400201a0, 0x0);
 727         CHECK_STATUS(retval, "error clearing bootloader bit.");
 728
 729         /*
 730          * Set up the SRAM.
 731          */
 732
 733         /*
 734          * Bank.
 735          */
 736         retval = target_write_u32(target, 0x10000000, offset);
 737         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 738
 739         /*
 740          * Num of words to program.
 741          */
 742         retval = target_write_u32(target, 0x10000004, count);
 743         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 744
 745         /*
 746          * Write Key.
 747          */
 748         retval = target_write_u32(target, 0x10000008, OTP_PROGRAM_KEY);
 749         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 750
 751         /*
 752          * Breakpoint.
 753          */
 754         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 755         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 756         if (retval != ERROR_OK)
 757                 return retval;
 758
 759         /*
 760          * Program OTP.
 761          */
 762         LOG_INFO("Programming OTP offset 0x%08x", offset);
 763
 764         /*
 765          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 766          */
 767         retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_OTP_FROM_SRAM, 0x1000000C);
 768         CHECK_STATUS(retval, "error executing ambiqmicro otp program algorithm");
 769
 770         LOG_INFO("Programming OTP finished.");
 771
 772         return retval;
 773 }
 774
 775
 776
 777 COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
 778 {
 779         int i;
 780
 781         if (CMD_ARGC < 1)
 782                 return ERROR_COMMAND_SYNTAX_ERROR;
 783
 784         struct flash_bank *bank;
 785         uint32_t retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 786         if (ERROR_OK != retval)
 787                 return retval;
 788
 789         if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
 790                 /* set all sectors as erased */
 791                 for (i = 0; i < bank->num_sectors; i++)
 792                         bank->sectors[i].is_erased = 1;
 793
 794                 command_print(CMD_CTX, "ambiqmicro mass erase complete");
 795         } else
 796                 command_print(CMD_CTX, "ambiqmicro mass erase failed");
 797
 798         return ERROR_OK;
 799 }
 800
 801 COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
 802 {
 803         struct flash_bank *bank;
 804         uint32_t first, last;
 805         uint32_t retval;
 806
 807         if (CMD_ARGC < 3)
 808                 return ERROR_COMMAND_SYNTAX_ERROR;
 809
 810         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
 811         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
 812
 813         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 814         if (ERROR_OK != retval)
 815                 return retval;
 816
 817         if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
 818                 command_print(CMD_CTX, "ambiqmicro page erase complete");
 819         else
 820                 command_print(CMD_CTX, "ambiqmicro page erase failed");
 821
 822         return ERROR_OK;
 823 }
 824
 825
 826 /**
 827  * Program the otp block.
 828  */
 829 COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
 830 {
 831         struct flash_bank *bank;
 832         uint32_t offset, count;
 833         uint32_t retval;
 834
 835         if (CMD_ARGC < 3)
 836                 return ERROR_COMMAND_SYNTAX_ERROR;
 837
 838         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
 839         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
 840
 841         command_print(CMD_CTX, "offset=0x%08x count=%d", offset, count);
 842
 843         CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 844
 845         retval = ambiqmicro_otp_program(bank, offset, count);
 846
 847         if (retval != ERROR_OK)
 848                 LOG_ERROR("error check log");
 849
 850         return ERROR_OK;
 851 }
 852
 853
 854
 855 static const struct command_registration ambiqmicro_exec_command_handlers[] = {
 856         {
 857                 .name = "mass_erase",
 858                 .usage = "<bank>",
 859                 .handler = ambiqmicro_handle_mass_erase_command,
 860                 .mode = COMMAND_EXEC,
 861                 .help = "Erase entire device",
 862         },
 863         {
 864                 .name = "page_erase",
 865                 .usage = "<bank> <first> <last>",
 866                 .handler = ambiqmicro_handle_page_erase_command,
 867                 .mode = COMMAND_EXEC,
 868                 .help = "Erase device pages",
 869         },
 870         {
 871                 .name = "program_otp",
 872                 .handler = ambiqmicro_handle_program_otp_command,
 873                 .mode = COMMAND_EXEC,
 874                 .usage = "<bank> <offset> <count>",
 875                 .help =
 876                         "Program OTP (assumes you have already written array starting at 0x10000010)",
 877         },
 878         COMMAND_REGISTRATION_DONE
 879 };
 880 static const struct command_registration ambiqmicro_command_handlers[] = {
 881         {
 882                 .name = "ambiqmicro",
 883                 .mode = COMMAND_EXEC,
 884                 .help = "ambiqmicro flash command group",
 885                 .usage = "Support for Ambiq Micro parts.",
 886                 .chain = ambiqmicro_exec_command_handlers,
 887         },
 888         COMMAND_REGISTRATION_DONE
 889 };
 890
 891 struct flash_driver ambiqmicro_flash = {
 892         .name = "ambiqmicro",
 893         .commands = ambiqmicro_command_handlers,
 894         .flash_bank_command = ambiqmicro_flash_bank_command,
 895         .erase = ambiqmicro_erase,
 896         .protect = ambiqmicro_protect,
 897         .write = ambiqmicro_write,
 898         .read = default_flash_read,
 899         .probe = ambiqmicro_probe,
 900         .auto_probe = ambiqmicro_probe,
 901         .erase_check = default_flash_blank_check,
 902         .protect_check = ambiqmicro_protect_check,
 903         .info = get_ambiqmicro_info,
 904 };