1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include "time_support.h"
26 #include "target_type.h"
30 #define _DEBUG_INSTRUCTION_EXECUTION_
34 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
35 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
36 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
37 int arm920t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
38 int arm920t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
41 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
43 /* forward declarations */
44 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
);
45 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
46 int arm920t_quit(void);
48 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
50 target_type_t arm920t_target
=
55 .arch_state
= arm920t_arch_state
,
57 .target_request_data
= arm7_9_target_request_data
,
60 .resume
= arm7_9_resume
,
63 .assert_reset
= arm7_9_assert_reset
,
64 .deassert_reset
= arm7_9_deassert_reset
,
65 .soft_reset_halt
= arm920t_soft_reset_halt
,
67 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
69 .read_memory
= arm920t_read_memory
,
70 .write_memory
= arm920t_write_memory
,
71 .bulk_write_memory
= arm7_9_bulk_write_memory
,
72 .checksum_memory
= arm7_9_checksum_memory
,
73 .blank_check_memory
= arm7_9_blank_check_memory
,
75 .run_algorithm
= armv4_5_run_algorithm
,
77 .add_breakpoint
= arm7_9_add_breakpoint
,
78 .remove_breakpoint
= arm7_9_remove_breakpoint
,
79 .add_watchpoint
= arm7_9_add_watchpoint
,
80 .remove_watchpoint
= arm7_9_remove_watchpoint
,
82 .register_commands
= arm920t_register_commands
,
83 .target_create
= arm920t_target_create
,
84 .init_target
= arm920t_init_target
,
85 .examine
= arm9tdmi_examine
,
89 int arm920t_read_cp15_physical(target_t
*target
, int reg_addr
, uint32_t *value
)
91 armv4_5_common_t
*armv4_5
= target
->arch_info
;
92 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
93 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
94 scan_field_t fields
[4];
95 uint8_t access_type_buf
= 1;
96 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
99 jtag_set_end_state(TAP_IDLE
);
100 arm_jtag_scann(jtag_info
, 0xf);
101 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
103 fields
[0].tap
= jtag_info
->tap
;
104 fields
[0].num_bits
= 1;
105 fields
[0].out_value
= &access_type_buf
;
106 fields
[0].in_value
= NULL
;
108 fields
[1].tap
= jtag_info
->tap
;
109 fields
[1].num_bits
= 32;
110 fields
[1].out_value
= NULL
;
111 fields
[1].in_value
= NULL
;
113 fields
[2].tap
= jtag_info
->tap
;
114 fields
[2].num_bits
= 6;
115 fields
[2].out_value
= ®_addr_buf
;
116 fields
[2].in_value
= NULL
;
118 fields
[3].tap
= jtag_info
->tap
;
119 fields
[3].num_bits
= 1;
120 fields
[3].out_value
= &nr_w_buf
;
121 fields
[3].in_value
= NULL
;
123 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
125 fields
[1].in_value
= (uint8_t *)value
;
127 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
129 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
131 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
132 jtag_execute_queue();
133 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
139 int arm920t_write_cp15_physical(target_t
*target
, int reg_addr
, uint32_t value
)
141 armv4_5_common_t
*armv4_5
= target
->arch_info
;
142 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
143 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
144 scan_field_t fields
[4];
145 uint8_t access_type_buf
= 1;
146 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
147 uint8_t nr_w_buf
= 1;
148 uint8_t value_buf
[4];
150 buf_set_u32(value_buf
, 0, 32, value
);
152 jtag_set_end_state(TAP_IDLE
);
153 arm_jtag_scann(jtag_info
, 0xf);
154 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
156 fields
[0].tap
= jtag_info
->tap
;
157 fields
[0].num_bits
= 1;
158 fields
[0].out_value
= &access_type_buf
;
159 fields
[0].in_value
= NULL
;
161 fields
[1].tap
= jtag_info
->tap
;
162 fields
[1].num_bits
= 32;
163 fields
[1].out_value
= value_buf
;
164 fields
[1].in_value
= NULL
;
166 fields
[2].tap
= jtag_info
->tap
;
167 fields
[2].num_bits
= 6;
168 fields
[2].out_value
= ®_addr_buf
;
169 fields
[2].in_value
= NULL
;
171 fields
[3].tap
= jtag_info
->tap
;
172 fields
[3].num_bits
= 1;
173 fields
[3].out_value
= &nr_w_buf
;
174 fields
[3].in_value
= NULL
;
176 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
178 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
179 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
185 int arm920t_execute_cp15(target_t
*target
, uint32_t cp15_opcode
, uint32_t arm_opcode
)
188 armv4_5_common_t
*armv4_5
= target
->arch_info
;
189 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
190 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
191 scan_field_t fields
[4];
192 uint8_t access_type_buf
= 0; /* interpreted access */
193 uint8_t reg_addr_buf
= 0x0;
194 uint8_t nr_w_buf
= 0;
195 uint8_t cp15_opcode_buf
[4];
197 jtag_set_end_state(TAP_IDLE
);
198 arm_jtag_scann(jtag_info
, 0xf);
199 arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
);
201 buf_set_u32(cp15_opcode_buf
, 0, 32, cp15_opcode
);
203 fields
[0].tap
= jtag_info
->tap
;
204 fields
[0].num_bits
= 1;
205 fields
[0].out_value
= &access_type_buf
;
206 fields
[0].in_value
= NULL
;
208 fields
[1].tap
= jtag_info
->tap
;
209 fields
[1].num_bits
= 32;
210 fields
[1].out_value
= cp15_opcode_buf
;
211 fields
[1].in_value
= NULL
;
213 fields
[2].tap
= jtag_info
->tap
;
214 fields
[2].num_bits
= 6;
215 fields
[2].out_value
= ®_addr_buf
;
216 fields
[2].in_value
= NULL
;
218 fields
[3].tap
= jtag_info
->tap
;
219 fields
[3].num_bits
= 1;
220 fields
[3].out_value
= &nr_w_buf
;
221 fields
[3].in_value
= NULL
;
223 jtag_add_dr_scan(4, fields
, jtag_get_end_state());
225 arm9tdmi_clock_out(jtag_info
, arm_opcode
, 0, NULL
, 0);
226 arm9tdmi_clock_out(jtag_info
, ARMV4_5_NOP
, 0, NULL
, 1);
227 retval
= arm7_9_execute_sys_speed(target
);
228 if (retval
!= ERROR_OK
)
231 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
233 LOG_ERROR("failed executing JTAG queue, exiting");
240 int arm920t_read_cp15_interpreted(target_t
*target
, uint32_t cp15_opcode
, uint32_t address
, uint32_t *value
)
242 armv4_5_common_t
*armv4_5
= target
->arch_info
;
245 uint32_t cp15c15
= 0x0;
247 /* load address into R1 */
249 arm9tdmi_write_core_regs(target
, 0x2, regs
);
251 /* read-modify-write CP15 test state register
252 * to enable interpreted access mode */
253 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
254 jtag_execute_queue();
255 cp15c15
|= 1; /* set interpret mode */
256 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
258 /* execute CP15 instruction and ARM load (reading from coprocessor) */
259 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_LDR(0, 1));
261 /* disable interpreted access mode */
262 cp15c15
&= ~1U; /* clear interpret mode */
263 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
265 /* retrieve value from R0 */
267 arm9tdmi_read_core_regs(target
, 0x1, regs_p
);
268 jtag_execute_queue();
270 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
271 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode
, address
, *value
);
274 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
277 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
278 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
283 int arm920t_write_cp15_interpreted(target_t
*target
, uint32_t cp15_opcode
, uint32_t value
, uint32_t address
)
285 uint32_t cp15c15
= 0x0;
286 armv4_5_common_t
*armv4_5
= target
->arch_info
;
289 /* load value, address into R0, R1 */
292 arm9tdmi_write_core_regs(target
, 0x3, regs
);
294 /* read-modify-write CP15 test state register
295 * to enable interpreted access mode */
296 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
297 jtag_execute_queue();
298 cp15c15
|= 1; /* set interpret mode */
299 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
301 /* execute CP15 instruction and ARM store (writing to coprocessor) */
302 arm920t_execute_cp15(target
, cp15_opcode
, ARMV4_5_STR(0, 1));
304 /* disable interpreted access mode */
305 cp15c15
&= ~1U; /* set interpret mode */
306 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
308 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
309 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode
, value
, address
);
312 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
315 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= 1;
316 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= 1;
321 uint32_t arm920t_get_ttb(target_t
*target
)
326 if ((retval
= arm920t_read_cp15_interpreted(target
, 0xeebf0f51, 0x0, &ttb
)) != ERROR_OK
)
332 void arm920t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
334 uint32_t cp15_control
;
336 /* read cp15 control register */
337 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
338 jtag_execute_queue();
341 cp15_control
&= ~0x1U
;
344 cp15_control
&= ~0x4U
;
347 cp15_control
&= ~0x1000U
;
349 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
352 void arm920t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
354 uint32_t cp15_control
;
356 /* read cp15 control register */
357 arm920t_read_cp15_physical(target
, 0x2, &cp15_control
);
358 jtag_execute_queue();
361 cp15_control
|= 0x1U
;
364 cp15_control
|= 0x4U
;
367 cp15_control
|= 0x1000U
;
369 arm920t_write_cp15_physical(target
, 0x2, cp15_control
);
372 void arm920t_post_debug_entry(target_t
*target
)
375 armv4_5_common_t
*armv4_5
= target
->arch_info
;
376 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
377 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
378 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
380 /* examine cp15 control reg */
381 arm920t_read_cp15_physical(target
, 0x2, &arm920t
->cp15_control_reg
);
382 jtag_execute_queue();
383 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm920t
->cp15_control_reg
);
385 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
== -1)
387 uint32_t cache_type_reg
;
388 /* identify caches */
389 arm920t_read_cp15_physical(target
, 0x1, &cache_type_reg
);
390 jtag_execute_queue();
391 armv4_5_identify_cache(cache_type_reg
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
394 arm920t
->armv4_5_mmu
.mmu_enabled
= (arm920t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
395 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm920t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
396 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= (arm920t
->cp15_control_reg
& 0x1000U
) ? 1 : 0;
398 /* save i/d fault status and address register */
399 arm920t_read_cp15_interpreted(target
, 0xee150f10, 0x0, &arm920t
->d_fsr
);
400 arm920t_read_cp15_interpreted(target
, 0xee150f30, 0x0, &arm920t
->i_fsr
);
401 arm920t_read_cp15_interpreted(target
, 0xee160f10, 0x0, &arm920t
->d_far
);
402 arm920t_read_cp15_interpreted(target
, 0xee160f30, 0x0, &arm920t
->i_far
);
404 LOG_DEBUG("D FSR: 0x%8.8" PRIx32
", D FAR: 0x%8.8" PRIx32
", I FSR: 0x%8.8" PRIx32
", I FAR: 0x%8.8" PRIx32
"",
405 arm920t
->d_fsr
, arm920t
->d_far
, arm920t
->i_fsr
, arm920t
->i_far
);
407 if (arm920t
->preserve_cache
)
409 /* read-modify-write CP15 test state register
410 * to disable I/D-cache linefills */
411 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
412 jtag_execute_queue();
414 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
418 void arm920t_pre_restore_context(target_t
*target
)
421 armv4_5_common_t
*armv4_5
= target
->arch_info
;
422 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
423 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
424 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
426 /* restore i/d fault status and address register */
427 arm920t_write_cp15_interpreted(target
, 0xee050f10, arm920t
->d_fsr
, 0x0);
428 arm920t_write_cp15_interpreted(target
, 0xee050f30, arm920t
->i_fsr
, 0x0);
429 arm920t_write_cp15_interpreted(target
, 0xee060f10, arm920t
->d_far
, 0x0);
430 arm920t_write_cp15_interpreted(target
, 0xee060f30, arm920t
->i_far
, 0x0);
432 /* read-modify-write CP15 test state register
433 * to reenable I/D-cache linefills */
434 if (arm920t
->preserve_cache
)
436 arm920t_read_cp15_physical(target
, 0x1e, &cp15c15
);
437 jtag_execute_queue();
439 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
443 int arm920t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm9tdmi_common_t
**arm9tdmi_p
, arm920t_common_t
**arm920t_p
)
445 armv4_5_common_t
*armv4_5
= target
->arch_info
;
446 arm7_9_common_t
*arm7_9
;
447 arm9tdmi_common_t
*arm9tdmi
;
448 arm920t_common_t
*arm920t
;
450 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
455 arm7_9
= armv4_5
->arch_info
;
456 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
461 arm9tdmi
= arm7_9
->arch_info
;
462 if (arm9tdmi
->common_magic
!= ARM9TDMI_COMMON_MAGIC
)
467 arm920t
= arm9tdmi
->arch_info
;
468 if (arm920t
->common_magic
!= ARM920T_COMMON_MAGIC
)
473 *armv4_5_p
= armv4_5
;
475 *arm9tdmi_p
= arm9tdmi
;
476 *arm920t_p
= arm920t
;
481 int arm920t_arch_state(struct target_s
*target
)
483 armv4_5_common_t
*armv4_5
= target
->arch_info
;
484 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
485 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
486 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
490 "disabled", "enabled"
493 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
495 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
499 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
500 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
501 "MMU: %s, D-Cache: %s, I-Cache: %s",
502 armv4_5_state_strings
[armv4_5
->core_state
],
503 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
504 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
505 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
506 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
507 state
[arm920t
->armv4_5_mmu
.mmu_enabled
],
508 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
],
509 state
[arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
]);
514 int arm920t_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
518 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
523 int arm920t_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
526 armv4_5_common_t
*armv4_5
= target
->arch_info
;
527 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
528 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
529 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
531 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
534 if (((size
== 4) || (size
== 2)) && (count
== 1))
536 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
538 LOG_DEBUG("D-Cache enabled, writing through to main memory");
542 pa
= armv4_5_mmu_translate_va(target
, &arm920t
->armv4_5_mmu
, address
, &type
, &cb
, &domain
, &ap
);
545 /* cacheable & bufferable means write-back region */
547 armv4_5_mmu_write_physical(target
, &arm920t
->armv4_5_mmu
, pa
, size
, count
, buffer
);
550 if (arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
)
552 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
553 arm920t_write_cp15_interpreted(target
, 0xee070f35, 0x0, address
);
560 int arm920t_soft_reset_halt(struct target_s
*target
)
562 int retval
= ERROR_OK
;
563 armv4_5_common_t
*armv4_5
= target
->arch_info
;
564 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
565 arm9tdmi_common_t
*arm9tdmi
= arm7_9
->arch_info
;
566 arm920t_common_t
*arm920t
= arm9tdmi
->arch_info
;
567 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
569 if ((retval
= target_halt(target
)) != ERROR_OK
)
574 long long then
= timeval_ms();
576 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
578 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
580 embeddedice_read_reg(dbg_stat
);
581 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
589 if (debug_level
>= 3)
591 /* do not eat all CPU, time out after 1 se*/
600 LOG_ERROR("Failed to halt CPU after 1 sec");
601 return ERROR_TARGET_TIMEOUT
;
604 target
->state
= TARGET_HALTED
;
606 /* SVC, ARM state, IRQ and FIQ disabled */
607 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
608 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
609 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
611 /* start fetching from 0x0 */
612 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
613 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
614 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
616 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
617 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
619 arm920t_disable_mmu_caches(target
, 1, 1, 1);
620 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
621 arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
622 arm920t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
624 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
632 int arm920t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
634 arm9tdmi_init_target(cmd_ctx
, target
);
639 int arm920t_quit(void)
644 int arm920t_init_arch_info(target_t
*target
, arm920t_common_t
*arm920t
, jtag_tap_t
*tap
)
646 arm9tdmi_common_t
*arm9tdmi
= &arm920t
->arm9tdmi_common
;
647 arm7_9_common_t
*arm7_9
= &arm9tdmi
->arm7_9_common
;
649 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
651 arm9tdmi_init_arch_info(target
, arm9tdmi
, tap
);
653 arm9tdmi
->arch_info
= arm920t
;
654 arm920t
->common_magic
= ARM920T_COMMON_MAGIC
;
656 arm7_9
->post_debug_entry
= arm920t_post_debug_entry
;
657 arm7_9
->pre_restore_context
= arm920t_pre_restore_context
;
659 arm920t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
660 arm920t
->armv4_5_mmu
.get_ttb
= arm920t_get_ttb
;
661 arm920t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
662 arm920t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
663 arm920t
->armv4_5_mmu
.disable_mmu_caches
= arm920t_disable_mmu_caches
;
664 arm920t
->armv4_5_mmu
.enable_mmu_caches
= arm920t_enable_mmu_caches
;
665 arm920t
->armv4_5_mmu
.has_tiny_pages
= 1;
666 arm920t
->armv4_5_mmu
.mmu_enabled
= 0;
668 /* disabling linefills leads to lockups, so keep them enabled for now
669 * this doesn't affect correctness, but might affect timing issues, if
670 * important data is evicted from the cache during the debug session
672 arm920t
->preserve_cache
= 0;
674 /* override hw single-step capability from ARM9TDMI */
675 arm7_9
->has_single_step
= 1;
680 int arm920t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
682 arm920t_common_t
*arm920t
= calloc(1,sizeof(arm920t_common_t
));
684 arm920t_init_arch_info(target
, arm920t
, target
->tap
);
689 int arm920t_register_commands(struct command_context_s
*cmd_ctx
)
692 command_t
*arm920t_cmd
;
695 retval
= arm9tdmi_register_commands(cmd_ctx
);
697 arm920t_cmd
= register_command(cmd_ctx
, NULL
, "arm920t", NULL
, COMMAND_ANY
, "arm920t specific commands");
699 register_command(cmd_ctx
, arm920t_cmd
, "cp15", arm920t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <num> [value]");
700 register_command(cmd_ctx
, arm920t_cmd
, "cp15i", arm920t_handle_cp15i_command
, COMMAND_EXEC
, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
701 register_command(cmd_ctx
, arm920t_cmd
, "cache_info", arm920t_handle_cache_info_command
, COMMAND_EXEC
, "display information about target caches");
703 register_command(cmd_ctx
, arm920t_cmd
, "mdw_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
704 register_command(cmd_ctx
, arm920t_cmd
, "mdh_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
705 register_command(cmd_ctx
, arm920t_cmd
, "mdb_phys", arm920t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
707 register_command(cmd_ctx
, arm920t_cmd
, "mww_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
708 register_command(cmd_ctx
, arm920t_cmd
, "mwh_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
709 register_command(cmd_ctx
, arm920t_cmd
, "mwb_phys", arm920t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
711 register_command(cmd_ctx
, arm920t_cmd
, "read_cache", arm920t_handle_read_cache_command
, COMMAND_EXEC
, "display I/D cache content");
712 register_command(cmd_ctx
, arm920t_cmd
, "read_mmu", arm920t_handle_read_mmu_command
, COMMAND_EXEC
, "display I/D mmu content");
717 int arm920t_handle_read_cache_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
719 int retval
= ERROR_OK
;
720 target_t
*target
= get_current_target(cmd_ctx
);
721 armv4_5_common_t
*armv4_5
;
722 arm7_9_common_t
*arm7_9
;
723 arm9tdmi_common_t
*arm9tdmi
;
724 arm920t_common_t
*arm920t
;
725 arm_jtag_t
*jtag_info
;
727 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
729 uint32_t *regs_p
[16];
730 uint32_t C15_C_D_Ind
, C15_C_I_Ind
;
733 arm920t_cache_line_t d_cache
[8][64], i_cache
[8][64];
738 command_print(cmd_ctx
, "usage: arm920t read_cache <filename>");
742 if ((output
= fopen(args
[0], "w")) == NULL
)
744 LOG_DEBUG("error opening cache content file");
748 for (i
= 0; i
< 16; i
++)
749 regs_p
[i
] = ®s
[i
];
751 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
753 command_print(cmd_ctx
, "current target isn't an ARM920t target");
757 jtag_info
= &arm7_9
->jtag_info
;
759 /* disable MMU and Caches */
760 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
761 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
765 cp15_ctrl_saved
= cp15_ctrl
;
766 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
767 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
769 /* read CP15 test state register */
770 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
771 jtag_execute_queue();
773 /* read DCache content */
774 fprintf(output
, "DCache:\n");
776 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
777 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
779 fprintf(output
, "\nsegment: %i\n----------", segment
);
781 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
782 regs
[0] = 0x0 | (segment
<< 5);
783 arm9tdmi_write_core_regs(target
, 0x1, regs
);
785 /* set interpret mode */
787 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
789 /* D CAM Read, loads current victim into C15.C.D.Ind */
790 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
792 /* read current victim */
793 arm920t_read_cp15_physical(target
, 0x3d, &C15_C_D_Ind
);
795 /* clear interpret mode */
797 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
799 for (index
= 0; index
< 64; index
++)
801 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
802 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
803 arm9tdmi_write_core_regs(target
, 0x1, regs
);
805 /* set interpret mode */
807 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
809 /* Write DCache victim */
810 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
813 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
816 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
818 /* clear interpret mode */
820 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
822 /* read D RAM and CAM content */
823 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
824 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
829 d_cache
[segment
][index
].cam
= regs
[9];
832 regs
[9] &= 0xfffffffe;
833 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32
", content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
835 for (i
= 1; i
< 9; i
++)
837 d_cache
[segment
][index
].data
[i
] = regs
[i
];
838 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n", i
-1, regs
[i
]);
843 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
844 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
845 arm9tdmi_write_core_regs(target
, 0x1, regs
);
847 /* set interpret mode */
849 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
851 /* Write DCache victim */
852 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
854 /* clear interpret mode */
856 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
859 /* read ICache content */
860 fprintf(output
, "ICache:\n");
862 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
863 for (segment
= 0; segment
< arm920t
->armv4_5_mmu
.armv4_5_cache
.d_u_size
.nsets
; segment
++)
865 fprintf(output
, "segment: %i\n----------", segment
);
867 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
868 regs
[0] = 0x0 | (segment
<< 5);
869 arm9tdmi_write_core_regs(target
, 0x1, regs
);
871 /* set interpret mode */
873 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
875 /* I CAM Read, loads current victim into C15.C.I.Ind */
876 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
878 /* read current victim */
879 arm920t_read_cp15_physical(target
, 0x3b, &C15_C_I_Ind
);
881 /* clear interpret mode */
883 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
885 for (index
= 0; index
< 64; index
++)
887 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
888 regs
[0] = 0x0 | (segment
<< 5) | (index
<< 26);
889 arm9tdmi_write_core_regs(target
, 0x1, regs
);
891 /* set interpret mode */
893 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
895 /* Write ICache victim */
896 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
899 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
902 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
904 /* clear interpret mode */
906 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
908 /* read I RAM and CAM content */
909 arm9tdmi_read_core_regs(target
, 0x3fe, regs_p
);
910 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
915 i_cache
[segment
][index
].cam
= regs
[9];
918 regs
[9] &= 0xfffffffe;
919 fprintf(output
, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32
", content (%s):\n", segment
, index
, regs
[9], (regs
[9] & 0x10) ? "valid" : "invalid");
921 for (i
= 1; i
< 9; i
++)
923 i_cache
[segment
][index
].data
[i
] = regs
[i
];
924 fprintf(output
, "%i: 0x%8.8" PRIx32
"\n", i
-1, regs
[i
]);
928 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
929 regs
[0] = 0x0 | (segment
<< 5) | (C15_C_D_Ind
<< 26);
930 arm9tdmi_write_core_regs(target
, 0x1, regs
);
932 /* set interpret mode */
934 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
936 /* Write ICache victim */
937 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
939 /* clear interpret mode */
941 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
944 /* restore CP15 MMU and Cache settings */
945 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
947 command_print(cmd_ctx
, "cache content successfully output to %s", args
[0]);
951 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
954 /* mark registers dirty. */
955 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
956 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
957 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
958 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
959 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
960 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
961 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
962 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
963 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
964 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
969 int arm920t_handle_read_mmu_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
971 int retval
= ERROR_OK
;
972 target_t
*target
= get_current_target(cmd_ctx
);
973 armv4_5_common_t
*armv4_5
;
974 arm7_9_common_t
*arm7_9
;
975 arm9tdmi_common_t
*arm9tdmi
;
976 arm920t_common_t
*arm920t
;
977 arm_jtag_t
*jtag_info
;
979 uint32_t cp15_ctrl
, cp15_ctrl_saved
;
981 uint32_t *regs_p
[16];
984 uint32_t Dlockdown
, Ilockdown
;
985 arm920t_tlb_entry_t d_tlb
[64], i_tlb
[64];
990 command_print(cmd_ctx
, "usage: arm920t read_mmu <filename>");
994 if ((output
= fopen(args
[0], "w")) == NULL
)
996 LOG_DEBUG("error opening mmu content file");
1000 for (i
= 0; i
< 16; i
++)
1001 regs_p
[i
] = ®s
[i
];
1003 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1005 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1009 jtag_info
= &arm7_9
->jtag_info
;
1011 /* disable MMU and Caches */
1012 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl
);
1013 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1017 cp15_ctrl_saved
= cp15_ctrl
;
1018 cp15_ctrl
&= ~(ARMV4_5_MMU_ENABLED
| ARMV4_5_D_U_CACHE_ENABLED
| ARMV4_5_I_CACHE_ENABLED
);
1019 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl
);
1021 /* read CP15 test state register */
1022 arm920t_read_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15
);
1023 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1028 /* prepare reading D TLB content
1031 /* set interpret mode */
1033 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1035 /* Read D TLB lockdown */
1036 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1038 /* clear interpret mode */
1040 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1042 /* read D TLB lockdown stored to r1 */
1043 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1044 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1048 Dlockdown
= regs
[1];
1050 for (victim
= 0; victim
< 64; victim
+= 8)
1052 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1053 * base remains unchanged, victim goes through entries 0 to 63 */
1054 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1055 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1057 /* set interpret mode */
1059 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1061 /* Write D TLB lockdown */
1062 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1064 /* Read D TLB CAM */
1065 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1067 /* clear interpret mode */
1069 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1071 /* read D TLB CAM content stored to r2-r9 */
1072 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1073 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1078 for (i
= 0; i
< 8; i
++)
1079 d_tlb
[victim
+ i
].cam
= regs
[i
+ 2];
1082 for (victim
= 0; victim
< 64; victim
++)
1084 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1085 * base remains unchanged, victim goes through entries 0 to 63 */
1086 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1087 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1089 /* set interpret mode */
1091 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1093 /* Write D TLB lockdown */
1094 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1096 /* Read D TLB RAM1 */
1097 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1099 /* Read D TLB RAM2 */
1100 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1102 /* clear interpret mode */
1104 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1106 /* read D TLB RAM content stored to r2 and r3 */
1107 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1108 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1113 d_tlb
[victim
].ram1
= regs
[2];
1114 d_tlb
[victim
].ram2
= regs
[3];
1117 /* restore D TLB lockdown */
1118 regs
[1] = Dlockdown
;
1119 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1121 /* Write D TLB lockdown */
1122 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1124 /* prepare reading I TLB content
1127 /* set interpret mode */
1129 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1131 /* Read I TLB lockdown */
1132 arm920t_execute_cp15(target
, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1134 /* clear interpret mode */
1136 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1138 /* read I TLB lockdown stored to r1 */
1139 arm9tdmi_read_core_regs(target
, 0x2, regs_p
);
1140 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1144 Ilockdown
= regs
[1];
1146 for (victim
= 0; victim
< 64; victim
+= 8)
1148 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1149 * base remains unchanged, victim goes through entries 0 to 63 */
1150 regs
[1] = (Ilockdown
& 0xfc000000) | (victim
<< 20);
1151 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1153 /* set interpret mode */
1155 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1157 /* Write I TLB lockdown */
1158 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1160 /* Read I TLB CAM */
1161 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1163 /* clear interpret mode */
1165 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1167 /* read I TLB CAM content stored to r2-r9 */
1168 arm9tdmi_read_core_regs(target
, 0x3fc, regs_p
);
1169 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1174 for (i
= 0; i
< 8; i
++)
1175 i_tlb
[i
+ victim
].cam
= regs
[i
+ 2];
1178 for (victim
= 0; victim
< 64; victim
++)
1180 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1181 * base remains unchanged, victim goes through entries 0 to 63 */
1182 regs
[1] = (Dlockdown
& 0xfc000000) | (victim
<< 20);
1183 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1185 /* set interpret mode */
1187 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15
);
1189 /* Write I TLB lockdown */
1190 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1192 /* Read I TLB RAM1 */
1193 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1195 /* Read I TLB RAM2 */
1196 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1198 /* clear interpret mode */
1200 arm920t_write_cp15_physical(target
, 0x1e, cp15c15
);
1202 /* read I TLB RAM content stored to r2 and r3 */
1203 arm9tdmi_read_core_regs(target
, 0xc, regs_p
);
1204 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1209 i_tlb
[victim
].ram1
= regs
[2];
1210 i_tlb
[victim
].ram2
= regs
[3];
1213 /* restore I TLB lockdown */
1214 regs
[1] = Ilockdown
;
1215 arm9tdmi_write_core_regs(target
, 0x2, regs
);
1217 /* Write I TLB lockdown */
1218 arm920t_execute_cp15(target
, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1220 /* restore CP15 MMU and Cache settings */
1221 arm920t_write_cp15_physical(target
, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved
);
1223 /* output data to file */
1224 fprintf(output
, "D TLB content:\n");
1225 for (i
= 0; i
< 64; i
++)
1227 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" %s\n", i
, d_tlb
[i
].cam
, d_tlb
[i
].ram1
, d_tlb
[i
].ram2
, (d_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1230 fprintf(output
, "\n\nI TLB content:\n");
1231 for (i
= 0; i
< 64; i
++)
1233 fprintf(output
, "%i: 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" 0x%8.8" PRIx32
" %s\n", i
, i_tlb
[i
].cam
, i_tlb
[i
].ram1
, i_tlb
[i
].ram2
, (i_tlb
[i
].cam
& 0x20) ? "(valid)" : "(invalid)");
1236 command_print(cmd_ctx
, "mmu content successfully output to %s", args
[0]);
1240 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
1243 /* mark registers dirty */
1244 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 0).valid
;
1245 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 1).valid
;
1246 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 2).valid
;
1247 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 3).valid
;
1248 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 4).valid
;
1249 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 5).valid
;
1250 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 6).valid
;
1251 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 7).valid
;
1252 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 8).valid
;
1253 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).dirty
= ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, 9).valid
;
1257 int arm920t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1260 target_t
*target
= get_current_target(cmd_ctx
);
1261 armv4_5_common_t
*armv4_5
;
1262 arm7_9_common_t
*arm7_9
;
1263 arm9tdmi_common_t
*arm9tdmi
;
1264 arm920t_common_t
*arm920t
;
1265 arm_jtag_t
*jtag_info
;
1267 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1269 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1273 jtag_info
= &arm7_9
->jtag_info
;
1275 if (target
->state
!= TARGET_HALTED
)
1277 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1281 /* one or more argument, access a single register (write if second argument is given */
1284 int address
= strtoul(args
[0], NULL
, 0);
1289 if ((retval
= arm920t_read_cp15_physical(target
, address
, &value
)) != ERROR_OK
)
1291 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1294 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
1299 command_print(cmd_ctx
, "%i: %8.8" PRIx32
"", address
, value
);
1303 uint32_t value
= strtoul(args
[1], NULL
, 0);
1304 if ((retval
= arm920t_write_cp15_physical(target
, address
, value
)) != ERROR_OK
)
1306 command_print(cmd_ctx
, "couldn't access reg %i", address
);
1309 command_print(cmd_ctx
, "%i: %8.8" PRIx32
"", address
, value
);
1316 int arm920t_handle_cp15i_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1319 target_t
*target
= get_current_target(cmd_ctx
);
1320 armv4_5_common_t
*armv4_5
;
1321 arm7_9_common_t
*arm7_9
;
1322 arm9tdmi_common_t
*arm9tdmi
;
1323 arm920t_common_t
*arm920t
;
1324 arm_jtag_t
*jtag_info
;
1326 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1328 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1332 jtag_info
= &arm7_9
->jtag_info
;
1334 if (target
->state
!= TARGET_HALTED
)
1336 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1340 /* one or more argument, access a single register (write if second argument is given */
1343 uint32_t opcode
= strtoul(args
[0], NULL
, 0);
1348 if ((retval
= arm920t_read_cp15_interpreted(target
, opcode
, 0x0, &value
)) != ERROR_OK
)
1350 command_print(cmd_ctx
, "couldn't execute %8.8" PRIx32
"", opcode
);
1354 command_print(cmd_ctx
, "%8.8" PRIx32
": %8.8" PRIx32
"", opcode
, value
);
1358 uint32_t value
= strtoul(args
[1], NULL
, 0);
1359 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, 0)) != ERROR_OK
)
1361 command_print(cmd_ctx
, "couldn't execute %8.8" PRIx32
"", opcode
);
1364 command_print(cmd_ctx
, "%8.8" PRIx32
": %8.8" PRIx32
"", opcode
, value
);
1368 uint32_t value
= strtoul(args
[1], NULL
, 0);
1369 uint32_t address
= strtoul(args
[2], NULL
, 0);
1370 if ((retval
= arm920t_write_cp15_interpreted(target
, opcode
, value
, address
)) != ERROR_OK
)
1372 command_print(cmd_ctx
, "couldn't execute %8.8" PRIx32
"", opcode
);
1375 command_print(cmd_ctx
, "%8.8" PRIx32
": %8.8" PRIx32
" %8.8" PRIx32
"", opcode
, value
, address
);
1380 command_print(cmd_ctx
, "usage: arm920t cp15i <opcode> [value] [address]");
1386 int arm920t_handle_cache_info_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1388 target_t
*target
= get_current_target(cmd_ctx
);
1389 armv4_5_common_t
*armv4_5
;
1390 arm7_9_common_t
*arm7_9
;
1391 arm9tdmi_common_t
*arm9tdmi
;
1392 arm920t_common_t
*arm920t
;
1394 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1396 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1400 return armv4_5_handle_cache_info_command(cmd_ctx
, &arm920t
->armv4_5_mmu
.armv4_5_cache
);
1403 int arm920t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1405 target_t
*target
= get_current_target(cmd_ctx
);
1406 armv4_5_common_t
*armv4_5
;
1407 arm7_9_common_t
*arm7_9
;
1408 arm9tdmi_common_t
*arm9tdmi
;
1409 arm920t_common_t
*arm920t
;
1410 arm_jtag_t
*jtag_info
;
1412 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1414 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1418 jtag_info
= &arm7_9
->jtag_info
;
1420 if (target
->state
!= TARGET_HALTED
)
1422 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1426 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);
1429 int arm920t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
1431 target_t
*target
= get_current_target(cmd_ctx
);
1432 armv4_5_common_t
*armv4_5
;
1433 arm7_9_common_t
*arm7_9
;
1434 arm9tdmi_common_t
*arm9tdmi
;
1435 arm920t_common_t
*arm920t
;
1436 arm_jtag_t
*jtag_info
;
1438 if (arm920t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm9tdmi
, &arm920t
) != ERROR_OK
)
1440 command_print(cmd_ctx
, "current target isn't an ARM920t target");
1444 jtag_info
= &arm7_9
->jtag_info
;
1446 if (target
->state
!= TARGET_HALTED
)
1448 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
1452 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm920t
->armv4_5_mmu
);