1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include "time_support.h"
26 #include "target_type.h"
30 #define _DEBUG_INSTRUCTION_EXECUTION_
34 int arm720t_register_commands(struct command_context_s
*cmd_ctx
);
36 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
37 int arm720t_handle_md_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
38 int arm720t_handle_mw_phys_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
40 /* forward declarations */
41 int arm720t_target_create(struct target_s
*target
,Jim_Interp
*interp
);
42 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
);
43 int arm720t_quit(void);
44 int arm720t_arch_state(struct target_s
*target
);
45 int arm720t_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
46 int arm720t_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
47 int arm720t_soft_reset_halt(struct target_s
*target
);
49 target_type_t arm720t_target
=
54 .arch_state
= arm720t_arch_state
,
57 .resume
= arm7_9_resume
,
60 .assert_reset
= arm7_9_assert_reset
,
61 .deassert_reset
= arm7_9_deassert_reset
,
62 .soft_reset_halt
= arm720t_soft_reset_halt
,
64 .get_gdb_reg_list
= armv4_5_get_gdb_reg_list
,
66 .read_memory
= arm720t_read_memory
,
67 .write_memory
= arm720t_write_memory
,
68 .bulk_write_memory
= arm7_9_bulk_write_memory
,
69 .checksum_memory
= arm7_9_checksum_memory
,
70 .blank_check_memory
= arm7_9_blank_check_memory
,
72 .run_algorithm
= armv4_5_run_algorithm
,
74 .add_breakpoint
= arm7_9_add_breakpoint
,
75 .remove_breakpoint
= arm7_9_remove_breakpoint
,
76 .add_watchpoint
= arm7_9_add_watchpoint
,
77 .remove_watchpoint
= arm7_9_remove_watchpoint
,
79 .register_commands
= arm720t_register_commands
,
80 .target_create
= arm720t_target_create
,
81 .init_target
= arm720t_init_target
,
82 .examine
= arm7tdmi_examine
,
86 int arm720t_scan_cp15(target_t
*target
, uint32_t out
, uint32_t *in
, int instruction
, int clock
)
88 int retval
= ERROR_OK
;
89 armv4_5_common_t
*armv4_5
= target
->arch_info
;
90 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
91 arm_jtag_t
*jtag_info
= &arm7_9
->jtag_info
;
92 scan_field_t fields
[2];
94 uint8_t instruction_buf
= instruction
;
96 buf_set_u32(out_buf
, 0, 32, flip_u32(out
, 32));
98 jtag_set_end_state(TAP_DRPAUSE
);
99 if ((retval
= arm_jtag_scann(jtag_info
, 0xf)) != ERROR_OK
)
103 if ((retval
= arm_jtag_set_instr(jtag_info
, jtag_info
->intest_instr
, NULL
)) != ERROR_OK
)
108 fields
[0].tap
= jtag_info
->tap
;
109 fields
[0].num_bits
= 1;
110 fields
[0].out_value
= &instruction_buf
;
111 fields
[0].in_value
= NULL
;
113 fields
[1].tap
= jtag_info
->tap
;
114 fields
[1].num_bits
= 32;
115 fields
[1].out_value
= out_buf
;
116 fields
[1].in_value
= NULL
;
120 fields
[1].in_value
= (uint8_t *)in
;
121 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
122 jtag_add_callback(arm7flip32
, (jtag_callback_data_t
)in
);
125 jtag_add_dr_scan(2, fields
, jtag_get_end_state());
129 jtag_add_runtest(0, jtag_get_end_state());
131 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
132 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
138 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out
, *in
, instruction
, clock
);
140 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out
, instruction
, clock
);
142 LOG_DEBUG("out: %8.8" PRIx32
", instruction: %i, clock: %i", out
, instruction
, clock
);
148 int arm720t_read_cp15(target_t
*target
, uint32_t opcode
, uint32_t *value
)
150 /* fetch CP15 opcode */
151 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
153 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
154 /* "EXECUTE" stage (1) */
155 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
156 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
157 /* "EXECUTE" stage (2) */
158 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
159 /* "EXECUTE" stage (3), CDATA is read */
160 arm720t_scan_cp15(target
, ARMV4_5_NOP
, value
, 1, 1);
165 int arm720t_write_cp15(target_t
*target
, uint32_t opcode
, uint32_t value
)
167 /* fetch CP15 opcode */
168 arm720t_scan_cp15(target
, opcode
, NULL
, 1, 1);
170 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
171 /* "EXECUTE" stage (1) */
172 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 0);
173 arm720t_scan_cp15(target
, 0x0, NULL
, 0, 1);
174 /* "EXECUTE" stage (2) */
175 arm720t_scan_cp15(target
, value
, NULL
, 0, 1);
176 arm720t_scan_cp15(target
, ARMV4_5_NOP
, NULL
, 1, 1);
181 uint32_t arm720t_get_ttb(target_t
*target
)
185 arm720t_read_cp15(target
, 0xee120f10, &ttb
);
186 jtag_execute_queue();
193 void arm720t_disable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
195 uint32_t cp15_control
;
197 /* read cp15 control register */
198 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
199 jtag_execute_queue();
202 cp15_control
&= ~0x1U
;
204 if (d_u_cache
|| i_cache
)
205 cp15_control
&= ~0x4U
;
207 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
210 void arm720t_enable_mmu_caches(target_t
*target
, int mmu
, int d_u_cache
, int i_cache
)
212 uint32_t cp15_control
;
214 /* read cp15 control register */
215 arm720t_read_cp15(target
, 0xee110f10, &cp15_control
);
216 jtag_execute_queue();
219 cp15_control
|= 0x1U
;
221 if (d_u_cache
|| i_cache
)
222 cp15_control
|= 0x4U
;
224 arm720t_write_cp15(target
, 0xee010f10, cp15_control
);
227 void arm720t_post_debug_entry(target_t
*target
)
229 armv4_5_common_t
*armv4_5
= target
->arch_info
;
230 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
231 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
232 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
234 /* examine cp15 control reg */
235 arm720t_read_cp15(target
, 0xee110f10, &arm720t
->cp15_control_reg
);
236 jtag_execute_queue();
237 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32
"", arm720t
->cp15_control_reg
);
239 arm720t
->armv4_5_mmu
.mmu_enabled
= (arm720t
->cp15_control_reg
& 0x1U
) ? 1 : 0;
240 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= (arm720t
->cp15_control_reg
& 0x4U
) ? 1 : 0;
241 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
243 /* save i/d fault status and address register */
244 arm720t_read_cp15(target
, 0xee150f10, &arm720t
->fsr_reg
);
245 arm720t_read_cp15(target
, 0xee160f10, &arm720t
->far_reg
);
246 jtag_execute_queue();
249 void arm720t_pre_restore_context(target_t
*target
)
251 armv4_5_common_t
*armv4_5
= target
->arch_info
;
252 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
253 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
254 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
256 /* restore i/d fault status and address register */
257 arm720t_write_cp15(target
, 0xee050f10, arm720t
->fsr_reg
);
258 arm720t_write_cp15(target
, 0xee060f10, arm720t
->far_reg
);
261 int arm720t_get_arch_pointers(target_t
*target
, armv4_5_common_t
**armv4_5_p
, arm7_9_common_t
**arm7_9_p
, arm7tdmi_common_t
**arm7tdmi_p
, arm720t_common_t
**arm720t_p
)
263 armv4_5_common_t
*armv4_5
= target
->arch_info
;
264 arm7_9_common_t
*arm7_9
;
265 arm7tdmi_common_t
*arm7tdmi
;
266 arm720t_common_t
*arm720t
;
268 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
273 arm7_9
= armv4_5
->arch_info
;
274 if (arm7_9
->common_magic
!= ARM7_9_COMMON_MAGIC
)
279 arm7tdmi
= arm7_9
->arch_info
;
280 if (arm7tdmi
->common_magic
!= ARM7TDMI_COMMON_MAGIC
)
285 arm720t
= arm7tdmi
->arch_info
;
286 if (arm720t
->common_magic
!= ARM720T_COMMON_MAGIC
)
291 *armv4_5_p
= armv4_5
;
293 *arm7tdmi_p
= arm7tdmi
;
294 *arm720t_p
= arm720t
;
299 int arm720t_arch_state(struct target_s
*target
)
301 armv4_5_common_t
*armv4_5
= target
->arch_info
;
302 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
303 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
304 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
308 "disabled", "enabled"
311 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
313 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
317 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
318 "cpsr: 0x%8.8" PRIx32
" pc: 0x%8.8" PRIx32
"\n"
319 "MMU: %s, Cache: %s",
320 armv4_5_state_strings
[armv4_5
->core_state
],
321 Jim_Nvp_value2name_simple(nvp_target_debug_reason
, target
->debug_reason
)->name
,
322 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
323 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
324 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32),
325 state
[arm720t
->armv4_5_mmu
.mmu_enabled
],
326 state
[arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
]);
331 int arm720t_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
334 armv4_5_common_t
*armv4_5
= target
->arch_info
;
335 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
336 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
337 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
339 /* disable cache, but leave MMU enabled */
340 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
341 arm720t_disable_mmu_caches(target
, 0, 1, 0);
343 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
345 if (arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
)
346 arm720t_enable_mmu_caches(target
, 0, 1, 0);
351 int arm720t_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
355 if ((retval
= arm7_9_write_memory(target
, address
, size
, count
, buffer
)) != ERROR_OK
)
361 int arm720t_soft_reset_halt(struct target_s
*target
)
363 int retval
= ERROR_OK
;
364 armv4_5_common_t
*armv4_5
= target
->arch_info
;
365 arm7_9_common_t
*arm7_9
= armv4_5
->arch_info
;
366 arm7tdmi_common_t
*arm7tdmi
= arm7_9
->arch_info
;
367 arm720t_common_t
*arm720t
= arm7tdmi
->arch_info
;
368 reg_t
*dbg_stat
= &arm7_9
->eice_cache
->reg_list
[EICE_DBG_STAT
];
370 if ((retval
= target_halt(target
)) != ERROR_OK
)
375 long long then
= timeval_ms();
377 while (!(timeout
= ((timeval_ms()-then
) > 1000)))
379 if (buf_get_u32(dbg_stat
->value
, EICE_DBG_STATUS_DBGACK
, 1) == 0)
381 embeddedice_read_reg(dbg_stat
);
382 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
390 if (debug_level
>= 3)
400 LOG_ERROR("Failed to halt CPU after 1 sec");
401 return ERROR_TARGET_TIMEOUT
;
404 target
->state
= TARGET_HALTED
;
406 /* SVC, ARM state, IRQ and FIQ disabled */
407 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 8, 0xd3);
408 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
409 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
411 /* start fetching from 0x0 */
412 buf_set_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32, 0x0);
413 armv4_5
->core_cache
->reg_list
[15].dirty
= 1;
414 armv4_5
->core_cache
->reg_list
[15].valid
= 1;
416 armv4_5
->core_mode
= ARMV4_5_MODE_SVC
;
417 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
419 arm720t_disable_mmu_caches(target
, 1, 1, 1);
420 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
421 arm720t
->armv4_5_mmu
.armv4_5_cache
.d_u_cache_enabled
= 0;
422 arm720t
->armv4_5_mmu
.armv4_5_cache
.i_cache_enabled
= 0;
424 if ((retval
= target_call_event_callbacks(target
, TARGET_EVENT_HALTED
)) != ERROR_OK
)
432 int arm720t_init_target(struct command_context_s
*cmd_ctx
, struct target_s
*target
)
434 arm7tdmi_init_target(cmd_ctx
, target
);
439 int arm720t_quit(void)
444 int arm720t_init_arch_info(target_t
*target
, arm720t_common_t
*arm720t
, jtag_tap_t
*tap
)
446 arm7tdmi_common_t
*arm7tdmi
= &arm720t
->arm7tdmi_common
;
447 arm7_9_common_t
*arm7_9
= &arm7tdmi
->arm7_9_common
;
449 arm7tdmi_init_arch_info(target
, arm7tdmi
, tap
);
451 arm7tdmi
->arch_info
= arm720t
;
452 arm720t
->common_magic
= ARM720T_COMMON_MAGIC
;
454 arm7_9
->post_debug_entry
= arm720t_post_debug_entry
;
455 arm7_9
->pre_restore_context
= arm720t_pre_restore_context
;
457 arm720t
->armv4_5_mmu
.armv4_5_cache
.ctype
= -1;
458 arm720t
->armv4_5_mmu
.get_ttb
= arm720t_get_ttb
;
459 arm720t
->armv4_5_mmu
.read_memory
= arm7_9_read_memory
;
460 arm720t
->armv4_5_mmu
.write_memory
= arm7_9_write_memory
;
461 arm720t
->armv4_5_mmu
.disable_mmu_caches
= arm720t_disable_mmu_caches
;
462 arm720t
->armv4_5_mmu
.enable_mmu_caches
= arm720t_enable_mmu_caches
;
463 arm720t
->armv4_5_mmu
.has_tiny_pages
= 0;
464 arm720t
->armv4_5_mmu
.mmu_enabled
= 0;
469 int arm720t_target_create(struct target_s
*target
, Jim_Interp
*interp
)
471 arm720t_common_t
*arm720t
= calloc(1,sizeof(arm720t_common_t
));
473 arm720t_init_arch_info(target
, arm720t
, target
->tap
);
478 int arm720t_register_commands(struct command_context_s
*cmd_ctx
)
481 command_t
*arm720t_cmd
;
484 retval
= arm7tdmi_register_commands(cmd_ctx
);
486 arm720t_cmd
= register_command(cmd_ctx
, NULL
, "arm720t", NULL
, COMMAND_ANY
, "arm720t specific commands");
488 register_command(cmd_ctx
, arm720t_cmd
, "cp15", arm720t_handle_cp15_command
, COMMAND_EXEC
, "display/modify cp15 register <opcode> [value]");
490 register_command(cmd_ctx
, arm720t_cmd
, "mdw_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory words <physical addr> [count]");
491 register_command(cmd_ctx
, arm720t_cmd
, "mdh_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory half-words <physical addr> [count]");
492 register_command(cmd_ctx
, arm720t_cmd
, "mdb_phys", arm720t_handle_md_phys_command
, COMMAND_EXEC
, "display memory bytes <physical addr> [count]");
494 register_command(cmd_ctx
, arm720t_cmd
, "mww_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory word <physical addr> <value>");
495 register_command(cmd_ctx
, arm720t_cmd
, "mwh_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory half-word <physical addr> <value>");
496 register_command(cmd_ctx
, arm720t_cmd
, "mwb_phys", arm720t_handle_mw_phys_command
, COMMAND_EXEC
, "write memory byte <physical addr> <value>");
501 int arm720t_handle_cp15_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
504 target_t
*target
= get_current_target(cmd_ctx
);
505 armv4_5_common_t
*armv4_5
;
506 arm7_9_common_t
*arm7_9
;
507 arm7tdmi_common_t
*arm7tdmi
;
508 arm720t_common_t
*arm720t
;
509 arm_jtag_t
*jtag_info
;
511 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
513 command_print(cmd_ctx
, "current target isn't an ARM720t target");
517 jtag_info
= &arm7_9
->jtag_info
;
519 if (target
->state
!= TARGET_HALTED
)
521 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
525 /* one or more argument, access a single register (write if second argument is given */
528 uint32_t opcode
= strtoul(args
[0], NULL
, 0);
533 if ((retval
= arm720t_read_cp15(target
, opcode
, &value
)) != ERROR_OK
)
535 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
539 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
544 command_print(cmd_ctx
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
548 uint32_t value
= strtoul(args
[1], NULL
, 0);
549 if ((retval
= arm720t_write_cp15(target
, opcode
, value
)) != ERROR_OK
)
551 command_print(cmd_ctx
, "couldn't access cp15 with opcode 0x%8.8" PRIx32
"", opcode
);
554 command_print(cmd_ctx
, "0x%8.8" PRIx32
": 0x%8.8" PRIx32
"", opcode
, value
);
561 int arm720t_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
563 target_t
*target
= get_current_target(cmd_ctx
);
564 armv4_5_common_t
*armv4_5
;
565 arm7_9_common_t
*arm7_9
;
566 arm7tdmi_common_t
*arm7tdmi
;
567 arm720t_common_t
*arm720t
;
568 arm_jtag_t
*jtag_info
;
570 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
572 command_print(cmd_ctx
, "current target isn't an ARM720t target");
576 jtag_info
= &arm7_9
->jtag_info
;
578 if (target
->state
!= TARGET_HALTED
)
580 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
584 return armv4_5_mmu_handle_md_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);
587 int arm720t_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
)
589 target_t
*target
= get_current_target(cmd_ctx
);
590 armv4_5_common_t
*armv4_5
;
591 arm7_9_common_t
*arm7_9
;
592 arm7tdmi_common_t
*arm7tdmi
;
593 arm720t_common_t
*arm720t
;
594 arm_jtag_t
*jtag_info
;
596 if (arm720t_get_arch_pointers(target
, &armv4_5
, &arm7_9
, &arm7tdmi
, &arm720t
) != ERROR_OK
)
598 command_print(cmd_ctx
, "current target isn't an ARM720t target");
602 jtag_info
= &arm7_9
->jtag_info
;
604 if (target
->state
!= TARGET_HALTED
)
606 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
610 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx
, cmd
, args
, argc
, target
, &arm720t
->armv4_5_mmu
);