1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
29 ***************************************************************************/
34 #include "jtag/interface.h"
35 #include "breakpoints.h"
37 #include "target_request.h"
38 #include "target_type.h"
39 #include "arm_disassembler.h"
41 #include "arm_opcodes.h"
42 #include "arm_semihosting.h"
43 #include <helper/time_support.h>
45 /* NOTE: most of this should work fine for the Cortex-M1 and
46 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
47 * Some differences: M0/M1 doesn't have FBP remapping or the
48 * DWT tracing/profiling support. (So the cycle counter will
49 * not be usable; the other stuff isn't currently used here.)
51 * Although there are some workarounds for errata seen only in r0p0
52 * silicon, such old parts are hard to find and thus not much tested
57 * Returns the type of a break point required by address location
59 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
61 /* forward declarations */
62 static int cortex_m_store_core_reg_u32(struct target
*target
,
63 uint32_t num
, uint32_t value
);
65 static int cortexm_dap_read_coreregister_u32(struct adiv5_dap
*swjdp
,
66 uint32_t *value
, int regnum
)
71 /* because the DCB_DCRDR is used for the emulated dcc channel
72 * we have to save/restore the DCB_DCRDR when used */
74 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
75 if (retval
!= ERROR_OK
)
78 /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
79 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
80 if (retval
!= ERROR_OK
)
82 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
);
83 if (retval
!= ERROR_OK
)
86 /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
87 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
88 if (retval
!= ERROR_OK
)
90 retval
= dap_queue_ap_read(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
91 if (retval
!= ERROR_OK
)
94 retval
= dap_run(swjdp
);
95 if (retval
!= ERROR_OK
)
98 /* restore DCB_DCRDR - this needs to be in a seperate
99 * transaction otherwise the emulated DCC channel breaks */
100 if (retval
== ERROR_OK
)
101 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
106 static int cortexm_dap_write_coreregister_u32(struct adiv5_dap
*swjdp
,
107 uint32_t value
, int regnum
)
112 /* because the DCB_DCRDR is used for the emulated dcc channel
113 * we have to save/restore the DCB_DCRDR when used */
115 retval
= mem_ap_read_u32(swjdp
, DCB_DCRDR
, &dcrdr
);
116 if (retval
!= ERROR_OK
)
119 /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
120 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRDR
& 0xFFFFFFF0);
121 if (retval
!= ERROR_OK
)
123 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRDR
& 0xC), value
);
124 if (retval
!= ERROR_OK
)
127 /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
128 retval
= dap_setup_accessport(swjdp
, CSW_32BIT
| CSW_ADDRINC_OFF
, DCB_DCRSR
& 0xFFFFFFF0);
129 if (retval
!= ERROR_OK
)
131 retval
= dap_queue_ap_write(swjdp
, AP_REG_BD0
| (DCB_DCRSR
& 0xC), regnum
| DCRSR_WnR
);
132 if (retval
!= ERROR_OK
)
135 retval
= dap_run(swjdp
);
136 if (retval
!= ERROR_OK
)
139 /* restore DCB_DCRDR - this needs to be in a seperate
140 * transaction otherwise the emulated DCC channel breaks */
141 if (retval
== ERROR_OK
)
142 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DCRDR
, dcrdr
);
147 static int cortex_m_write_debug_halt_mask(struct target
*target
,
148 uint32_t mask_on
, uint32_t mask_off
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
153 /* mask off status bits */
154 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
155 /* create new register mask */
156 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
158 return mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
161 static int cortex_m_clear_halt(struct target
*target
)
163 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
164 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
167 /* clear step if any */
168 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
170 /* Read Debug Fault Status Register */
171 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
172 if (retval
!= ERROR_OK
)
175 /* Clear Debug Fault Status */
176 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
177 if (retval
!= ERROR_OK
)
179 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
184 static int cortex_m_single_step_core(struct target
*target
)
186 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
187 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
191 /* backup dhcsr reg */
192 dhcsr_save
= cortex_m
->dcb_dhcsr
;
194 /* Mask interrupts before clearing halt, if done already. This avoids
195 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
196 * HALT can put the core into an unknown state.
198 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
199 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
200 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
201 if (retval
!= ERROR_OK
)
204 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
205 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
206 if (retval
!= ERROR_OK
)
210 /* restore dhcsr reg */
211 cortex_m
->dcb_dhcsr
= dhcsr_save
;
212 cortex_m_clear_halt(target
);
217 static int cortex_m_enable_fpb(struct target
*target
)
219 int retval
= target_write_u32(target
, FP_CTRL
, 3);
220 if (retval
!= ERROR_OK
)
223 /* check the fpb is actually enabled */
225 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
226 if (retval
!= ERROR_OK
)
235 static int cortex_m_endreset_event(struct target
*target
)
240 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
241 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
242 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
243 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
244 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
246 /* REVISIT The four debug monitor bits are currently ignored... */
247 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &dcb_demcr
);
248 if (retval
!= ERROR_OK
)
250 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
252 /* this register is used for emulated dcc channel */
253 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
254 if (retval
!= ERROR_OK
)
257 /* Enable debug requests */
258 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
259 if (retval
!= ERROR_OK
)
261 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
262 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
263 if (retval
!= ERROR_OK
)
267 /* clear any interrupt masking */
268 cortex_m_write_debug_halt_mask(target
, 0, C_MASKINTS
);
270 /* Enable features controlled by ITM and DWT blocks, and catch only
271 * the vectors we were told to pay attention to.
273 * Target firmware is responsible for all fault handling policy
274 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
275 * or manual updates to the NVIC SHCSR and CCR registers.
277 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
278 if (retval
!= ERROR_OK
)
281 /* Paranoia: evidently some (early?) chips don't preserve all the
282 * debug state (including FBP, DWT, etc) across reset...
286 retval
= cortex_m_enable_fpb(target
);
287 if (retval
!= ERROR_OK
) {
288 LOG_ERROR("Failed to enable the FPB");
292 cortex_m
->fpb_enabled
= 1;
294 /* Restore FPB registers */
295 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
296 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
297 if (retval
!= ERROR_OK
)
301 /* Restore DWT registers */
302 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
303 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
305 if (retval
!= ERROR_OK
)
307 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
309 if (retval
!= ERROR_OK
)
311 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
312 dwt_list
[i
].function
);
313 if (retval
!= ERROR_OK
)
316 retval
= dap_run(swjdp
);
317 if (retval
!= ERROR_OK
)
320 register_cache_invalidate(armv7m
->arm
.core_cache
);
322 /* make sure we have latest dhcsr flags */
323 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
328 static int cortex_m_examine_debug_reason(struct target
*target
)
330 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
332 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
333 * only check the debug reason if we don't know it already */
335 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
336 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
337 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
338 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
339 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
340 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
341 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
342 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
343 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
344 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
345 else /* EXTERNAL, HALTED */
346 target
->debug_reason
= DBG_REASON_UNDEFINED
;
352 static int cortex_m_examine_exception_reason(struct target
*target
)
354 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
355 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
356 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
359 retval
= mem_ap_read_u32(swjdp
, NVIC_SHCSR
, &shcsr
);
360 if (retval
!= ERROR_OK
)
362 switch (armv7m
->exception_number
) {
365 case 3: /* Hard Fault */
366 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_HFSR
, &except_sr
);
367 if (retval
!= ERROR_OK
)
369 if (except_sr
& 0x40000000) {
370 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &cfsr
);
371 if (retval
!= ERROR_OK
)
375 case 4: /* Memory Management */
376 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
377 if (retval
!= ERROR_OK
)
379 retval
= mem_ap_read_u32(swjdp
, NVIC_MMFAR
, &except_ar
);
380 if (retval
!= ERROR_OK
)
383 case 5: /* Bus Fault */
384 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
385 if (retval
!= ERROR_OK
)
387 retval
= mem_ap_read_u32(swjdp
, NVIC_BFAR
, &except_ar
);
388 if (retval
!= ERROR_OK
)
391 case 6: /* Usage Fault */
392 retval
= mem_ap_read_u32(swjdp
, NVIC_CFSR
, &except_sr
);
393 if (retval
!= ERROR_OK
)
396 case 11: /* SVCall */
398 case 12: /* Debug Monitor */
399 retval
= mem_ap_read_u32(swjdp
, NVIC_DFSR
, &except_sr
);
400 if (retval
!= ERROR_OK
)
403 case 14: /* PendSV */
405 case 15: /* SysTick */
411 retval
= dap_run(swjdp
);
412 if (retval
== ERROR_OK
)
413 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
414 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
415 armv7m_exception_string(armv7m
->exception_number
),
416 shcsr
, except_sr
, cfsr
, except_ar
);
420 static int cortex_m_debug_entry(struct target
*target
)
425 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
426 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
427 struct arm
*arm
= &armv7m
->arm
;
428 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
433 cortex_m_clear_halt(target
);
434 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
435 if (retval
!= ERROR_OK
)
438 retval
= armv7m
->examine_debug_reason(target
);
439 if (retval
!= ERROR_OK
)
442 /* Examine target state and mode
443 * First load register accessible through core debug port */
444 int num_regs
= arm
->core_cache
->num_regs
;
446 for (i
= 0; i
< num_regs
; i
++) {
447 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
449 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
453 xPSR
= buf_get_u32(r
->value
, 0, 32);
455 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
458 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
461 /* Are we in an exception handler */
463 armv7m
->exception_number
= (xPSR
& 0x1FF);
465 arm
->core_mode
= ARM_MODE_HANDLER
;
466 arm
->map
= armv7m_msp_reg_map
;
468 unsigned control
= buf_get_u32(arm
->core_cache
469 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
471 /* is this thread privileged? */
472 arm
->core_mode
= control
& 1
473 ? ARM_MODE_USER_THREAD
476 /* which stack is it using? */
478 arm
->map
= armv7m_psp_reg_map
;
480 arm
->map
= armv7m_msp_reg_map
;
482 armv7m
->exception_number
= 0;
485 if (armv7m
->exception_number
)
486 cortex_m_examine_exception_reason(target
);
488 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
489 arm_mode_name(arm
->core_mode
),
490 *(uint32_t *)(arm
->pc
->value
),
491 target_state_name(target
));
493 if (armv7m
->post_debug_entry
) {
494 retval
= armv7m
->post_debug_entry(target
);
495 if (retval
!= ERROR_OK
)
502 static int cortex_m_poll(struct target
*target
)
504 int detected_failure
= ERROR_OK
;
505 int retval
= ERROR_OK
;
506 enum target_state prev_target_state
= target
->state
;
507 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
508 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
510 /* Read from Debug Halting Control and Status Register */
511 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
512 if (retval
!= ERROR_OK
) {
513 target
->state
= TARGET_UNKNOWN
;
517 /* Recover from lockup. See ARMv7-M architecture spec,
518 * section B1.5.15 "Unrecoverable exception cases".
520 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
521 LOG_ERROR("%s -- clearing lockup after double fault",
522 target_name(target
));
523 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
524 target
->debug_reason
= DBG_REASON_DBGRQ
;
526 /* We have to execute the rest (the "finally" equivalent, but
527 * still throw this exception again).
529 detected_failure
= ERROR_FAIL
;
531 /* refresh status bits */
532 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
533 if (retval
!= ERROR_OK
)
537 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
538 /* check if still in reset */
539 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
540 if (retval
!= ERROR_OK
)
543 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
544 target
->state
= TARGET_RESET
;
549 if (target
->state
== TARGET_RESET
) {
550 /* Cannot switch context while running so endreset is
551 * called with target->state == TARGET_RESET
553 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
554 cortex_m
->dcb_dhcsr
);
555 cortex_m_endreset_event(target
);
556 target
->state
= TARGET_RUNNING
;
557 prev_target_state
= TARGET_RUNNING
;
560 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
561 target
->state
= TARGET_HALTED
;
563 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
564 retval
= cortex_m_debug_entry(target
);
565 if (retval
!= ERROR_OK
)
568 if (arm_semihosting(target
, &retval
) != 0)
571 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
573 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
575 retval
= cortex_m_debug_entry(target
);
576 if (retval
!= ERROR_OK
)
579 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
583 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
584 * How best to model low power modes?
587 if (target
->state
== TARGET_UNKNOWN
) {
588 /* check if processor is retiring instructions */
589 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
590 target
->state
= TARGET_RUNNING
;
595 /* Did we detect a failure condition that we cleared? */
596 if (detected_failure
!= ERROR_OK
)
597 retval
= detected_failure
;
601 static int cortex_m_halt(struct target
*target
)
603 LOG_DEBUG("target->state: %s",
604 target_state_name(target
));
606 if (target
->state
== TARGET_HALTED
) {
607 LOG_DEBUG("target was already halted");
611 if (target
->state
== TARGET_UNKNOWN
)
612 LOG_WARNING("target was in unknown state when halt was requested");
614 if (target
->state
== TARGET_RESET
) {
615 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
616 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
617 return ERROR_TARGET_FAILURE
;
619 /* we came here in a reset_halt or reset_init sequence
620 * debug entry was already prepared in cortex_m3_assert_reset()
622 target
->debug_reason
= DBG_REASON_DBGRQ
;
628 /* Write to Debug Halting Control and Status Register */
629 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
631 target
->debug_reason
= DBG_REASON_DBGRQ
;
636 static int cortex_m_soft_reset_halt(struct target
*target
)
638 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
639 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
640 uint32_t dcb_dhcsr
= 0;
641 int retval
, timeout
= 0;
643 /* soft_reset_halt is deprecated on cortex_m as the same functionality
644 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
645 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
646 * core, not the peripherals */
647 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
649 /* Enter debug state on reset; restore DEMCR in endreset_event() */
650 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
,
651 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
652 if (retval
!= ERROR_OK
)
655 /* Request a core-only reset */
656 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
657 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
658 if (retval
!= ERROR_OK
)
660 target
->state
= TARGET_RESET
;
662 /* registers are now invalid */
663 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
665 while (timeout
< 100) {
666 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &dcb_dhcsr
);
667 if (retval
== ERROR_OK
) {
668 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_DFSR
,
669 &cortex_m
->nvic_dfsr
);
670 if (retval
!= ERROR_OK
)
672 if ((dcb_dhcsr
& S_HALT
)
673 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
674 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
676 (unsigned) dcb_dhcsr
,
677 (unsigned) cortex_m
->nvic_dfsr
);
678 cortex_m_poll(target
);
679 /* FIXME restore user's vector catch config */
682 LOG_DEBUG("waiting for system reset-halt, "
683 "DHCSR 0x%08x, %d ms",
684 (unsigned) dcb_dhcsr
, timeout
);
693 void cortex_m_enable_breakpoints(struct target
*target
)
695 struct breakpoint
*breakpoint
= target
->breakpoints
;
697 /* set any pending breakpoints */
699 if (!breakpoint
->set
)
700 cortex_m_set_breakpoint(target
, breakpoint
);
701 breakpoint
= breakpoint
->next
;
705 static int cortex_m_resume(struct target
*target
, int current
,
706 uint32_t address
, int handle_breakpoints
, int debug_execution
)
708 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
709 struct breakpoint
*breakpoint
= NULL
;
713 if (target
->state
!= TARGET_HALTED
) {
714 LOG_WARNING("target not halted");
715 return ERROR_TARGET_NOT_HALTED
;
718 if (!debug_execution
) {
719 target_free_all_working_areas(target
);
720 cortex_m_enable_breakpoints(target
);
721 cortex_m_enable_watchpoints(target
);
724 if (debug_execution
) {
725 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
727 /* Disable interrupts */
728 /* We disable interrupts in the PRIMASK register instead of
729 * masking with C_MASKINTS. This is probably the same issue
730 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
731 * in parallel with disabled interrupts can cause local faults
734 * REVISIT this clearly breaks non-debug execution, since the
735 * PRIMASK register state isn't saved/restored... workaround
736 * by never resuming app code after debug execution.
738 buf_set_u32(r
->value
, 0, 1, 1);
742 /* Make sure we are in Thumb mode */
743 r
= armv7m
->arm
.cpsr
;
744 buf_set_u32(r
->value
, 24, 1, 1);
749 /* current = 1: continue on current pc, otherwise continue at <address> */
752 buf_set_u32(r
->value
, 0, 32, address
);
757 /* if we halted last time due to a bkpt instruction
758 * then we have to manually step over it, otherwise
759 * the core will break again */
761 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
763 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
765 resume_pc
= buf_get_u32(r
->value
, 0, 32);
767 armv7m_restore_context(target
);
769 /* the front-end may request us not to handle breakpoints */
770 if (handle_breakpoints
) {
771 /* Single step past breakpoint at current address */
772 breakpoint
= breakpoint_find(target
, resume_pc
);
774 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32
" (ID: %" PRIu32
")",
776 breakpoint
->unique_id
);
777 cortex_m_unset_breakpoint(target
, breakpoint
);
778 cortex_m_single_step_core(target
);
779 cortex_m_set_breakpoint(target
, breakpoint
);
784 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
786 target
->debug_reason
= DBG_REASON_NOTHALTED
;
788 /* registers are now invalid */
789 register_cache_invalidate(armv7m
->arm
.core_cache
);
791 if (!debug_execution
) {
792 target
->state
= TARGET_RUNNING
;
793 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
794 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
796 target
->state
= TARGET_DEBUG_RUNNING
;
797 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
798 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
804 /* int irqstepcount = 0; */
805 static int cortex_m_step(struct target
*target
, int current
,
806 uint32_t address
, int handle_breakpoints
)
808 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
809 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
810 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
811 struct breakpoint
*breakpoint
= NULL
;
812 struct reg
*pc
= armv7m
->arm
.pc
;
813 bool bkpt_inst_found
= false;
815 bool isr_timed_out
= false;
817 if (target
->state
!= TARGET_HALTED
) {
818 LOG_WARNING("target not halted");
819 return ERROR_TARGET_NOT_HALTED
;
822 /* current = 1: continue on current pc, otherwise continue at <address> */
824 buf_set_u32(pc
->value
, 0, 32, address
);
826 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
828 /* the front-end may request us not to handle breakpoints */
829 if (handle_breakpoints
) {
830 breakpoint
= breakpoint_find(target
, pc_value
);
832 cortex_m_unset_breakpoint(target
, breakpoint
);
835 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
837 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
839 armv7m_restore_context(target
);
841 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
843 /* if no bkpt instruction is found at pc then we can perform
844 * a normal step, otherwise we have to manually step over the bkpt
845 * instruction - as such simulate a step */
846 if (bkpt_inst_found
== false) {
847 /* Automatic ISR masking mode off: Just step over the next instruction */
848 if ((cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
))
849 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
851 /* Process interrupts during stepping in a way they don't interfere
856 * Set a temporary break point at the current pc and let the core run
857 * with interrupts enabled. Pending interrupts get served and we run
858 * into the breakpoint again afterwards. Then we step over the next
859 * instruction with interrupts disabled.
861 * If the pending interrupts don't complete within time, we leave the
862 * core running. This may happen if the interrupts trigger faster
863 * than the core can process them or the handler doesn't return.
865 * If no more breakpoints are available we simply do a step with
866 * interrupts enabled.
872 * If a break point is already set on the lower half word then a break point on
873 * the upper half word will not break again when the core is restarted. So we
874 * just step over the instruction with interrupts disabled.
876 * The documentation has no information about this, it was found by observation
877 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
878 * suffer from this problem.
880 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
881 * address has it always cleared. The former is done to indicate thumb mode
885 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
886 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
887 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
888 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
889 /* Re-enable interrupts */
890 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
894 /* Set a temporary break point */
896 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
898 retval
= breakpoint_add(target
, pc_value
, 2, BKPT_TYPE_BY_ADDR(pc_value
));
899 bool tmp_bp_set
= (retval
== ERROR_OK
);
901 /* No more breakpoints left, just do a step */
903 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
906 LOG_DEBUG("Starting core to serve pending interrupts");
907 int64_t t_start
= timeval_ms();
908 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
910 /* Wait for pending handlers to complete or timeout */
912 retval
= mem_ap_read_atomic_u32(swjdp
,
914 &cortex_m
->dcb_dhcsr
);
915 if (retval
!= ERROR_OK
) {
916 target
->state
= TARGET_UNKNOWN
;
919 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
920 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
922 /* only remove breakpoint if we created it */
924 cortex_m_unset_breakpoint(target
, breakpoint
);
926 /* Remove the temporary breakpoint */
927 breakpoint_remove(target
, pc_value
);
931 LOG_DEBUG("Interrupt handlers didn't complete within time, "
932 "leaving target running");
934 /* Step over next instruction with interrupts disabled */
935 cortex_m_write_debug_halt_mask(target
,
938 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
939 /* Re-enable interrupts */
940 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
947 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
948 if (retval
!= ERROR_OK
)
951 /* registers are now invalid */
952 register_cache_invalidate(armv7m
->arm
.core_cache
);
955 cortex_m_set_breakpoint(target
, breakpoint
);
958 /* Leave the core running. The user has to stop execution manually. */
959 target
->debug_reason
= DBG_REASON_NOTHALTED
;
960 target
->state
= TARGET_RUNNING
;
964 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
965 " nvic_icsr = 0x%" PRIx32
,
966 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
968 retval
= cortex_m_debug_entry(target
);
969 if (retval
!= ERROR_OK
)
971 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
973 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
974 " nvic_icsr = 0x%" PRIx32
,
975 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
980 static int cortex_m_assert_reset(struct target
*target
)
982 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
983 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
984 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
986 LOG_DEBUG("target->state: %s",
987 target_state_name(target
));
989 enum reset_types jtag_reset_config
= jtag_get_reset_config();
991 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
992 /* allow scripts to override the reset event */
994 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
995 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
996 target
->state
= TARGET_RESET
;
1001 /* some cores support connecting while srst is asserted
1002 * use that mode is it has been configured */
1004 bool srst_asserted
= false;
1006 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1007 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1008 adapter_assert_reset();
1009 srst_asserted
= true;
1012 /* Enable debug requests */
1014 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1015 if (retval
!= ERROR_OK
)
1017 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
1018 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_DEBUGEN
);
1019 if (retval
!= ERROR_OK
)
1023 /* If the processor is sleeping in a WFI or WFE instruction, the
1024 * C_HALT bit must be asserted to regain control */
1025 if (cortex_m
->dcb_dhcsr
& S_SLEEP
) {
1026 retval
= mem_ap_write_u32(swjdp
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1027 if (retval
!= ERROR_OK
)
1031 retval
= mem_ap_write_u32(swjdp
, DCB_DCRDR
, 0);
1032 if (retval
!= ERROR_OK
)
1035 if (!target
->reset_halt
) {
1036 /* Set/Clear C_MASKINTS in a separate operation */
1037 if (cortex_m
->dcb_dhcsr
& C_MASKINTS
) {
1038 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DHCSR
,
1039 DBGKEY
| C_DEBUGEN
| C_HALT
);
1040 if (retval
!= ERROR_OK
)
1044 /* clear any debug flags before resuming */
1045 cortex_m_clear_halt(target
);
1047 /* clear C_HALT in dhcsr reg */
1048 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1050 /* Halt in debug on reset; endreset_event() restores DEMCR.
1052 * REVISIT catching BUSERR presumably helps to defend against
1053 * bad vector table entries. Should this include MMERR or
1056 retval
= mem_ap_write_atomic_u32(swjdp
, DCB_DEMCR
,
1057 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1058 if (retval
!= ERROR_OK
)
1062 if (jtag_reset_config
& RESET_HAS_SRST
) {
1063 /* default to asserting srst */
1065 adapter_assert_reset();
1067 /* Use a standard Cortex-M3 software reset mechanism.
1068 * We default to using VECRESET as it is supported on all current cores.
1069 * This has the disadvantage of not resetting the peripherals, so a
1070 * reset-init event handler is needed to perform any peripheral resets.
1072 retval
= mem_ap_write_atomic_u32(swjdp
, NVIC_AIRCR
,
1073 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1074 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1075 if (retval
!= ERROR_OK
)
1078 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1079 ? "SYSRESETREQ" : "VECTRESET");
1081 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1082 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1083 "handler to reset any peripherals or configure hardware srst support.");
1087 /* I do not know why this is necessary, but it
1088 * fixes strange effects (step/resume cause NMI
1089 * after reset) on LM3S6918 -- Michael Schwingen
1092 retval
= mem_ap_read_atomic_u32(swjdp
, NVIC_AIRCR
, &tmp
);
1093 if (retval
!= ERROR_OK
)
1098 target
->state
= TARGET_RESET
;
1099 jtag_add_sleep(50000);
1101 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1103 if (target
->reset_halt
) {
1104 retval
= target_halt(target
);
1105 if (retval
!= ERROR_OK
)
1112 static int cortex_m_deassert_reset(struct target
*target
)
1114 LOG_DEBUG("target->state: %s",
1115 target_state_name(target
));
1117 /* deassert reset lines */
1118 adapter_deassert_reset();
1123 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1128 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1129 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1131 if (breakpoint
->set
) {
1132 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1136 if (cortex_m
->auto_bp_type
)
1137 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1139 if (breakpoint
->type
== BKPT_HARD
) {
1140 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1142 if (fp_num
>= cortex_m
->fp_num_code
) {
1143 LOG_ERROR("Can not find free FPB Comparator!");
1146 breakpoint
->set
= fp_num
+ 1;
1147 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1148 comparator_list
[fp_num
].used
= 1;
1149 comparator_list
[fp_num
].fpcr_value
= (breakpoint
->address
& 0x1FFFFFFC) | hilo
| 1;
1150 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1151 comparator_list
[fp_num
].fpcr_value
);
1152 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1154 comparator_list
[fp_num
].fpcr_value
);
1155 if (!cortex_m
->fpb_enabled
) {
1156 LOG_DEBUG("FPB wasn't enabled, do it now");
1157 retval
= cortex_m_enable_fpb(target
);
1158 if (retval
!= ERROR_OK
) {
1159 LOG_ERROR("Failed to enable the FPB");
1163 cortex_m
->fpb_enabled
= 1;
1165 } else if (breakpoint
->type
== BKPT_SOFT
) {
1168 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1169 * semihosting; don't use that. Otherwise the BKPT
1170 * parameter is arbitrary.
1172 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1173 retval
= target_read_memory(target
,
1174 breakpoint
->address
& 0xFFFFFFFE,
1175 breakpoint
->length
, 1,
1176 breakpoint
->orig_instr
);
1177 if (retval
!= ERROR_OK
)
1179 retval
= target_write_memory(target
,
1180 breakpoint
->address
& 0xFFFFFFFE,
1181 breakpoint
->length
, 1,
1183 if (retval
!= ERROR_OK
)
1185 breakpoint
->set
= true;
1188 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1189 breakpoint
->unique_id
,
1190 (int)(breakpoint
->type
),
1191 breakpoint
->address
,
1198 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1201 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1202 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1204 if (!breakpoint
->set
) {
1205 LOG_WARNING("breakpoint not set");
1209 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: 0x%08" PRIx32
" Length: %d (set=%d)",
1210 breakpoint
->unique_id
,
1211 (int)(breakpoint
->type
),
1212 breakpoint
->address
,
1216 if (breakpoint
->type
== BKPT_HARD
) {
1217 int fp_num
= breakpoint
->set
- 1;
1218 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1219 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1222 comparator_list
[fp_num
].used
= 0;
1223 comparator_list
[fp_num
].fpcr_value
= 0;
1224 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1225 comparator_list
[fp_num
].fpcr_value
);
1227 /* restore original instruction (kept in target endianness) */
1228 if (breakpoint
->length
== 4) {
1229 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 4, 1,
1230 breakpoint
->orig_instr
);
1231 if (retval
!= ERROR_OK
)
1234 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE, 2, 1,
1235 breakpoint
->orig_instr
);
1236 if (retval
!= ERROR_OK
)
1240 breakpoint
->set
= false;
1245 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1247 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1249 if (cortex_m
->auto_bp_type
)
1250 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1252 if (breakpoint
->type
!= BKPT_TYPE_BY_ADDR(breakpoint
->address
)) {
1253 if (breakpoint
->type
== BKPT_HARD
) {
1254 LOG_INFO("flash patch comparator requested outside code memory region");
1255 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1258 if (breakpoint
->type
== BKPT_SOFT
) {
1259 LOG_INFO("soft breakpoint requested in code (flash) memory region");
1260 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1264 if ((breakpoint
->type
== BKPT_HARD
) && (cortex_m
->fp_code_available
< 1)) {
1265 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1266 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1269 if ((breakpoint
->length
!= 2)) {
1270 LOG_INFO("only breakpoints of two bytes length supported");
1271 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1274 if (breakpoint
->type
== BKPT_HARD
)
1275 cortex_m
->fp_code_available
--;
1277 return cortex_m_set_breakpoint(target
, breakpoint
);
1280 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1282 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1284 /* REVISIT why check? FBP can be updated with core running ... */
1285 if (target
->state
!= TARGET_HALTED
) {
1286 LOG_WARNING("target not halted");
1287 return ERROR_TARGET_NOT_HALTED
;
1290 if (cortex_m
->auto_bp_type
)
1291 breakpoint
->type
= BKPT_TYPE_BY_ADDR(breakpoint
->address
);
1293 if (breakpoint
->set
)
1294 cortex_m_unset_breakpoint(target
, breakpoint
);
1296 if (breakpoint
->type
== BKPT_HARD
)
1297 cortex_m
->fp_code_available
++;
1302 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1305 uint32_t mask
, temp
;
1306 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1308 /* watchpoint params were validated earlier */
1310 temp
= watchpoint
->length
;
1317 /* REVISIT Don't fully trust these "not used" records ... users
1318 * may set up breakpoints by hand, e.g. dual-address data value
1319 * watchpoint using comparator #1; comparator #0 matching cycle
1320 * count; send data trace info through ITM and TPIU; etc
1322 struct cortex_m_dwt_comparator
*comparator
;
1324 for (comparator
= cortex_m
->dwt_comparator_list
;
1325 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1326 comparator
++, dwt_num
++)
1328 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1329 LOG_ERROR("Can not find free DWT Comparator");
1332 comparator
->used
= 1;
1333 watchpoint
->set
= dwt_num
+ 1;
1335 comparator
->comp
= watchpoint
->address
;
1336 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1339 comparator
->mask
= mask
;
1340 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1343 switch (watchpoint
->rw
) {
1345 comparator
->function
= 5;
1348 comparator
->function
= 6;
1351 comparator
->function
= 7;
1354 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1355 comparator
->function
);
1357 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1358 watchpoint
->unique_id
, dwt_num
,
1359 (unsigned) comparator
->comp
,
1360 (unsigned) comparator
->mask
,
1361 (unsigned) comparator
->function
);
1365 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1367 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1368 struct cortex_m_dwt_comparator
*comparator
;
1371 if (!watchpoint
->set
) {
1372 LOG_WARNING("watchpoint (wpid: %d) not set",
1373 watchpoint
->unique_id
);
1377 dwt_num
= watchpoint
->set
- 1;
1379 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1380 watchpoint
->unique_id
, dwt_num
,
1381 (unsigned) watchpoint
->address
);
1383 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1384 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1388 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1389 comparator
->used
= 0;
1390 comparator
->function
= 0;
1391 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1392 comparator
->function
);
1394 watchpoint
->set
= false;
1399 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1401 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1403 if (cortex_m
->dwt_comp_available
< 1) {
1404 LOG_DEBUG("no comparators?");
1405 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1408 /* hardware doesn't support data value masking */
1409 if (watchpoint
->mask
!= ~(uint32_t)0) {
1410 LOG_DEBUG("watchpoint value masks not supported");
1411 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1414 /* hardware allows address masks of up to 32K */
1417 for (mask
= 0; mask
< 16; mask
++) {
1418 if ((1u << mask
) == watchpoint
->length
)
1422 LOG_DEBUG("unsupported watchpoint length");
1423 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1425 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1426 LOG_DEBUG("watchpoint address is unaligned");
1427 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1430 /* Caller doesn't seem to be able to describe watching for data
1431 * values of zero; that flags "no value".
1433 * REVISIT This DWT may well be able to watch for specific data
1434 * values. Requires comparator #1 to set DATAVMATCH and match
1435 * the data, and another comparator (DATAVADDR0) matching addr.
1437 if (watchpoint
->value
) {
1438 LOG_DEBUG("data value watchpoint not YET supported");
1439 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1442 cortex_m
->dwt_comp_available
--;
1443 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1448 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1450 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1452 /* REVISIT why check? DWT can be updated with core running ... */
1453 if (target
->state
!= TARGET_HALTED
) {
1454 LOG_WARNING("target not halted");
1455 return ERROR_TARGET_NOT_HALTED
;
1458 if (watchpoint
->set
)
1459 cortex_m_unset_watchpoint(target
, watchpoint
);
1461 cortex_m
->dwt_comp_available
++;
1462 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1467 void cortex_m_enable_watchpoints(struct target
*target
)
1469 struct watchpoint
*watchpoint
= target
->watchpoints
;
1471 /* set any pending watchpoints */
1472 while (watchpoint
) {
1473 if (!watchpoint
->set
)
1474 cortex_m_set_watchpoint(target
, watchpoint
);
1475 watchpoint
= watchpoint
->next
;
1479 static int cortex_m_load_core_reg_u32(struct target
*target
,
1480 uint32_t num
, uint32_t *value
)
1483 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1484 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1486 /* NOTE: we "know" here that the register identifiers used
1487 * in the v7m header match the Cortex-M3 Debug Core Register
1488 * Selector values for R0..R15, xPSR, MSP, and PSP.
1492 /* read a normal core register */
1493 retval
= cortexm_dap_read_coreregister_u32(swjdp
, value
, num
);
1495 if (retval
!= ERROR_OK
) {
1496 LOG_ERROR("JTAG failure %i", retval
);
1497 return ERROR_JTAG_DEVICE_ERROR
;
1499 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1502 case ARMV7M_PRIMASK
:
1503 case ARMV7M_BASEPRI
:
1504 case ARMV7M_FAULTMASK
:
1505 case ARMV7M_CONTROL
:
1506 /* Cortex-M3 packages these four registers as bitfields
1507 * in one Debug Core register. So say r0 and r2 docs;
1508 * it was removed from r1 docs, but still works.
1510 cortexm_dap_read_coreregister_u32(swjdp
, value
, 20);
1513 case ARMV7M_PRIMASK
:
1514 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1517 case ARMV7M_BASEPRI
:
1518 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1521 case ARMV7M_FAULTMASK
:
1522 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1525 case ARMV7M_CONTROL
:
1526 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1530 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1534 return ERROR_COMMAND_SYNTAX_ERROR
;
1540 static int cortex_m_store_core_reg_u32(struct target
*target
,
1541 uint32_t num
, uint32_t value
)
1545 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1546 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1548 /* NOTE: we "know" here that the register identifiers used
1549 * in the v7m header match the Cortex-M3 Debug Core Register
1550 * Selector values for R0..R15, xPSR, MSP, and PSP.
1554 retval
= cortexm_dap_write_coreregister_u32(swjdp
, value
, num
);
1555 if (retval
!= ERROR_OK
) {
1558 LOG_ERROR("JTAG failure");
1559 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1560 r
->dirty
= r
->valid
;
1561 return ERROR_JTAG_DEVICE_ERROR
;
1563 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1566 case ARMV7M_PRIMASK
:
1567 case ARMV7M_BASEPRI
:
1568 case ARMV7M_FAULTMASK
:
1569 case ARMV7M_CONTROL
:
1570 /* Cortex-M3 packages these four registers as bitfields
1571 * in one Debug Core register. So say r0 and r2 docs;
1572 * it was removed from r1 docs, but still works.
1574 cortexm_dap_read_coreregister_u32(swjdp
, ®
, 20);
1577 case ARMV7M_PRIMASK
:
1578 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1581 case ARMV7M_BASEPRI
:
1582 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1585 case ARMV7M_FAULTMASK
:
1586 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1589 case ARMV7M_CONTROL
:
1590 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1594 cortexm_dap_write_coreregister_u32(swjdp
, reg
, 20);
1596 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1600 return ERROR_COMMAND_SYNTAX_ERROR
;
1606 static int cortex_m_read_memory(struct target
*target
, uint32_t address
,
1607 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1609 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1610 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1612 if (armv7m
->arm
.is_armv6m
) {
1613 /* armv6m does not handle unaligned memory access */
1614 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1615 return ERROR_TARGET_UNALIGNED_ACCESS
;
1618 return mem_ap_read(swjdp
, buffer
, size
, count
, address
, true);
1621 static int cortex_m_write_memory(struct target
*target
, uint32_t address
,
1622 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1624 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1625 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1627 if (armv7m
->arm
.is_armv6m
) {
1628 /* armv6m does not handle unaligned memory access */
1629 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1630 return ERROR_TARGET_UNALIGNED_ACCESS
;
1633 return mem_ap_write(swjdp
, buffer
, size
, count
, address
, true);
1636 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1637 struct target
*target
)
1639 armv7m_build_reg_cache(target
);
1643 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1644 * on r/w if the core is not running, and clear on resume or reset ... or
1645 * at least, in a post_restore_context() method.
1648 struct dwt_reg_state
{
1649 struct target
*target
;
1651 uint32_t value
; /* scratch/cache */
1654 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1656 struct dwt_reg_state
*state
= reg
->arch_info
;
1658 return target_read_u32(state
->target
, state
->addr
, &state
->value
);
1661 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1663 struct dwt_reg_state
*state
= reg
->arch_info
;
1665 return target_write_u32(state
->target
, state
->addr
,
1666 buf_get_u32(buf
, 0, reg
->size
));
1675 static struct dwt_reg dwt_base_regs
[] = {
1676 { DWT_CTRL
, "dwt_ctrl", 32, },
1677 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1678 * increments while the core is asleep.
1680 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1681 /* plus some 8 bit counters, useful for profiling with TPIU */
1684 static struct dwt_reg dwt_comp
[] = {
1685 #define DWT_COMPARATOR(i) \
1686 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1687 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1688 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1693 #undef DWT_COMPARATOR
1696 static const struct reg_arch_type dwt_reg_type
= {
1697 .get
= cortex_m_dwt_get_reg
,
1698 .set
= cortex_m_dwt_set_reg
,
1701 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, struct dwt_reg
*d
)
1703 struct dwt_reg_state
*state
;
1705 state
= calloc(1, sizeof *state
);
1708 state
->addr
= d
->addr
;
1713 r
->value
= &state
->value
;
1714 r
->arch_info
= state
;
1715 r
->type
= &dwt_reg_type
;
1718 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1721 struct reg_cache
*cache
;
1722 struct cortex_m_dwt_comparator
*comparator
;
1725 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1727 LOG_DEBUG("no DWT");
1731 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1732 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1733 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1734 sizeof(struct cortex_m_dwt_comparator
));
1735 if (!cm
->dwt_comparator_list
) {
1737 cm
->dwt_num_comp
= 0;
1738 LOG_ERROR("out of mem");
1742 cache
= calloc(1, sizeof *cache
);
1745 free(cm
->dwt_comparator_list
);
1748 cache
->name
= "cortex-m3 dwt registers";
1749 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
1750 cache
->reg_list
= calloc(cache
->num_regs
, sizeof *cache
->reg_list
);
1751 if (!cache
->reg_list
) {
1756 for (reg
= 0; reg
< 2; reg
++)
1757 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1758 dwt_base_regs
+ reg
);
1760 comparator
= cm
->dwt_comparator_list
;
1761 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
1764 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1765 for (j
= 0; j
< 3; j
++, reg
++)
1766 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1767 dwt_comp
+ 3 * i
+ j
);
1769 /* make sure we clear any watchpoints enabled on the target */
1770 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1773 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1774 cm
->dwt_cache
= cache
;
1776 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1777 dwtcr
, cm
->dwt_num_comp
,
1778 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1780 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1781 * implement single-address data value watchpoints ... so we
1782 * won't need to check it later, when asked to set one up.
1786 #define MVFR0 0xe000ef40
1787 #define MVFR1 0xe000ef44
1789 #define MVFR0_DEFAULT_M4 0x10110021
1790 #define MVFR1_DEFAULT_M4 0x11000011
1792 int cortex_m_examine(struct target
*target
)
1795 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1797 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1798 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
1799 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1801 /* stlink shares the examine handler but does not support
1803 if (!armv7m
->stlink
) {
1804 retval
= ahbap_debugport_init(swjdp
);
1805 if (retval
!= ERROR_OK
)
1809 if (!target_was_examined(target
)) {
1810 target_set_examined(target
);
1812 /* Read from Device Identification Registers */
1813 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1814 if (retval
!= ERROR_OK
)
1818 i
= (cpuid
>> 4) & 0xf;
1820 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
1821 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
1822 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
1824 /* test for floating point feature on cortex-m4 */
1826 target_read_u32(target
, MVFR0
, &mvfr0
);
1827 target_read_u32(target
, MVFR1
, &mvfr1
);
1829 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
1830 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
1831 armv7m
->fp_feature
= FPv4_SP
;
1833 } else if (i
== 0) {
1834 /* Cortex-M0 does not support unaligned memory access */
1835 armv7m
->arm
.is_armv6m
= true;
1838 if (i
== 4 || i
== 3) {
1839 /* Cortex-M3/M4 has 4096 bytes autoincrement range */
1840 armv7m
->dap
.tar_autoincr_block
= (1 << 12);
1843 /* NOTE: FPB and DWT are both optional. */
1846 target_read_u32(target
, FP_CTRL
, &fpcr
);
1847 cortex_m
->auto_bp_type
= 1;
1848 /* bits [14:12] and [7:4] */
1849 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
1850 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
1851 cortex_m
->fp_code_available
= cortex_m
->fp_num_code
;
1852 cortex_m
->fp_comparator_list
= calloc(
1853 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
1854 sizeof(struct cortex_m_fp_comparator
));
1855 cortex_m
->fpb_enabled
= fpcr
& 1;
1856 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
1857 cortex_m
->fp_comparator_list
[i
].type
=
1858 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
1859 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
1861 /* make sure we clear any breakpoints enabled on the target */
1862 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
1864 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
1866 cortex_m
->fp_num_code
,
1867 cortex_m
->fp_num_lit
);
1870 cortex_m_dwt_setup(cortex_m
, target
);
1872 /* These hardware breakpoints only work for code in flash! */
1873 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1874 target_name(target
),
1875 cortex_m
->fp_num_code
,
1876 cortex_m
->dwt_num_comp
);
1882 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
1884 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1885 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
1890 retval
= mem_ap_read(swjdp
, buf
, 2, 1, DCB_DCRDR
, false);
1891 if (retval
!= ERROR_OK
)
1894 dcrdr
= target_buffer_get_u16(target
, buf
);
1895 *ctrl
= (uint8_t)dcrdr
;
1896 *value
= (uint8_t)(dcrdr
>> 8);
1898 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
1900 /* write ack back to software dcc register
1901 * signify we have read data */
1902 if (dcrdr
& (1 << 0)) {
1903 target_buffer_set_u16(target
, buf
, 0);
1904 retval
= mem_ap_write(swjdp
, buf
, 2, 1, DCB_DCRDR
, false);
1905 if (retval
!= ERROR_OK
)
1912 static int cortex_m_target_request_data(struct target
*target
,
1913 uint32_t size
, uint8_t *buffer
)
1919 for (i
= 0; i
< (size
* 4); i
++) {
1920 cortex_m_dcc_read(target
, &data
, &ctrl
);
1927 static int cortex_m_handle_target_request(void *priv
)
1929 struct target
*target
= priv
;
1930 if (!target_was_examined(target
))
1933 if (!target
->dbg_msg_enabled
)
1936 if (target
->state
== TARGET_RUNNING
) {
1940 cortex_m_dcc_read(target
, &data
, &ctrl
);
1942 /* check if we have data */
1943 if (ctrl
& (1 << 0)) {
1946 /* we assume target is quick enough */
1948 cortex_m_dcc_read(target
, &data
, &ctrl
);
1949 request
|= (data
<< 8);
1950 cortex_m_dcc_read(target
, &data
, &ctrl
);
1951 request
|= (data
<< 16);
1952 cortex_m_dcc_read(target
, &data
, &ctrl
);
1953 request
|= (data
<< 24);
1954 target_request(target
, request
);
1961 static int cortex_m_init_arch_info(struct target
*target
,
1962 struct cortex_m_common
*cortex_m
, struct jtag_tap
*tap
)
1965 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1967 armv7m_init_arch_info(target
, armv7m
);
1969 /* prepare JTAG information for the new target */
1970 cortex_m
->jtag_info
.tap
= tap
;
1971 cortex_m
->jtag_info
.scann_size
= 4;
1973 /* default reset mode is to use srst if fitted
1974 * if not it will use CORTEX_M3_RESET_VECTRESET */
1975 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
1977 armv7m
->arm
.dap
= &armv7m
->dap
;
1979 /* Leave (only) generic DAP stuff for debugport_init(); */
1980 armv7m
->dap
.jtag_info
= &cortex_m
->jtag_info
;
1981 armv7m
->dap
.memaccess_tck
= 8;
1983 /* Cortex-M3/M4 has 4096 bytes autoincrement range
1984 * but set a safe default to 1024 to support Cortex-M0
1985 * this will be changed in cortex_m3_examine if a M3/M4 is detected */
1986 armv7m
->dap
.tar_autoincr_block
= (1 << 10);
1988 /* register arch-specific functions */
1989 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
1991 armv7m
->post_debug_entry
= NULL
;
1993 armv7m
->pre_restore_context
= NULL
;
1995 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
1996 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
1998 target_register_timer_callback(cortex_m_handle_target_request
, 1, 1, target
);
2000 retval
= arm_jtag_setup_connection(&cortex_m
->jtag_info
);
2001 if (retval
!= ERROR_OK
)
2007 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2009 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2011 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2012 cortex_m_init_arch_info(target
, cortex_m
, target
->tap
);
2017 /*--------------------------------------------------------------------------*/
2019 static int cortex_m_verify_pointer(struct command_context
*cmd_ctx
,
2020 struct cortex_m_common
*cm
)
2022 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2023 command_print(cmd_ctx
, "target is not a Cortex-M");
2024 return ERROR_TARGET_INVALID
;
2030 * Only stuff below this line should need to verify that its target
2031 * is a Cortex-M3. Everything else should have indirected through the
2032 * cortexm3_target structure, which is only used with CM3 targets.
2035 static const struct {
2039 { "hard_err", VC_HARDERR
, },
2040 { "int_err", VC_INTERR
, },
2041 { "bus_err", VC_BUSERR
, },
2042 { "state_err", VC_STATERR
, },
2043 { "chk_err", VC_CHKERR
, },
2044 { "nocp_err", VC_NOCPERR
, },
2045 { "mm_err", VC_MMERR
, },
2046 { "reset", VC_CORERESET
, },
2049 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2051 struct target
*target
= get_current_target(CMD_CTX
);
2052 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2053 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2054 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
2058 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2059 if (retval
!= ERROR_OK
)
2062 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2063 if (retval
!= ERROR_OK
)
2069 if (CMD_ARGC
== 1) {
2070 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2071 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2072 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2073 | VC_MMERR
| VC_CORERESET
;
2075 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2078 while (CMD_ARGC
-- > 0) {
2080 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2081 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2083 catch |= vec_ids
[i
].mask
;
2086 if (i
== ARRAY_SIZE(vec_ids
)) {
2087 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2088 return ERROR_COMMAND_SYNTAX_ERROR
;
2092 /* For now, armv7m->demcr only stores vector catch flags. */
2093 armv7m
->demcr
= catch;
2098 /* write, but don't assume it stuck (why not??) */
2099 retval
= mem_ap_write_u32(swjdp
, DCB_DEMCR
, demcr
);
2100 if (retval
!= ERROR_OK
)
2102 retval
= mem_ap_read_atomic_u32(swjdp
, DCB_DEMCR
, &demcr
);
2103 if (retval
!= ERROR_OK
)
2106 /* FIXME be sure to clear DEMCR on clean server shutdown.
2107 * Otherwise the vector catch hardware could fire when there's
2108 * no debugger hooked up, causing much confusion...
2112 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2113 command_print(CMD_CTX
, "%9s: %s", vec_ids
[i
].name
,
2114 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2120 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2122 struct target
*target
= get_current_target(CMD_CTX
);
2123 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2126 static const Jim_Nvp nvp_maskisr_modes
[] = {
2127 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2128 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2129 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2130 { .name
= NULL
, .value
= -1 },
2135 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2136 if (retval
!= ERROR_OK
)
2139 if (target
->state
!= TARGET_HALTED
) {
2140 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
2145 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2146 if (n
->name
== NULL
)
2147 return ERROR_COMMAND_SYNTAX_ERROR
;
2148 cortex_m
->isrmasking_mode
= n
->value
;
2151 if (cortex_m
->isrmasking_mode
== CORTEX_M_ISRMASK_ON
)
2152 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
2154 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_MASKINTS
);
2157 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2158 command_print(CMD_CTX
, "cortex_m interrupt mask %s", n
->name
);
2163 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2165 struct target
*target
= get_current_target(CMD_CTX
);
2166 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2170 retval
= cortex_m_verify_pointer(CMD_CTX
, cortex_m
);
2171 if (retval
!= ERROR_OK
)
2175 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2176 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2177 else if (strcmp(*CMD_ARGV
, "vectreset") == 0)
2178 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2181 switch (cortex_m
->soft_reset_config
) {
2182 case CORTEX_M_RESET_SYSRESETREQ
:
2183 reset_config
= "sysresetreq";
2186 case CORTEX_M_RESET_VECTRESET
:
2187 reset_config
= "vectreset";
2191 reset_config
= "unknown";
2195 command_print(CMD_CTX
, "cortex_m reset_config %s", reset_config
);
2200 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2203 .handler
= handle_cortex_m_mask_interrupts_command
,
2204 .mode
= COMMAND_EXEC
,
2205 .help
= "mask cortex_m interrupts",
2206 .usage
= "['auto'|'on'|'off']",
2209 .name
= "vector_catch",
2210 .handler
= handle_cortex_m_vector_catch_command
,
2211 .mode
= COMMAND_EXEC
,
2212 .help
= "configure hardware vectors to trigger debug entry",
2213 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2216 .name
= "reset_config",
2217 .handler
= handle_cortex_m_reset_config_command
,
2218 .mode
= COMMAND_ANY
,
2219 .help
= "configure software reset handling",
2220 .usage
= "['srst'|'sysresetreq'|'vectreset']",
2222 COMMAND_REGISTRATION_DONE
2224 static const struct command_registration cortex_m_command_handlers
[] = {
2226 .chain
= armv7m_command_handlers
,
2230 .mode
= COMMAND_EXEC
,
2231 .help
= "Cortex-M command group",
2233 .chain
= cortex_m_exec_command_handlers
,
2235 COMMAND_REGISTRATION_DONE
2238 struct target_type cortexm_target
= {
2240 .deprecated_name
= "cortex_m3",
2242 .poll
= cortex_m_poll
,
2243 .arch_state
= armv7m_arch_state
,
2245 .target_request_data
= cortex_m_target_request_data
,
2247 .halt
= cortex_m_halt
,
2248 .resume
= cortex_m_resume
,
2249 .step
= cortex_m_step
,
2251 .assert_reset
= cortex_m_assert_reset
,
2252 .deassert_reset
= cortex_m_deassert_reset
,
2253 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2255 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2257 .read_memory
= cortex_m_read_memory
,
2258 .write_memory
= cortex_m_write_memory
,
2259 .checksum_memory
= armv7m_checksum_memory
,
2260 .blank_check_memory
= armv7m_blank_check_memory
,
2262 .run_algorithm
= armv7m_run_algorithm
,
2263 .start_algorithm
= armv7m_start_algorithm
,
2264 .wait_algorithm
= armv7m_wait_algorithm
,
2266 .add_breakpoint
= cortex_m_add_breakpoint
,
2267 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2268 .add_watchpoint
= cortex_m_add_watchpoint
,
2269 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2271 .commands
= cortex_m_command_handlers
,
2272 .target_create
= cortex_m_target_create
,
2273 .init_target
= cortex_m_init_target
,
2274 .examine
= cortex_m_examine
,