src/target/arm11.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2008 digenius technology GmbH.                          *
   5  *   Michael Bruck                                                         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  ***************************************************************************/
   9
  10 #ifndef OPENOCD_TARGET_ARM11_H
  11 #define OPENOCD_TARGET_ARM11_H
  12
  13 #include "arm.h"
  14 #include "arm_dpm.h"
  15
  16 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  17
  18 #define CHECK_RETVAL(action)                    \
  19         do {                                    \
  20                 int __retval = (action);        \
  21                 if (__retval != ERROR_OK) {     \
  22                         LOG_DEBUG("error while calling \"%s\"", \
  23                                 # action);     \
  24                         return __retval;        \
  25                 }                               \
  26         } while (0)
  27
  28 /* bits from ARMv7 DIDR */
  29 enum arm11_debug_version {
  30         ARM11_DEBUG_V6                  = 0x01,
  31         ARM11_DEBUG_V61                 = 0x02,
  32         ARM11_DEBUG_V7                  = 0x03,
  33         ARM11_DEBUG_V7_CP14             = 0x04,
  34 };
  35
  36 struct arm11_common {
  37         struct arm arm;
  38
  39         /** Debug module state. */
  40         struct arm_dpm dpm;
  41         struct arm11_sc7_action *bpwp_actions;
  42         unsigned bpwp_n;
  43
  44         size_t brp;                     /**< Number of Breakpoint Register Pairs from DIDR      */
  45         size_t free_brps;               /**< Number of breakpoints allocated */
  46
  47         uint32_t dscr;                  /**< Last retrieved DSCR value. */
  48
  49         uint32_t saved_rdtr;
  50         uint32_t saved_wdtr;
  51
  52         bool is_rdtr_saved;
  53         bool is_wdtr_saved;
  54
  55         bool simulate_reset_on_next_halt;       /**< Perform cleanups of the ARM state on next halt **/
  56
  57         /* Per-core configurable options.
  58          * NOTE that several of these boolean options should not exist
  59          * once the relevant code is known to work correctly.
  60          */
  61         bool memwrite_burst;
  62         bool memwrite_error_fatal;
  63         bool step_irq_enable;
  64         bool hardware_step;
  65
  66         /** Configured Vector Catch Register settings. */
  67         uint32_t vcr;
  68
  69         struct arm_jtag jtag_info;
  70 };
  71
  72 static inline struct arm11_common *target_to_arm11(struct target *target)
  73 {
  74         return container_of(target->arch_info, struct arm11_common, arm);
  75 }
  76
  77 /**
  78  * ARM11 DBGTAP instructions
  79  *
  80  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  81  */
  82 enum arm11_instructions {
  83         ARM11_EXTEST    = 0x00,
  84         ARM11_SCAN_N    = 0x02,
  85         ARM11_RESTART   = 0x04,
  86         ARM11_HALT          = 0x08,
  87         ARM11_INTEST    = 0x0C,
  88         ARM11_ITRSEL    = 0x1D,
  89         ARM11_IDCODE    = 0x1E,
  90         ARM11_BYPASS    = 0x1F,
  91 };
  92
  93 enum arm11_sc7 {
  94         ARM11_SC7_NULL                          = 0,
  95         ARM11_SC7_VCR                           = 7,
  96         ARM11_SC7_PC                            = 8,
  97         ARM11_SC7_BVR0                          = 64,
  98         ARM11_SC7_BCR0                          = 80,
  99         ARM11_SC7_WVR0                          = 96,
 100         ARM11_SC7_WCR0                          = 112,
 101 };
 102
 103 #endif /* OPENOCD_TARGET_ARM11_H */