| blob | e0a348ef08f9df594544cb653c81fb10982d1e19 |
1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # This is a stm32h747i-disco with a single STM32H747XIH6 chip.
4 # www.st.com/en/product/stm32h747i-disco.html
5 #
7 # This is for using the onboard STLINK
8 source [find interface/stlink.cfg]
10 transport select hla_swd
12 set CHIPNAME stm32h747xih6
14 # enable stmqspi
15 if {![info exists QUADSPI]} {
16 set QUADSPI 1
17 }
19 source [find target/stm32h7x_dual_bank.cfg]
21 reset_config srst_only
23 # QUADSPI initialization
24 # qpi: 4-line mode
25 proc qspi_init { qpi } {
26 global a
27 mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
28 mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
29 sleep 1 ;# Wait for clock startup
31 # PG06: BK1_NCS, PB02: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
32 # PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
34 # PB02:AF09:V, PD11:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
35 # PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
37 # Port B: PB02:AF09:V
38 mmw 0x58020400 0x00000020 0x00000010 ;# MODER
39 mmw 0x58020408 0x00000030 0x00000000 ;# OSPEEDR
40 mmw 0x58020420 0x00000900 0x00000600 ;# AFRL
41 # Port D: PD11:AF09:V
42 mmw 0x58020C00 0x00800000 0x00400000 ;# MODER
43 mmw 0x58020C08 0x00C00000 0x00000000 ;# OSPEEDR
44 mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH
45 # Port F: PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
46 mmw 0x58021400 0x0008A000 0x00045000 ;# MODER
47 mmw 0x58021408 0x000CF000 0x00000000 ;# OSPEEDR
48 mmw 0x58021420 0x99000000 0x66000000 ;# AFRL
49 mmw 0x58021424 0x000000A0 0x00000050 ;# AFRH
50 # Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
51 mmw 0x58021800 0x20082000 0x10041000 ;# MODER
52 mmw 0x58021808 0x200C2000 0x10001000 ;# OSPEEDR
53 mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL
54 mmw 0x58021824 0x09000090 0x06000060 ;# AFRH
55 # Port H: PH03:AF09:V, PH02:AF09:V
56 mmw 0x58021C00 0x000000A0 0x00000050 ;# MODER
57 mmw 0x58021C08 0x000000F0 0x00000000 ;# OSPEEDR
58 mmw 0x58021C20 0x00009900 0x00006600 ;# AFRL
60 # correct FSIZE is 0x1A, however, this causes trouble when
61 # reading the last bytes at end of bank in *memory mapped* mode
63 # for dual flash mode 2 * mt25ql512
64 mww 0x52005000 0x05500058 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
65 mww 0x52005004 0x001A0200 ;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
67 mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
68 mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
69 mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1
71 # Exit QPI mode
72 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
73 mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
74 sleep 1
76 if { $qpi == 1 } {
77 # Write Enable
78 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
79 mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
80 sleep 1
82 # Configure dummy clocks via volatile configuration register
83 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
84 mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
85 mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
86 mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
87 sleep 1
89 # Write Enable
90 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
91 mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
92 sleep 1
94 # Enable QPI mode via enhanced volatile configuration register
95 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
96 mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
97 mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
98 mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
99 sleep 1
101 # Enter QPI mode
102 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
103 mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
104 sleep 1
106 # memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
107 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
108 mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
109 } else {
110 # memory-mapped read mode with 4-byte addresses
111 mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
112 mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
113 }
114 }
116 $_CHIPNAME.cpu0 configure -event reset-init {
117 global QUADSPI
119 mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
121 mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
122 mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
123 mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
124 mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
125 mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
126 mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
127 mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
128 mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
129 mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
130 sleep 1
131 mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
132 sleep 1
134 adapter speed 24000
136 if { $QUADSPI } {
137 qspi_init 1
138 }
139 }