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Cortex-A8: remove previous mcr()/mrc() methods
[openocd.git] / src / target / cortex_a8.c
blobe312e547615842bd45259705a7064f3320530de5
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 * *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
30 * *
31 ***************************************************************************/
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "breakpoints.h"
37 #include "cortex_a8.h"
38 #include "register.h"
39 #include "target_request.h"
40 #include "target_type.h"
41
42 static int cortex_a8_poll(struct target *target);
43 static int cortex_a8_debug_entry(struct target *target);
44 static int cortex_a8_restore_context(struct target *target);
45 static int cortex_a8_set_breakpoint(struct target *target,
46 struct breakpoint *breakpoint, uint8_t matchmode);
47 static int cortex_a8_unset_breakpoint(struct target *target,
48 struct breakpoint *breakpoint);
49 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
50 uint32_t *value, int regnum);
51 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
52 uint32_t value, int regnum);
53 /*
54 * FIXME do topology discovery using the ROM; don't
55 * assume this is an OMAP3.
56 */
57 #define swjdp_memoryap 0
58 #define swjdp_debugap 1
59 #define OMAP3530_DEBUG_BASE 0x54011000
60
61 /*
62 * Cortex-A8 Basic debug access, very low level assumes state is saved
63 */
64 static int cortex_a8_init_debug_access(struct target *target)
65 {
66 struct armv7a_common *armv7a = target_to_armv7a(target);
67 struct swjdp_common *swjdp = &armv7a->swjdp_info;
68
69 int retval;
70 uint32_t dummy;
71
72 LOG_DEBUG(" ");
73
74 /* Unlocking the debug registers for modification */
75 /* The debugport might be uninitialised so try twice */
76 retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
77 if (retval != ERROR_OK)
78 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
79 /* Clear Sticky Power Down status Bit in PRSR to enable access to
80 the registers in the Core Power Domain */
81 retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
82 /* Enabling of instruction execution in debug mode is done in debug_entry code */
83
84 /* Resync breakpoint registers */
85
86 /* Since this is likley called from init or reset, update targtet state information*/
87 cortex_a8_poll(target);
88
89 return retval;
90 }
91
92 /* To reduce needless round-trips, pass in a pointer to the current
93 * DSCR value. Initialize it to zero if you just need to know the
94 * value on return from this function; or (1 << DSCR_INSTR_COMP) if
95 * you happen to know that no instruction is pending.
96 */
97 static int cortex_a8_exec_opcode(struct target *target,
98 uint32_t opcode, uint32_t *dscr_p)
99 {
100 uint32_t dscr;
101 int retval;
102 struct armv7a_common *armv7a = target_to_armv7a(target);
103 struct swjdp_common *swjdp = &armv7a->swjdp_info;
104
105 dscr = dscr_p ? *dscr_p : 0;
106
107 LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
108
109 /* Wait for InstrCompl bit to be set */
110 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
111 {
112 retval = mem_ap_read_atomic_u32(swjdp,
113 armv7a->debug_base + CPUDBG_DSCR, &dscr);
114 if (retval != ERROR_OK)
115 {
116 LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
117 return retval;
118 }
119 }
120
121 mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
122
123 do
124 {
125 retval = mem_ap_read_atomic_u32(swjdp,
126 armv7a->debug_base + CPUDBG_DSCR, &dscr);
127 if (retval != ERROR_OK)
128 {
129 LOG_ERROR("Could not read DSCR register");
130 return retval;
131 }
132 }
133 while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
134
135 if (dscr_p)
136 *dscr_p = dscr;
137
138 return retval;
139 }
140
141 /**************************************************************************
142 Read core register with very few exec_opcode, fast but needs work_area.
143 This can cause problems with MMU active.
144 **************************************************************************/
145 static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
146 uint32_t * regfile)
147 {
148 int retval = ERROR_OK;
149 struct armv7a_common *armv7a = target_to_armv7a(target);
150 struct swjdp_common *swjdp = &armv7a->swjdp_info;
151
152 cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
153 cortex_a8_dap_write_coreregister_u32(target, address, 0);
154 cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
155 dap_ap_select(swjdp, swjdp_memoryap);
156 mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
157 dap_ap_select(swjdp, swjdp_debugap);
158
159 return retval;
160 }
161
162 static int cortex_a8_dap_read_coreregister_u32(struct target *target,
163 uint32_t *value, int regnum)
164 {
165 int retval = ERROR_OK;
166 uint8_t reg = regnum&0xFF;
167 uint32_t dscr = 0;
168 struct armv7a_common *armv7a = target_to_armv7a(target);
169 struct swjdp_common *swjdp = &armv7a->swjdp_info;
170
171 if (reg > 17)
172 return retval;
173
174 if (reg < 15)
175 {
176 /* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
177 cortex_a8_exec_opcode(target,
178 ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
179 &dscr);
180 }
181 else if (reg == 15)
182 {
183 /* "MOV r0, r15"; then move r0 to DCCTX */
184 cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
185 cortex_a8_exec_opcode(target,
186 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
187 &dscr);
188 }
189 else
190 {
191 /* "MRS r0, CPSR" or "MRS r0, SPSR"
192 * then move r0 to DCCTX
193 */
194 cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
195 cortex_a8_exec_opcode(target,
196 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
197 &dscr);
198 }
199
200 /* Wait for DTRRXfull then read DTRRTX */
201 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
202 {
203 retval = mem_ap_read_atomic_u32(swjdp,
204 armv7a->debug_base + CPUDBG_DSCR, &dscr);
205 }
206
207 retval = mem_ap_read_atomic_u32(swjdp,
208 armv7a->debug_base + CPUDBG_DTRTX, value);
209 LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
210
211 return retval;
212 }
213
214 static int cortex_a8_dap_write_coreregister_u32(struct target *target,
215 uint32_t value, int regnum)
216 {
217 int retval = ERROR_OK;
218 uint8_t Rd = regnum&0xFF;
219 uint32_t dscr;
220 struct armv7a_common *armv7a = target_to_armv7a(target);
221 struct swjdp_common *swjdp = &armv7a->swjdp_info;
222
223 LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
224
225 /* Check that DCCRX is not full */
226 retval = mem_ap_read_atomic_u32(swjdp,
227 armv7a->debug_base + CPUDBG_DSCR, &dscr);
228 if (dscr & (1 << DSCR_DTR_RX_FULL))
229 {
230 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
231 /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
232 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
233 &dscr);
234 }
235
236 if (Rd > 17)
237 return retval;
238
239 /* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
240 LOG_DEBUG("write DCC 0x%08" PRIx32, value);
241 retval = mem_ap_write_u32(swjdp,
242 armv7a->debug_base + CPUDBG_DTRRX, value);
243
244 if (Rd < 15)
245 {
246 /* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
247 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
248 &dscr);
249 }
250 else if (Rd == 15)
251 {
252 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
253 * then "mov r15, r0"
254 */
255 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
256 &dscr);
257 cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
258 }
259 else
260 {
261 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
262 * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
263 */
264 cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
265 &dscr);
266 cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
267 &dscr);
268
269 /* "Prefetch flush" after modifying execution status in CPSR */
270 if (Rd == 16)
271 cortex_a8_exec_opcode(target,
272 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
273 &dscr);
274 }
275
276 return retval;
277 }
278
279 /* Write to memory mapped registers directly with no cache or mmu handling */
280 static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
281 {
282 int retval;
283 struct armv7a_common *armv7a = target_to_armv7a(target);
284 struct swjdp_common *swjdp = &armv7a->swjdp_info;
285
286 retval = mem_ap_write_atomic_u32(swjdp, address, value);
287
288 return retval;
289 }
290
291 /*
292 * Cortex-A8 implementation of Debug Programmer's Model
293 *
294 * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
295 * so there's no need to poll for it before executing an instruction.
296 *
297 * NOTE that in several of these cases the "stall" mode might be useful.
298 * It'd let us queue a few operations together... prepare/finish might
299 * be the places to enable/disable that mode.
300 */
301
302 static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
303 {
304 return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
305 }
306
307 static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
308 {
309 LOG_DEBUG("write DCC 0x%08" PRIx32, data);
310 return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
311 a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
312 }
313
314 static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
315 uint32_t *dscr_p)
316 {
317 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
318 uint32_t dscr = 1 << DSCR_INSTR_COMP;
319 int retval;
320
321 if (dscr_p)
322 dscr = *dscr_p;
323
324 /* Wait for DTRRXfull */
325 while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
326 retval = mem_ap_read_atomic_u32(swjdp,
327 a8->armv7a_common.debug_base + CPUDBG_DSCR,
328 &dscr);
329 }
330
331 retval = mem_ap_read_atomic_u32(swjdp,
332 a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
333 //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
334
335 if (dscr_p)
336 *dscr_p = dscr;
337
338 return retval;
339 }
340
341 static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
342 {
343 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
344 struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
345 uint32_t dscr;
346 int retval;
347
348 /* set up invariant: INSTR_COMP is set after ever DPM operation */
349 do {
350 retval = mem_ap_read_atomic_u32(swjdp,
351 a8->armv7a_common.debug_base + CPUDBG_DSCR,
352 &dscr);
353 } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
354
355 /* this "should never happen" ... */
356 if (dscr & (1 << DSCR_DTR_RX_FULL)) {
357 LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
358 /* Clear DCCRX */
359 retval = cortex_a8_exec_opcode(
360 a8->armv7a_common.armv4_5_common.target,
361 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
362 &dscr);
363 }
364
365 return retval;
366 }
367
368 static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
369 {
370 /* REVISIT what could be done here? */
371 return ERROR_OK;
372 }
373
374 static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
375 uint32_t opcode, uint32_t data)
376 {
377 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
378 int retval;
379 uint32_t dscr = 1 << DSCR_INSTR_COMP;
380
381 retval = cortex_a8_write_dcc(a8, data);
382
383 return cortex_a8_exec_opcode(
384 a8->armv7a_common.armv4_5_common.target,
385 opcode,
386 &dscr);
387 }
388
389 static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
390 uint32_t opcode, uint32_t data)
391 {
392 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
393 uint32_t dscr = 1 << DSCR_INSTR_COMP;
394 int retval;
395
396 retval = cortex_a8_write_dcc(a8, data);
397
398 /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
399 retval = cortex_a8_exec_opcode(
400 a8->armv7a_common.armv4_5_common.target,
401 ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
402 &dscr);
403
404 /* then the opcode, taking data from R0 */
405 retval = cortex_a8_exec_opcode(
406 a8->armv7a_common.armv4_5_common.target,
407 opcode,
408 &dscr);
409
410 return retval;
411 }
412
413 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
414 {
415 struct target *target = dpm->arm->target;
416 uint32_t dscr = 1 << DSCR_INSTR_COMP;
417
418 /* "Prefetch flush" after modifying execution status in CPSR */
419 return cortex_a8_exec_opcode(target,
420 ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
421 &dscr);
422 }
423
424 static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
425 uint32_t opcode, uint32_t *data)
426 {
427 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
428 int retval;
429 uint32_t dscr = 1 << DSCR_INSTR_COMP;
430
431 /* the opcode, writing data to DCC */
432 retval = cortex_a8_exec_opcode(
433 a8->armv7a_common.armv4_5_common.target,
434 opcode,
435 &dscr);
436
437 return cortex_a8_read_dcc(a8, data, &dscr);
438 }
439
440
441 static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
442 uint32_t opcode, uint32_t *data)
443 {
444 struct cortex_a8_common *a8 = dpm_to_a8(dpm);
445 uint32_t dscr = 1 << DSCR_INSTR_COMP;
446 int retval;
447
448 /* the opcode, writing data to R0 */
449 retval = cortex_a8_exec_opcode(
450 a8->armv7a_common.armv4_5_common.target,
451 opcode,
452 &dscr);
453
454 /* write R0 to DCC */
455 retval = cortex_a8_exec_opcode(
456 a8->armv7a_common.armv4_5_common.target,
457 ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
458 &dscr);
459
460 return cortex_a8_read_dcc(a8, data, &dscr);
461 }
462
463 static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
464 {
465 struct arm_dpm *dpm = &a8->armv7a_common.dpm;
466
467 dpm->arm = &a8->armv7a_common.armv4_5_common;
468 dpm->didr = didr;
469
470 dpm->prepare = cortex_a8_dpm_prepare;
471 dpm->finish = cortex_a8_dpm_finish;
472
473 dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
474 dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
475 dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
476
477 dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
478 dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
479
480 return arm_dpm_setup(dpm);
481 }
482
483
484 /*
485 * Cortex-A8 Run control
486 */
487
488 static int cortex_a8_poll(struct target *target)
489 {
490 int retval = ERROR_OK;
491 uint32_t dscr;
492 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
493 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
494 struct swjdp_common *swjdp = &armv7a->swjdp_info;
495 enum target_state prev_target_state = target->state;
496 uint8_t saved_apsel = dap_ap_get_select(swjdp);
497
498 dap_ap_select(swjdp, swjdp_debugap);
499 retval = mem_ap_read_atomic_u32(swjdp,
500 armv7a->debug_base + CPUDBG_DSCR, &dscr);
501 if (retval != ERROR_OK)
502 {
503 dap_ap_select(swjdp, saved_apsel);
504 return retval;
505 }
506 cortex_a8->cpudbg_dscr = dscr;
507
508 if ((dscr & 0x3) == 0x3)
509 {
510 if (prev_target_state != TARGET_HALTED)
511 {
512 /* We have a halting debug event */
513 LOG_DEBUG("Target halted");
514 target->state = TARGET_HALTED;
515 if ((prev_target_state == TARGET_RUNNING)
516 || (prev_target_state == TARGET_RESET))
517 {
518 retval = cortex_a8_debug_entry(target);
519 if (retval != ERROR_OK)
520 return retval;
521
522 target_call_event_callbacks(target,
523 TARGET_EVENT_HALTED);
524 }
525 if (prev_target_state == TARGET_DEBUG_RUNNING)
526 {
527 LOG_DEBUG(" ");
528
529 retval = cortex_a8_debug_entry(target);
530 if (retval != ERROR_OK)
531 return retval;
532
533 target_call_event_callbacks(target,
534 TARGET_EVENT_DEBUG_HALTED);
535 }
536 }
537 }
538 else if ((dscr & 0x3) == 0x2)
539 {
540 target->state = TARGET_RUNNING;
541 }
542 else
543 {
544 LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
545 target->state = TARGET_UNKNOWN;
546 }
547
548 dap_ap_select(swjdp, saved_apsel);
549
550 return retval;
551 }
552
553 static int cortex_a8_halt(struct target *target)
554 {
555 int retval = ERROR_OK;
556 uint32_t dscr;
557 struct armv7a_common *armv7a = target_to_armv7a(target);
558 struct swjdp_common *swjdp = &armv7a->swjdp_info;
559 uint8_t saved_apsel = dap_ap_get_select(swjdp);
560 dap_ap_select(swjdp, swjdp_debugap);
561
562 /*
563 * Tell the core to be halted by writing DRCR with 0x1
564 * and then wait for the core to be halted.
565 */
566 retval = mem_ap_write_atomic_u32(swjdp,
567 armv7a->debug_base + CPUDBG_DRCR, 0x1);
568
569 /*
570 * enter halting debug mode
571 */
572 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
573 retval = mem_ap_write_atomic_u32(swjdp,
574 armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
575
576 if (retval != ERROR_OK)
577 goto out;
578
579 do {
580 mem_ap_read_atomic_u32(swjdp,
581 armv7a->debug_base + CPUDBG_DSCR, &dscr);
582 } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
583
584 target->debug_reason = DBG_REASON_DBGRQ;
585
586 out:
587 dap_ap_select(swjdp, saved_apsel);
588 return retval;
589 }
590
591 static int cortex_a8_resume(struct target *target, int current,
592 uint32_t address, int handle_breakpoints, int debug_execution)
593 {
594 struct armv7a_common *armv7a = target_to_armv7a(target);
595 struct arm *armv4_5 = &armv7a->armv4_5_common;
596 struct swjdp_common *swjdp = &armv7a->swjdp_info;
597
598 // struct breakpoint *breakpoint = NULL;
599 uint32_t resume_pc, dscr;
600
601 uint8_t saved_apsel = dap_ap_get_select(swjdp);
602 dap_ap_select(swjdp, swjdp_debugap);
603
604 if (!debug_execution)
605 {
606 target_free_all_working_areas(target);
607 // cortex_m3_enable_breakpoints(target);
608 // cortex_m3_enable_watchpoints(target);
609 }
610
611 #if 0
612 if (debug_execution)
613 {
614 /* Disable interrupts */
615 /* We disable interrupts in the PRIMASK register instead of
616 * masking with C_MASKINTS,
617 * This is probably the same issue as Cortex-M3 Errata 377493:
618 * C_MASKINTS in parallel with disabled interrupts can cause
619 * local faults to not be taken. */
620 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
621 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
622 armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
623
624 /* Make sure we are in Thumb mode */
625 buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
626 buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
627 armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
628 armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
629 }
630 #endif
631
632 /* current = 1: continue on current pc, otherwise continue at <address> */
633 resume_pc = buf_get_u32(
634 armv4_5->core_cache->reg_list[15].value,
635 0, 32);
636 if (!current)
637 resume_pc = address;
638
639 /* Make sure that the Armv7 gdb thumb fixups does not
640 * kill the return address
641 */
642 switch (armv4_5->core_state)
643 {
644 case ARMV4_5_STATE_ARM:
645 resume_pc &= 0xFFFFFFFC;
646 break;
647 case ARMV4_5_STATE_THUMB:
648 case ARM_STATE_THUMB_EE:
649 /* When the return address is loaded into PC
650 * bit 0 must be 1 to stay in Thumb state
651 */
652 resume_pc |= 0x1;
653 break;
654 case ARMV4_5_STATE_JAZELLE:
655 LOG_ERROR("How do I resume into Jazelle state??");
656 return ERROR_FAIL;
657 }
658 LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
659 buf_set_u32(armv4_5->core_cache->reg_list[15].value,
660 0, 32, resume_pc);
661 armv4_5->core_cache->reg_list[15].dirty = 1;
662 armv4_5->core_cache->reg_list[15].valid = 1;
663
664 cortex_a8_restore_context(target);
665
666 #if 0
667 /* the front-end may request us not to handle breakpoints */
668 if (handle_breakpoints)
669 {
670 /* Single step past breakpoint at current address */
671 if ((breakpoint = breakpoint_find(target, resume_pc)))
672 {
673 LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
674 cortex_m3_unset_breakpoint(target, breakpoint);
675 cortex_m3_single_step_core(target);
676 cortex_m3_set_breakpoint(target, breakpoint);
677 }
678 }
679
680 #endif
681 /* Restart core and wait for it to be started */
682 mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
683
684 do {
685 mem_ap_read_atomic_u32(swjdp,
686 armv7a->debug_base + CPUDBG_DSCR, &dscr);
687 } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
688
689 target->debug_reason = DBG_REASON_NOTHALTED;
690 target->state = TARGET_RUNNING;
691
692 /* registers are now invalid */
693 register_cache_invalidate(armv4_5->core_cache);
694
695 if (!debug_execution)
696 {
697 target->state = TARGET_RUNNING;
698 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
699 LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
700 }
701 else
702 {
703 target->state = TARGET_DEBUG_RUNNING;
704 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
705 LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
706 }
707
708 dap_ap_select(swjdp, saved_apsel);
709
710 return ERROR_OK;
711 }
712
713 static int cortex_a8_debug_entry(struct target *target)
714 {
715 int i;
716 uint32_t regfile[16], pc, cpsr, dscr;
717 int retval = ERROR_OK;
718 struct working_area *regfile_working_area = NULL;
719 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
720 struct armv7a_common *armv7a = target_to_armv7a(target);
721 struct arm *armv4_5 = &armv7a->armv4_5_common;
722 struct swjdp_common *swjdp = &armv7a->swjdp_info;
723 struct reg *reg;
724
725 LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
726
727 /* Enable the ITR execution once we are in debug mode */
728 mem_ap_read_atomic_u32(swjdp,
729 armv7a->debug_base + CPUDBG_DSCR, &dscr);
730
731 /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
732 * imprecise data aborts get discarded by issuing a Data
733 * Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
734 */
735
736 dscr |= (1 << DSCR_EXT_INT_EN);
737 retval = mem_ap_write_atomic_u32(swjdp,
738 armv7a->debug_base + CPUDBG_DSCR, dscr);
739
740 /* Examine debug reason */
741 switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
742 {
743 case 0: /* DRCR[0] write */
744 case 4: /* EDBGRQ */
745 target->debug_reason = DBG_REASON_DBGRQ;
746 break;
747 case 1: /* HW breakpoint */
748 case 3: /* SW BKPT */
749 case 5: /* vector catch */
750 target->debug_reason = DBG_REASON_BREAKPOINT;
751 break;
752 case 10: /* precise watchpoint */
753 target->debug_reason = DBG_REASON_WATCHPOINT;
754 /* REVISIT could collect WFAR later, to see just
755 * which instruction triggered the watchpoint.
756 */
757 break;
758 default:
759 target->debug_reason = DBG_REASON_UNDEFINED;
760 break;
761 }
762
763 /* REVISIT fast_reg_read is never set ... */
764
765 /* Examine target state and mode */
766 if (cortex_a8->fast_reg_read)
767 target_alloc_working_area(target, 64, &regfile_working_area);
768
769 /* First load register acessible through core debug port*/
770 if (!regfile_working_area)
771 {
772 retval = arm_dpm_read_current_registers(&armv7a->dpm);
773 }
774 else
775 {
776 dap_ap_select(swjdp, swjdp_memoryap);
777 cortex_a8_read_regs_through_mem(target,
778 regfile_working_area->address, regfile);
779 dap_ap_select(swjdp, swjdp_memoryap);
780 target_free_working_area(target, regfile_working_area);
781
782 /* read Current PSR */
783 cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
784 pc = regfile[15];
785 dap_ap_select(swjdp, swjdp_debugap);
786 LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
787
788 arm_set_cpsr(armv4_5, cpsr);
789
790 /* update cache */
791 for (i = 0; i <= ARM_PC; i++)
792 {
793 reg = arm_reg_current(armv4_5, i);
794
795 buf_set_u32(reg->value, 0, 32, regfile[i]);
796 reg->valid = 1;
797 reg->dirty = 0;
798 }
799
800 /* Fixup PC Resume Address */
801 if (cpsr & (1 << 5))
802 {
803 // T bit set for Thumb or ThumbEE state
804 regfile[ARM_PC] -= 4;
805 }
806 else
807 {
808 // ARM state
809 regfile[ARM_PC] -= 8;
810 }
811
812 reg = armv4_5->core_cache->reg_list + 15;
813 buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
814 reg->dirty = reg->valid;
815 }
816
817 #if 0
818 /* TODO, Move this */
819 uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
820 cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
821 LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
822
823 cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
824 LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
825
826 cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
827 LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
828 #endif
829
830 /* Are we in an exception handler */
831 // armv4_5->exception_number = 0;
832 if (armv7a->post_debug_entry)
833 armv7a->post_debug_entry(target);
834
835
836
837 return retval;
838
839 }
840
841 static void cortex_a8_post_debug_entry(struct target *target)
842 {
843 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
844 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
845 int retval;
846
847 /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
848 retval = armv7a->armv4_5_common.mrc(target, 15,
849 0, 0, /* op1, op2 */
850 1, 0, /* CRn, CRm */
851 &cortex_a8->cp15_control_reg);
852 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
853
854 if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
855 {
856 uint32_t cache_type_reg;
857
858 /* MRC p15,0,<Rt>,c0,c0,1 ; Read CP15 Cache Type Register */
859 retval = armv7a->armv4_5_common.mrc(target, 15,
860 0, 1, /* op1, op2 */
861 0, 0, /* CRn, CRm */
862 &cache_type_reg);
863 LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
864
865 /* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
866 armv4_5_identify_cache(cache_type_reg,
867 &armv7a->armv4_5_mmu.armv4_5_cache);
868 }
869
870 armv7a->armv4_5_mmu.mmu_enabled =
871 (cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
872 armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
873 (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
874 armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
875 (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
876
877
878 }
879
880 static int cortex_a8_step(struct target *target, int current, uint32_t address,
881 int handle_breakpoints)
882 {
883 struct armv7a_common *armv7a = target_to_armv7a(target);
884 struct arm *armv4_5 = &armv7a->armv4_5_common;
885 struct breakpoint *breakpoint = NULL;
886 struct breakpoint stepbreakpoint;
887 struct reg *r;
888
889 int timeout = 100;
890
891 if (target->state != TARGET_HALTED)
892 {
893 LOG_WARNING("target not halted");
894 return ERROR_TARGET_NOT_HALTED;
895 }
896
897 /* current = 1: continue on current pc, otherwise continue at <address> */
898 r = armv4_5->core_cache->reg_list + 15;
899 if (!current)
900 {
901 buf_set_u32(r->value, 0, 32, address);
902 }
903 else
904 {
905 address = buf_get_u32(r->value, 0, 32);
906 }
907
908 /* The front-end may request us not to handle breakpoints.
909 * But since Cortex-A8 uses breakpoint for single step,
910 * we MUST handle breakpoints.
911 */
912 handle_breakpoints = 1;
913 if (handle_breakpoints) {
914 breakpoint = breakpoint_find(target, address);
915 if (breakpoint)
916 cortex_a8_unset_breakpoint(target, breakpoint);
917 }
918
919 /* Setup single step breakpoint */
920 stepbreakpoint.address = address;
921 stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
922 ? 2 : 4;
923 stepbreakpoint.type = BKPT_HARD;
924 stepbreakpoint.set = 0;
925
926 /* Break on IVA mismatch */
927 cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
928
929 target->debug_reason = DBG_REASON_SINGLESTEP;
930
931 cortex_a8_resume(target, 1, address, 0, 0);
932
933 while (target->state != TARGET_HALTED)
934 {
935 cortex_a8_poll(target);
936 if (--timeout == 0)
937 {
938 LOG_WARNING("timeout waiting for target halt");
939 break;
940 }
941 }
942
943 cortex_a8_unset_breakpoint(target, &stepbreakpoint);
944 if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
945
946 if (breakpoint)
947 cortex_a8_set_breakpoint(target, breakpoint, 0);
948
949 if (target->state != TARGET_HALTED)
950 LOG_DEBUG("target stepped");
951
952 return ERROR_OK;
953 }
954
955 static int cortex_a8_restore_context(struct target *target)
956 {
957 struct armv7a_common *armv7a = target_to_armv7a(target);
958
959 LOG_DEBUG(" ");
960
961 if (armv7a->pre_restore_context)
962 armv7a->pre_restore_context(target);
963
964 arm_dpm_write_dirty_registers(&armv7a->dpm);
965
966 if (armv7a->post_restore_context)
967 armv7a->post_restore_context(target);
968
969 return ERROR_OK;
970 }
971
972
973 /*
974 * Cortex-A8 Breakpoint and watchpoint fuctions
975 */
976
977 /* Setup hardware Breakpoint Register Pair */
978 static int cortex_a8_set_breakpoint(struct target *target,
979 struct breakpoint *breakpoint, uint8_t matchmode)
980 {
981 int retval;
982 int brp_i=0;
983 uint32_t control;
984 uint8_t byte_addr_select = 0x0F;
985 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
986 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
987 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
988
989 if (breakpoint->set)
990 {
991 LOG_WARNING("breakpoint already set");
992 return ERROR_OK;
993 }
994
995 if (breakpoint->type == BKPT_HARD)
996 {
997 while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
998 brp_i++ ;
999 if (brp_i >= cortex_a8->brp_num)
1000 {
1001 LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
1002 return ERROR_FAIL;
1003 }
1004 breakpoint->set = brp_i + 1;
1005 if (breakpoint->length == 2)
1006 {
1007 byte_addr_select = (3 << (breakpoint->address & 0x02));
1008 }
1009 control = ((matchmode & 0x7) << 20)
1010 | (byte_addr_select << 5)
1011 | (3 << 1) | 1;
1012 brp_list[brp_i].used = 1;
1013 brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
1014 brp_list[brp_i].control = control;
1015 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1016 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1017 brp_list[brp_i].value);
1018 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1019 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1020 brp_list[brp_i].control);
1021 LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1022 brp_list[brp_i].control,
1023 brp_list[brp_i].value);
1024 }
1025 else if (breakpoint->type == BKPT_SOFT)
1026 {
1027 uint8_t code[4];
1028 if (breakpoint->length == 2)
1029 {
1030 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1031 }
1032 else
1033 {
1034 buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
1035 }
1036 retval = target->type->read_memory(target,
1037 breakpoint->address & 0xFFFFFFFE,
1038 breakpoint->length, 1,
1039 breakpoint->orig_instr);
1040 if (retval != ERROR_OK)
1041 return retval;
1042 retval = target->type->write_memory(target,
1043 breakpoint->address & 0xFFFFFFFE,
1044 breakpoint->length, 1, code);
1045 if (retval != ERROR_OK)
1046 return retval;
1047 breakpoint->set = 0x11; /* Any nice value but 0 */
1048 }
1049
1050 return ERROR_OK;
1051 }
1052
1053 static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1054 {
1055 int retval;
1056 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1057 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1058 struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
1059
1060 if (!breakpoint->set)
1061 {
1062 LOG_WARNING("breakpoint not set");
1063 return ERROR_OK;
1064 }
1065
1066 if (breakpoint->type == BKPT_HARD)
1067 {
1068 int brp_i = breakpoint->set - 1;
1069 if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
1070 {
1071 LOG_DEBUG("Invalid BRP number in breakpoint");
1072 return ERROR_OK;
1073 }
1074 LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
1075 brp_list[brp_i].control, brp_list[brp_i].value);
1076 brp_list[brp_i].used = 0;
1077 brp_list[brp_i].value = 0;
1078 brp_list[brp_i].control = 0;
1079 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1080 + CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
1081 brp_list[brp_i].control);
1082 cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
1083 + CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
1084 brp_list[brp_i].value);
1085 }
1086 else
1087 {
1088 /* restore original instruction (kept in target endianness) */
1089 if (breakpoint->length == 4)
1090 {
1091 retval = target->type->write_memory(target,
1092 breakpoint->address & 0xFFFFFFFE,
1093 4, 1, breakpoint->orig_instr);
1094 if (retval != ERROR_OK)
1095 return retval;
1096 }
1097 else
1098 {
1099 retval = target->type->write_memory(target,
1100 breakpoint->address & 0xFFFFFFFE,
1101 2, 1, breakpoint->orig_instr);
1102 if (retval != ERROR_OK)
1103 return retval;
1104 }
1105 }
1106 breakpoint->set = 0;
1107
1108 return ERROR_OK;
1109 }
1110
1111 static int cortex_a8_add_breakpoint(struct target *target,
1112 struct breakpoint *breakpoint)
1113 {
1114 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1115
1116 if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
1117 {
1118 LOG_INFO("no hardware breakpoint available");
1119 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1120 }
1121
1122 if (breakpoint->type == BKPT_HARD)
1123 cortex_a8->brp_num_available--;
1124 cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
1125
1126 return ERROR_OK;
1127 }
1128
1129 static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1130 {
1131 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1132
1133 #if 0
1134 /* It is perfectly possible to remove brakpoints while the taget is running */
1135 if (target->state != TARGET_HALTED)
1136 {
1137 LOG_WARNING("target not halted");
1138 return ERROR_TARGET_NOT_HALTED;
1139 }
1140 #endif
1141
1142 if (breakpoint->set)
1143 {
1144 cortex_a8_unset_breakpoint(target, breakpoint);
1145 if (breakpoint->type == BKPT_HARD)
1146 cortex_a8->brp_num_available++ ;
1147 }
1148
1149
1150 return ERROR_OK;
1151 }
1152
1153
1154
1155 /*
1156 * Cortex-A8 Reset fuctions
1157 */
1158
1159 static int cortex_a8_assert_reset(struct target *target)
1160 {
1161 struct armv7a_common *armv7a = target_to_armv7a(target);
1162
1163 LOG_DEBUG(" ");
1164
1165 /* FIXME when halt is requested, make it work somehow... */
1166
1167 /* Issue some kind of warm reset. */
1168 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1169 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1170 } else if (jtag_get_reset_config() & RESET_HAS_SRST) {
1171 /* REVISIT handle "pulls" cases, if there's
1172 * hardware that needs them to work.
1173 */
1174 jtag_add_reset(0, 1);
1175 } else {
1176 LOG_ERROR("%s: how to reset?", target_name(target));
1177 return ERROR_FAIL;
1178 }
1179
1180 /* registers are now invalid */
1181 register_cache_invalidate(armv7a->armv4_5_common.core_cache);
1182
1183 target->state = TARGET_RESET;
1184
1185 return ERROR_OK;
1186 }
1187
1188 static int cortex_a8_deassert_reset(struct target *target)
1189 {
1190 int retval;
1191
1192 LOG_DEBUG(" ");
1193
1194 /* be certain SRST is off */
1195 jtag_add_reset(0, 0);
1196
1197 retval = cortex_a8_poll(target);
1198
1199 if (target->reset_halt) {
1200 if (target->state != TARGET_HALTED) {
1201 LOG_WARNING("%s: ran after reset and before halt ...",
1202 target_name(target));
1203 if ((retval = target_halt(target)) != ERROR_OK)
1204 return retval;
1205 }
1206 }
1207
1208 return ERROR_OK;
1209 }
1210
1211 /*
1212 * Cortex-A8 Memory access
1213 *
1214 * This is same Cortex M3 but we must also use the correct
1215 * ap number for every access.
1216 */
1217
1218 static int cortex_a8_read_memory(struct target *target, uint32_t address,
1219 uint32_t size, uint32_t count, uint8_t *buffer)
1220 {
1221 struct armv7a_common *armv7a = target_to_armv7a(target);
1222 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1223 int retval = ERROR_INVALID_ARGUMENTS;
1224
1225 /* cortex_a8 handles unaligned memory access */
1226
1227 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1228
1229 if (count && buffer) {
1230 switch (size) {
1231 case 4:
1232 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1233 break;
1234 case 2:
1235 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1236 break;
1237 case 1:
1238 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1239 break;
1240 }
1241 }
1242
1243 return retval;
1244 }
1245
1246 static int cortex_a8_write_memory(struct target *target, uint32_t address,
1247 uint32_t size, uint32_t count, uint8_t *buffer)
1248 {
1249 struct armv7a_common *armv7a = target_to_armv7a(target);
1250 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1251 int retval = ERROR_INVALID_ARGUMENTS;
1252
1253 // ??? dap_ap_select(swjdp, swjdp_memoryap);
1254
1255 if (count && buffer) {
1256 switch (size) {
1257 case 4:
1258 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1259 break;
1260 case 2:
1261 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1262 break;
1263 case 1:
1264 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1265 break;
1266 }
1267 }
1268
1269 /* REVISIT this op is generic ARMv7-A/R stuff */
1270 if (retval == ERROR_OK && target->state == TARGET_HALTED)
1271 {
1272 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
1273
1274 retval = dpm->prepare(dpm);
1275 if (retval != ERROR_OK)
1276 return retval;
1277
1278 /* The Cache handling will NOT work with MMU active, the
1279 * wrong addresses will be invalidated!
1280 *
1281 * For both ICache and DCache, walk all cache lines in the
1282 * address range. Cortex-A8 has fixed 64 byte line length.
1283 */
1284
1285 /* invalidate I-Cache */
1286 if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
1287 {
1288 /* ICIMVAU - Invalidate Cache single entry
1289 * with MVA to PoU
1290 * MCR p15, 0, r0, c7, c5, 1
1291 */
1292 for (uint32_t cacheline = address;
1293 cacheline < address + size * count;
1294 cacheline += 64) {
1295 retval = dpm->instr_write_data_r0(dpm,
1296 ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
1297 cacheline);
1298 }
1299 }
1300
1301 /* invalidate D-Cache */
1302 if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
1303 {
1304 /* DCIMVAC - Invalidate data Cache line
1305 * with MVA to PoC
1306 * MCR p15, 0, r0, c7, c6, 1
1307 */
1308 for (uint32_t cacheline = address;
1309 cacheline < address + size * count;
1310 cacheline += 64) {
1311 retval = dpm->instr_write_data_r0(dpm,
1312 ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
1313 cacheline);
1314 }
1315 }
1316
1317 /* (void) */ dpm->finish(dpm);
1318 }
1319
1320 return retval;
1321 }
1322
1323 static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
1324 uint32_t count, uint8_t *buffer)
1325 {
1326 return cortex_a8_write_memory(target, address, 4, count, buffer);
1327 }
1328
1329
1330 static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
1331 {
1332 #if 0
1333 u16 dcrdr;
1334
1335 mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1336 *ctrl = (uint8_t)dcrdr;
1337 *value = (uint8_t)(dcrdr >> 8);
1338
1339 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1340
1341 /* write ack back to software dcc register
1342 * signify we have read data */
1343 if (dcrdr & (1 << 0))
1344 {
1345 dcrdr = 0;
1346 mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1347 }
1348 #endif
1349 return ERROR_OK;
1350 }
1351
1352
1353 static int cortex_a8_handle_target_request(void *priv)
1354 {
1355 struct target *target = priv;
1356 struct armv7a_common *armv7a = target_to_armv7a(target);
1357 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1358
1359 if (!target_was_examined(target))
1360 return ERROR_OK;
1361 if (!target->dbg_msg_enabled)
1362 return ERROR_OK;
1363
1364 if (target->state == TARGET_RUNNING)
1365 {
1366 uint8_t data = 0;
1367 uint8_t ctrl = 0;
1368
1369 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1370
1371 /* check if we have data */
1372 if (ctrl & (1 << 0))
1373 {
1374 uint32_t request;
1375
1376 /* we assume target is quick enough */
1377 request = data;
1378 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1379 request |= (data << 8);
1380 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1381 request |= (data << 16);
1382 cortex_a8_dcc_read(swjdp, &data, &ctrl);
1383 request |= (data << 24);
1384 target_request(target, request);
1385 }
1386 }
1387
1388 return ERROR_OK;
1389 }
1390
1391 /*
1392 * Cortex-A8 target information and configuration
1393 */
1394
1395 static int cortex_a8_examine_first(struct target *target)
1396 {
1397 struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
1398 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1399 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1400 int i;
1401 int retval = ERROR_OK;
1402 uint32_t didr, ctypr, ttypr, cpuid;
1403
1404 LOG_DEBUG("TODO");
1405
1406 /* Here we shall insert a proper ROM Table scan */
1407 armv7a->debug_base = OMAP3530_DEBUG_BASE;
1408
1409 /* We do one extra read to ensure DAP is configured,
1410 * we call ahbap_debugport_init(swjdp) instead
1411 */
1412 ahbap_debugport_init(swjdp);
1413 mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
1414 if ((retval = mem_ap_read_atomic_u32(swjdp,
1415 armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
1416 {
1417 LOG_DEBUG("Examine failed");
1418 return retval;
1419 }
1420
1421 if ((retval = mem_ap_read_atomic_u32(swjdp,
1422 armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
1423 {
1424 LOG_DEBUG("Examine failed");
1425 return retval;
1426 }
1427
1428 if ((retval = mem_ap_read_atomic_u32(swjdp,
1429 armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
1430 {
1431 LOG_DEBUG("Examine failed");
1432 return retval;
1433 }
1434
1435 if ((retval = mem_ap_read_atomic_u32(swjdp,
1436 armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
1437 {
1438 LOG_DEBUG("Examine failed");
1439 return retval;
1440 }
1441
1442 LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
1443 LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
1444 LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
1445 LOG_DEBUG("didr = 0x%08" PRIx32, didr);
1446
1447 armv7a->armv4_5_common.core_type = ARM_MODE_MON;
1448 cortex_a8_dpm_setup(cortex_a8, didr);
1449
1450 /* Setup Breakpoint Register Pairs */
1451 cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
1452 cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
1453 cortex_a8->brp_num_available = cortex_a8->brp_num;
1454 cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
1455 // cortex_a8->brb_enabled = ????;
1456 for (i = 0; i < cortex_a8->brp_num; i++)
1457 {
1458 cortex_a8->brp_list[i].used = 0;
1459 if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
1460 cortex_a8->brp_list[i].type = BRP_NORMAL;
1461 else
1462 cortex_a8->brp_list[i].type = BRP_CONTEXT;
1463 cortex_a8->brp_list[i].value = 0;
1464 cortex_a8->brp_list[i].control = 0;
1465 cortex_a8->brp_list[i].BRPn = i;
1466 }
1467
1468 /* Setup Watchpoint Register Pairs */
1469 cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
1470 cortex_a8->wrp_num_available = cortex_a8->wrp_num;
1471 cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
1472 for (i = 0; i < cortex_a8->wrp_num; i++)
1473 {
1474 cortex_a8->wrp_list[i].used = 0;
1475 cortex_a8->wrp_list[i].type = 0;
1476 cortex_a8->wrp_list[i].value = 0;
1477 cortex_a8->wrp_list[i].control = 0;
1478 cortex_a8->wrp_list[i].WRPn = i;
1479 }
1480 LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
1481 cortex_a8->brp_num , cortex_a8->wrp_num);
1482
1483 target_set_examined(target);
1484 return ERROR_OK;
1485 }
1486
1487 static int cortex_a8_examine(struct target *target)
1488 {
1489 int retval = ERROR_OK;
1490
1491 /* don't re-probe hardware after each reset */
1492 if (!target_was_examined(target))
1493 retval = cortex_a8_examine_first(target);
1494
1495 /* Configure core debug access */
1496 if (retval == ERROR_OK)
1497 retval = cortex_a8_init_debug_access(target);
1498
1499 return retval;
1500 }
1501
1502 /*
1503 * Cortex-A8 target creation and initialization
1504 */
1505
1506 static int cortex_a8_init_target(struct command_context *cmd_ctx,
1507 struct target *target)
1508 {
1509 /* examine_first() does a bunch of this */
1510 return ERROR_OK;
1511 }
1512
1513 static int cortex_a8_init_arch_info(struct target *target,
1514 struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
1515 {
1516 struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
1517 struct arm *armv4_5 = &armv7a->armv4_5_common;
1518 struct swjdp_common *swjdp = &armv7a->swjdp_info;
1519
1520 /* Setup struct cortex_a8_common */
1521 cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
1522 armv4_5->arch_info = armv7a;
1523
1524 /* prepare JTAG information for the new target */
1525 cortex_a8->jtag_info.tap = tap;
1526 cortex_a8->jtag_info.scann_size = 4;
1527
1528 swjdp->dp_select_value = -1;
1529 swjdp->ap_csw_value = -1;
1530 swjdp->ap_tar_value = -1;
1531 swjdp->jtag_info = &cortex_a8->jtag_info;
1532 swjdp->memaccess_tck = 80;
1533
1534 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
1535 swjdp->tar_autoincr_block = (1 << 10);
1536
1537 cortex_a8->fast_reg_read = 0;
1538
1539 /* register arch-specific functions */
1540 armv7a->examine_debug_reason = NULL;
1541
1542 armv7a->post_debug_entry = cortex_a8_post_debug_entry;
1543
1544 armv7a->pre_restore_context = NULL;
1545 armv7a->post_restore_context = NULL;
1546 armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
1547 // armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
1548 armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
1549 armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
1550 // armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
1551 // armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
1552 armv7a->armv4_5_mmu.has_tiny_pages = 1;
1553 armv7a->armv4_5_mmu.mmu_enabled = 0;
1554
1555
1556 // arm7_9->handle_target_request = cortex_a8_handle_target_request;
1557
1558 /* REVISIT v7a setup should be in a v7a-specific routine */
1559 armv4_5_init_arch_info(target, armv4_5);
1560 armv7a->common_magic = ARMV7_COMMON_MAGIC;
1561
1562 target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
1563
1564 return ERROR_OK;
1565 }
1566
1567 static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
1568 {
1569 struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
1570
1571 cortex_a8_init_arch_info(target, cortex_a8, target->tap);
1572
1573 return ERROR_OK;
1574 }
1575
1576 COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
1577 {
1578 struct target *target = get_current_target(CMD_CTX);
1579 struct armv7a_common *armv7a = target_to_armv7a(target);
1580
1581 return armv4_5_handle_cache_info_command(CMD_CTX,
1582 &armv7a->armv4_5_mmu.armv4_5_cache);
1583 }
1584
1585
1586 COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
1587 {
1588 struct target *target = get_current_target(CMD_CTX);
1589
1590 cortex_a8_init_debug_access(target);
1591
1592 return ERROR_OK;
1593 }
1594
1595 static const struct command_registration cortex_a8_exec_command_handlers[] = {
1596 {
1597 .name = "cache_info",
1598 .handler = &cortex_a8_handle_cache_info_command,
1599 .mode = COMMAND_EXEC,
1600 .help = "display information about target caches",
1601 },
1602 {
1603 .name = "dbginit",
1604 .handler = &cortex_a8_handle_dbginit_command,
1605 .mode = COMMAND_EXEC,
1606 .help = "Initialize core debug",
1607 },
1608 COMMAND_REGISTRATION_DONE
1609 };
1610 static const struct command_registration cortex_a8_command_handlers[] = {
1611 {
1612 .chain = arm_command_handlers,
1613 },
1614 {
1615 .chain = armv7a_command_handlers,
1616 },
1617 {
1618 .name = "cortex_a8",
1619 .mode = COMMAND_ANY,
1620 .help = "Cortex-A8 command group",
1621 .chain = cortex_a8_exec_command_handlers,
1622 },
1623 COMMAND_REGISTRATION_DONE
1624 };
1625
1626 struct target_type cortexa8_target = {
1627 .name = "cortex_a8",
1628
1629 .poll = cortex_a8_poll,
1630 .arch_state = armv7a_arch_state,
1631
1632 .target_request_data = NULL,
1633
1634 .halt = cortex_a8_halt,
1635 .resume = cortex_a8_resume,
1636 .step = cortex_a8_step,
1637
1638 .assert_reset = cortex_a8_assert_reset,
1639 .deassert_reset = cortex_a8_deassert_reset,
1640 .soft_reset_halt = NULL,
1641
1642 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1643
1644 .read_memory = cortex_a8_read_memory,
1645 .write_memory = cortex_a8_write_memory,
1646 .bulk_write_memory = cortex_a8_bulk_write_memory,
1647
1648 .checksum_memory = arm_checksum_memory,
1649 .blank_check_memory = arm_blank_check_memory,
1650
1651 .run_algorithm = armv4_5_run_algorithm,
1652
1653 .add_breakpoint = cortex_a8_add_breakpoint,
1654 .remove_breakpoint = cortex_a8_remove_breakpoint,
1655 .add_watchpoint = NULL,
1656 .remove_watchpoint = NULL,
1657
1658 .commands = cortex_a8_command_handlers,
1659 .target_create = cortex_a8_target_create,
1660 .init_target = cortex_a8_init_target,
1661 .examine = cortex_a8_examine,
1662 };
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