1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2010 by Drasko DRASKOVIC *
9 * drasko.draskovic@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include "target_type.h"
31 #include "arm_opcodes.h"
33 #include "breakpoints.h"
36 #define _DEBUG_INSTRUCTION_EXECUTION_
39 #define NB_CACHE_WAYS 4
42 #define CP15_CTL_DCACHE (1<<2)
43 #define CP15_CTL_ICACHE (1<<12)
46 * flag to give info about cache manipulation during debug :
47 * "0" - cache lines are invalidated "on the fly", for affected addresses.
48 * This is prefered from performance point of view.
49 * "1" - cache is invalidated and switched off on debug_entry, and switched back on on restore.
50 * It is kept off during debugging.
52 static uint8_t arm946e_preserve_cache
;
54 int arm946e_post_debug_entry(struct target
*target
);
55 void arm946e_pre_restore_context(struct target
*target
);
56 static int arm946e_read_cp15(struct target
*target
, int reg_addr
, uint32_t *value
);
58 int arm946e_init_arch_info(struct target
*target
,
59 struct arm946e_common
*arm946e
,
62 struct arm7_9_common
*arm7_9
= &arm946e
->arm7_9_common
;
64 /* initialize arm7/arm9 specific info (including armv4_5) */
65 arm9tdmi_init_arch_info(target
, arm7_9
, tap
);
67 arm946e
->common_magic
= ARM946E_COMMON_MAGIC
;
70 * The ARM946E-S implements the ARMv5TE architecture which
71 * has the BKPT instruction, so we don't have to use a watchpoint comparator
73 arm7_9
->arm_bkpt
= ARMV5_BKPT(0x0);
74 arm7_9
->thumb_bkpt
= ARMV5_T_BKPT(0x0) & 0xffff;
77 arm7_9
->post_debug_entry
= arm946e_post_debug_entry
;
78 arm7_9
->pre_restore_context
= arm946e_pre_restore_context
;
81 * disabling linefills leads to lockups, so keep them enabled for now
82 * this doesn't affect correctness, but might affect timing issues, if
83 * important data is evicted from the cache during the debug session
85 arm946e_preserve_cache
= 0;
87 /* override hw single-step capability from ARM9TDMI */
88 /* arm7_9->has_single_step = 1; */
93 static int arm946e_target_create(struct target
*target
, Jim_Interp
*interp
)
95 struct arm946e_common
*arm946e
= calloc(1, sizeof(struct arm946e_common
));
97 arm946e_init_arch_info(target
, arm946e
, target
->tap
);
102 static void arm946e_deinit_target(struct target
*target
)
104 struct arm
*arm
= target_to_arm(target
);
105 struct arm946e_common
*arm946e
= target_to_arm946(target
);
107 arm7_9_deinit(target
);
108 arm_free_reg_cache(arm
);
112 static int arm946e_verify_pointer(struct command_invocation
*cmd
,
113 struct arm946e_common
*arm946e
)
115 if (arm946e
->common_magic
!= ARM946E_COMMON_MAGIC
) {
116 command_print(cmd
, "target is not an ARM946");
117 return ERROR_TARGET_INVALID
;
123 * Update cp15_control_reg, saved on debug_entry.
125 static void arm946e_update_cp15_caches(struct target
*target
, uint32_t value
)
127 struct arm946e_common
*arm946e
= target_to_arm946(target
);
128 arm946e
->cp15_control_reg
= (arm946e
->cp15_control_reg
& ~(CP15_CTL_DCACHE
|CP15_CTL_ICACHE
))
129 | (value
& (CP15_CTL_DCACHE
|CP15_CTL_ICACHE
));
133 * REVISIT: The "read_cp15" and "write_cp15" commands could hook up
134 * to eventual mrc() and mcr() routines ... the reg_addr values being
135 * constructed (for CP15 only) from Opcode_1, Opcode_2, and CRn values.
136 * See section 7.3 of the ARM946E-S TRM.
138 static int arm946e_read_cp15(struct target
*target
, int reg_addr
, uint32_t *value
)
140 int retval
= ERROR_OK
;
141 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
142 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
143 struct scan_field fields
[3];
144 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
145 uint8_t nr_w_buf
= 0;
147 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
148 if (retval
!= ERROR_OK
)
150 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
151 if (retval
!= ERROR_OK
)
154 fields
[0].num_bits
= 32;
155 /* REVISIT: table 7-2 shows that bits 31-31 need to be
156 * specified for accessing BIST registers ...
158 fields
[0].out_value
= NULL
;
159 fields
[0].in_value
= NULL
;
161 fields
[1].num_bits
= 6;
162 fields
[1].out_value
= ®_addr_buf
;
163 fields
[1].in_value
= NULL
;
165 fields
[2].num_bits
= 1;
166 fields
[2].out_value
= &nr_w_buf
;
167 fields
[2].in_value
= NULL
;
169 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
171 fields
[0].in_value
= (uint8_t *)value
;
172 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
174 jtag_add_callback(arm_le_to_h_u32
, (jtag_callback_data_t
)value
);
176 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
177 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, *value
);
180 retval
= jtag_execute_queue();
181 if (retval
!= ERROR_OK
)
187 int arm946e_write_cp15(struct target
*target
, int reg_addr
, uint32_t value
)
189 int retval
= ERROR_OK
;
190 struct arm7_9_common
*arm7_9
= target_to_arm7_9(target
);
191 struct arm_jtag
*jtag_info
= &arm7_9
->jtag_info
;
192 struct scan_field fields
[3];
193 uint8_t reg_addr_buf
= reg_addr
& 0x3f;
194 uint8_t nr_w_buf
= 1;
195 uint8_t value_buf
[4];
197 buf_set_u32(value_buf
, 0, 32, value
);
199 retval
= arm_jtag_scann(jtag_info
, 0xf, TAP_IDLE
);
200 if (retval
!= ERROR_OK
)
202 retval
= arm_jtag_set_instr(jtag_info
->tap
, jtag_info
->intest_instr
, NULL
, TAP_IDLE
);
203 if (retval
!= ERROR_OK
)
206 fields
[0].num_bits
= 32;
207 fields
[0].out_value
= value_buf
;
208 fields
[0].in_value
= NULL
;
210 fields
[1].num_bits
= 6;
211 fields
[1].out_value
= ®_addr_buf
;
212 fields
[1].in_value
= NULL
;
214 fields
[2].num_bits
= 1;
215 fields
[2].out_value
= &nr_w_buf
;
216 fields
[2].in_value
= NULL
;
218 jtag_add_dr_scan(jtag_info
->tap
, 3, fields
, TAP_IDLE
);
220 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
221 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr
, value
);
224 retval
= jtag_execute_queue();
225 if (retval
!= ERROR_OK
)
231 #define GET_ICACHE_SIZE 6
232 #define GET_DCACHE_SIZE 18
235 * \param target struct target pointer
236 * \param idsel select GET_ICACHE_SIZE or GET_DCACHE_SIZE
237 * \returns cache size, given in bytes
239 static uint32_t arm946e_cp15_get_csize(struct target
*target
, int idsel
)
241 struct arm946e_common
*arm946e
= target_to_arm946(target
);
242 uint32_t csize
= arm946e
->cp15_cache_info
;
244 if (arm946e_read_cp15(target
, 0x01, &csize
) == ERROR_OK
)
245 arm946e
->cp15_cache_info
= csize
;
247 if (csize
& (1<<(idsel
-4))) /* cache absent */
249 csize
= (csize
>> idsel
) & 0x0F;
250 return csize
? 1 << (12 + (csize
-3)) : 0;
253 uint32_t arm946e_invalidate_whole_dcache(struct target
*target
)
255 uint32_t csize
= arm946e_cp15_get_csize(target
, GET_DCACHE_SIZE
);
257 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
259 /* One line (index) is 32 bytes (8 words) long, 4-way assoc
260 * ARM DDI 0201D, Section 3.3.5
262 int nb_idx
= (csize
/ (4*8*NB_CACHE_WAYS
)); /* gives nb of lines (indexes) in the cache */
264 /* Loop for all segmentde (i.e. ways) */
266 for (seg
= 0; seg
< NB_CACHE_WAYS
; seg
++) {
267 /* Loop for all indexes */
269 for (idx
= 0; idx
< nb_idx
; idx
++) {
270 /* Form and write cp15 index (segment + line idx) */
271 uint32_t cp15_idx
= seg
<< 30 | idx
<< 5;
272 int retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
273 if (retval
!= ERROR_OK
) {
274 LOG_DEBUG("ERROR writing index");
280 retval
= arm946e_read_cp15(target
, 0x16, &dtag
);
281 if (retval
!= ERROR_OK
) {
282 LOG_DEBUG("ERROR reading dtag");
286 /* Check cache line VALID bit */
287 if (!(dtag
>> 4 & 0x1))
290 /* Clean data cache line */
291 retval
= arm946e_write_cp15(target
, 0x35, 0x1);
292 if (retval
!= ERROR_OK
) {
293 LOG_DEBUG("ERROR cleaning cache line");
297 /* Flush data cache line */
298 retval
= arm946e_write_cp15(target
, 0x1a, 0x1);
299 if (retval
!= ERROR_OK
) {
300 LOG_DEBUG("ERROR flushing cache line");
309 uint32_t arm946e_invalidate_whole_icache(struct target
*target
)
311 /* Check cache presence before flushing - avoid undefined behavior */
312 uint32_t csize
= arm946e_cp15_get_csize(target
, GET_ICACHE_SIZE
);
314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
316 LOG_DEBUG("FLUSHING I$");
318 * Invalidate (flush) I$
319 * mcr 15, 0, r0, cr7, cr5, {0}
321 int retval
= arm946e_write_cp15(target
, 0x0f, 0x1);
322 if (retval
!= ERROR_OK
) {
323 LOG_DEBUG("ERROR flushing I$");
330 int arm946e_post_debug_entry(struct target
*target
)
332 uint32_t ctr_reg
= 0x0;
333 uint32_t retval
= ERROR_OK
;
334 struct arm946e_common
*arm946e
= target_to_arm946(target
);
336 /* See if CACHES are enabled, and save that info
337 * in the context bits, so that arm946e_pre_restore_context() can use them */
338 arm946e_read_cp15(target
, CP15_CTL
, &ctr_reg
);
340 /* Save control reg in the context */
341 arm946e
->cp15_control_reg
= ctr_reg
;
343 if (arm946e_preserve_cache
) {
344 if (ctr_reg
& CP15_CTL_DCACHE
) {
345 /* Clean and flush D$ */
346 arm946e_invalidate_whole_dcache(target
);
349 ctr_reg
&= ~CP15_CTL_DCACHE
;
352 if (ctr_reg
& CP15_CTL_ICACHE
) {
354 arm946e_invalidate_whole_icache(target
);
357 ctr_reg
&= ~CP15_CTL_ICACHE
;
360 /* Write the new configuration */
361 retval
= arm946e_write_cp15(target
, CP15_CTL
, ctr_reg
);
362 if (retval
!= ERROR_OK
) {
363 LOG_DEBUG("ERROR disabling cache");
366 } /* if preserve_cache */
371 void arm946e_pre_restore_context(struct target
*target
)
373 uint32_t ctr_reg
= 0x0;
376 if (arm946e_preserve_cache
) {
377 struct arm946e_common
*arm946e
= target_to_arm946(target
);
378 /* Get the contents of the CTR reg */
379 arm946e_read_cp15(target
, CP15_CTL
, &ctr_reg
);
382 * Read-modify-write CP15 control
383 * to reenable I/D-cache operation
384 * NOTE: It is not possible to disable cache by CP15.
385 * if arm946e_preserve_cache debugging flag enabled.
387 ctr_reg
|= arm946e
->cp15_control_reg
& (CP15_CTL_DCACHE
|CP15_CTL_ICACHE
);
389 /* Write the new configuration */
390 retval
= arm946e_write_cp15(target
, CP15_CTL
, ctr_reg
);
391 if (retval
!= ERROR_OK
)
392 LOG_DEBUG("ERROR enabling cache");
393 } /* if preserve_cache */
396 uint32_t arm946e_invalidate_dcache(struct target
*target
, uint32_t address
,
397 uint32_t size
, uint32_t count
)
399 uint32_t cur_addr
= 0x0;
400 uint32_t cp15_idx
, set
, way
, dtag
;
404 for (i
= 0; i
< count
*size
; i
++) {
405 cur_addr
= address
+ i
;
408 set
= (cur_addr
>> 5) & 0xff; /* set field is 8 bits long */
410 for (way
= 0; way
< NB_CACHE_WAYS
; way
++) {
412 * Find if the affected address is kept in the cache.
413 * Because JTAG Scan Chain 15 offers limited approach,
414 * we have to loop through all cache ways (segments) and
415 * read cache tags, then compare them with with address.
418 /* Form and write cp15 index (segment + line idx) */
419 cp15_idx
= way
<< 30 | set
<< 5;
420 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
421 if (retval
!= ERROR_OK
) {
422 LOG_DEBUG("ERROR writing index");
427 retval
= arm946e_read_cp15(target
, 0x16, &dtag
);
428 if (retval
!= ERROR_OK
) {
429 LOG_DEBUG("ERROR reading dtag");
433 /* Check cache line VALID bit */
434 if (!(dtag
>> 4 & 0x1))
437 /* If line is valid and corresponds to affected address - invalidate it */
438 if (dtag
>> 5 == cur_addr
>> 5) {
439 /* Clean data cache line */
440 retval
= arm946e_write_cp15(target
, 0x35, 0x1);
441 if (retval
!= ERROR_OK
) {
442 LOG_DEBUG("ERROR cleaning cache line");
446 /* Flush data cache line */
447 retval
= arm946e_write_cp15(target
, 0x1c, 0x1);
448 if (retval
!= ERROR_OK
) {
449 LOG_DEBUG("ERROR flushing cache line");
455 } /* loop through all 4 ways */
456 } /* loop through all addresses */
461 uint32_t arm946e_invalidate_icache(struct target
*target
, uint32_t address
,
462 uint32_t size
, uint32_t count
)
464 uint32_t cur_addr
= 0x0;
465 uint32_t cp15_idx
, set
, way
, itag
;
469 for (i
= 0; i
< count
*size
; i
++) {
470 cur_addr
= address
+ i
;
472 set
= (cur_addr
>> 5) & 0xff; /* set field is 8 bits long */
474 for (way
= 0; way
< NB_CACHE_WAYS
; way
++) {
475 /* Form and write cp15 index (segment + line idx) */
476 cp15_idx
= way
<< 30 | set
<< 5;
477 retval
= arm946e_write_cp15(target
, 0x3a, cp15_idx
);
478 if (retval
!= ERROR_OK
) {
479 LOG_DEBUG("ERROR writing index");
484 retval
= arm946e_read_cp15(target
, 0x17, &itag
);
485 if (retval
!= ERROR_OK
) {
486 LOG_DEBUG("ERROR reading itag");
490 /* Check cache line VALID bit */
491 if (!(itag
>> 4 & 0x1))
494 /* If line is valid and corresponds to affected address - invalidate it */
495 if (itag
>> 5 == cur_addr
>> 5) {
497 retval
= arm946e_write_cp15(target
, 0x1d, 0x0);
498 if (retval
!= ERROR_OK
) {
499 LOG_DEBUG("ERROR flushing cache line");
511 /** Writes a buffer, in the specified word size, with current MMU settings. */
512 int arm946e_write_memory(struct target
*target
, target_addr_t address
,
513 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
519 struct arm946e_common
*arm946e
= target_to_arm946(target
);
520 /* Invalidate D$ if it is ON */
521 if (!arm946e_preserve_cache
&& (arm946e
->cp15_control_reg
& CP15_CTL_DCACHE
))
522 arm946e_invalidate_dcache(target
, address
, size
, count
);
527 retval
= arm7_9_write_memory_opt(target
, address
, size
, count
, buffer
);
528 if (retval
!= ERROR_OK
)
532 * Invalidate I$ if it is ON.
534 * D$ has been cleaned and flushed before mem write thus forcing it to behave like write-through,
535 * because arm7_9_write_memory() has seen non-valid bit in D$
536 * and wrote data into physical RAM (without touching or allocating the cache line).
537 * From ARM946ES Technical Reference Manual we can see that it uses "allocate on read-miss"
538 * policy for both I$ and D$ (Chapter 3.2 and 3.3)
541 * "ARM system developer's guide: designing and optimizing system software" by
542 * Andrew N. Sloss, Dominic Symes and Chris Wright,
543 * Chapter 12.3.3 Allocating Policy on a Cache Miss :
544 * A read allocate on cache miss policy allocates a cache line only during a read from main memory.
545 * If the victim cache line contains valid data, then it is written to main memory before the cache line
546 * is filled with new data.
547 * Under this strategy, a write of new data to memory does not update the contents of the cache memory
548 * unless a cache line was allocated on a previous read from main memory.
549 * If the cache line contains valid data, then the write updates the cache and may update the main memory if
550 * the cache write policy is write-through.
551 * If the data is not in the cache, the controller writes to main memory only.
553 if (!arm946e_preserve_cache
&& (arm946e
->cp15_control_reg
& CP15_CTL_ICACHE
))
554 arm946e_invalidate_icache(target
, address
, size
, count
);
560 int arm946e_read_memory(struct target
*target
, target_addr_t address
,
561 uint32_t size
, uint32_t count
, uint8_t *buffer
)
567 retval
= arm7_9_read_memory(target
, address
, size
, count
, buffer
);
568 if (retval
!= ERROR_OK
)
574 COMMAND_HANDLER(arm946e_handle_cp15
)
576 /* one or two arguments, access a single register (write if second argument is given) */
577 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
578 return ERROR_COMMAND_SYNTAX_ERROR
;
580 struct target
*target
= get_current_target(CMD_CTX
);
582 struct arm946e_common
*arm946e
= target_to_arm946(target
);
583 int retval
= arm946e_verify_pointer(CMD
, arm946e
);
584 if (retval
!= ERROR_OK
)
587 if (target
->state
!= TARGET_HALTED
) {
588 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
589 return ERROR_TARGET_NOT_HALTED
;
593 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], address
);
597 retval
= arm946e_read_cp15(target
, address
, &value
);
598 if (retval
!= ERROR_OK
) {
599 command_print(CMD
, "%s cp15 reg %" PRIi32
" access failed", target_name(target
), address
);
602 retval
= jtag_execute_queue();
603 if (retval
!= ERROR_OK
)
606 /* Return value in hex format */
607 command_print(CMD
, "0x%08" PRIx32
, value
);
608 } else if (CMD_ARGC
== 2) {
610 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], value
);
612 retval
= arm946e_write_cp15(target
, address
, value
);
613 if (retval
!= ERROR_OK
) {
614 command_print(CMD
, "%s cp15 reg %" PRIi32
" access failed", target_name(target
), address
);
617 if (address
== CP15_CTL
)
618 arm946e_update_cp15_caches(target
, value
);
624 COMMAND_HANDLER(arm946e_handle_idcache
)
627 return ERROR_COMMAND_SYNTAX_ERROR
;
630 struct target
*target
= get_current_target(CMD_CTX
);
631 struct arm946e_common
*arm946e
= target_to_arm946(target
);
633 retval
= arm946e_verify_pointer(CMD
, arm946e
);
634 if (retval
!= ERROR_OK
)
637 if (target
->state
!= TARGET_HALTED
) {
638 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
639 return ERROR_TARGET_NOT_HALTED
;
642 bool icache
= (strcmp(CMD_NAME
, "icache") == 0);
643 uint32_t csize
= arm946e_cp15_get_csize(target
, icache
? GET_ICACHE_SIZE
: GET_DCACHE_SIZE
) / 1024;
645 bool bena
= ((arm946e
->cp15_control_reg
& (icache
? CP15_CTL_ICACHE
: CP15_CTL_DCACHE
)) != 0)
646 && (arm946e
->cp15_control_reg
& 0x1);
648 command_print(CMD
, "%s-cache absent", icache
? "I" : "D");
650 command_print(CMD
, "%s-cache size: %" PRIu32
"K, %s",
651 icache
? "I" : "D", csize
, bena
? "enabled" : "disabled");
657 retval
= command_parse_bool_arg(CMD_ARGV
[0], &enable
);
658 if (retval
== ERROR_COMMAND_SYNTAX_ERROR
) {
659 if (strcmp(CMD_ARGV
[0], "flush") == 0) {
666 /* Do not invalidate or change state, if cache is absent */
668 command_print(CMD
, "%s-cache absent, '%s' operation undefined", icache
? "I" : "D", CMD_ARGV
[0]);
669 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
672 /* NOTE: flushing entire cache will not preserve lock-down cache regions */
674 if ((arm946e
->cp15_control_reg
& CP15_CTL_ICACHE
) && !enable
)
675 retval
= arm946e_invalidate_whole_icache(target
);
677 if ((arm946e
->cp15_control_reg
& CP15_CTL_DCACHE
) && !enable
)
678 retval
= arm946e_invalidate_whole_dcache(target
);
681 if (retval
!= ERROR_OK
|| flush
)
685 retval
= arm946e_read_cp15(target
, CP15_CTL
, &value
);
686 if (retval
!= ERROR_OK
)
689 uint32_t vnew
= value
;
690 uint32_t cmask
= icache
? CP15_CTL_ICACHE
: CP15_CTL_DCACHE
;
692 if ((value
& 0x1) == 0)
693 LOG_WARNING("arm946e: MPU must be enabled for cache to operate");
701 retval
= arm946e_write_cp15(target
, CP15_CTL
, vnew
);
702 if (retval
!= ERROR_OK
)
705 arm946e_update_cp15_caches(target
, vnew
);
709 static const struct command_registration arm946e_exec_command_handlers
[] = {
712 .handler
= arm946e_handle_cp15
,
713 .mode
= COMMAND_EXEC
,
714 .usage
= "regnum [value]",
715 .help
= "read/modify cp15 register",
719 .handler
= arm946e_handle_idcache
,
720 .mode
= COMMAND_EXEC
,
721 .usage
= "['enable'|'disable'|'flush']",
722 .help
= "I-cache info and operations",
726 .handler
= arm946e_handle_idcache
,
727 .mode
= COMMAND_EXEC
,
728 .usage
= "['enable'|'disable'|'flush']",
729 .help
= "D-cache info and operations",
731 COMMAND_REGISTRATION_DONE
734 const struct command_registration arm946e_command_handlers
[] = {
736 .chain
= arm9tdmi_command_handlers
,
741 .help
= "arm946e command group",
743 .chain
= arm946e_exec_command_handlers
,
745 COMMAND_REGISTRATION_DONE
748 /** Holds methods for ARM946 targets. */
749 struct target_type arm946e_target
= {
753 .arch_state
= arm_arch_state
,
755 .target_request_data
= arm7_9_target_request_data
,
758 .resume
= arm7_9_resume
,
761 .assert_reset
= arm7_9_assert_reset
,
762 .deassert_reset
= arm7_9_deassert_reset
,
763 .soft_reset_halt
= arm7_9_soft_reset_halt
,
765 .get_gdb_arch
= arm_get_gdb_arch
,
766 .get_gdb_reg_list
= arm_get_gdb_reg_list
,
768 /* .read_memory = arm7_9_read_memory, */
769 /* .write_memory = arm7_9_write_memory, */
770 .read_memory
= arm946e_read_memory
,
771 .write_memory
= arm946e_write_memory
,
773 .checksum_memory
= arm_checksum_memory
,
774 .blank_check_memory
= arm_blank_check_memory
,
776 .run_algorithm
= armv4_5_run_algorithm
,
778 .add_breakpoint
= arm7_9_add_breakpoint
,
779 .remove_breakpoint
= arm7_9_remove_breakpoint
,
780 /* .add_breakpoint = arm946e_add_breakpoint, */
781 /* .remove_breakpoint = arm946e_remove_breakpoint, */
783 .add_watchpoint
= arm7_9_add_watchpoint
,
784 .remove_watchpoint
= arm7_9_remove_watchpoint
,
786 .commands
= arm946e_command_handlers
,
787 .target_create
= arm946e_target_create
,
788 .init_target
= arm9tdmi_init_target
,
789 .deinit_target
= arm946e_deinit_target
,
790 .examine
= arm7_9_examine
,
791 .check_reset
= arm7_9_check_reset
,