src/target/arm.h

   1 /*
   2  * Copyright (C) 2005 by Dominic Rath
   3  * Dominic.Rath@gmx.de
   4  *
   5  * Copyright (C) 2008 by Spencer Oliver
   6  * spen@spen-soft.co.uk
   7  *
   8  * Copyright (C) 2009 by Øyvind Harboe
   9  * oyvind.harboe@zylin.com
  10  *
  11  * Copyright (C) 2018 by Liviu Ionescu
  12  *   <ilg@livius.net>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #ifndef OPENOCD_TARGET_ARM_H
  29 #define OPENOCD_TARGET_ARM_H
  30
  31 #include <helper/command.h>
  32 #include "target.h"
  33
  34 /**
  35  * @file
  36  * Holds the interface to ARM cores.
  37  *
  38  * At this writing, only "classic ARM" cores built on the ARMv4 register
  39  * and mode model are supported.  The Thumb2-only microcontroller profile
  40  * support has not yet been integrated, affecting Cortex-M parts.
  41  */
  42
  43 /**
  44  * Indicates what registers are in the ARM state core register set.
  45  *
  46  * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
  47  *   on for example ARM7TDMI cores.
  48  * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
  49  *   three more registers are shadowed for "Secure Monitor" mode.
  50  * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
  51  *   and also security extensions. Additional shadowed registers for
  52  *   "Secure Monitor" and "Hypervisor" modes.
  53  * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
  54  *   which only shadows SP.
  55  */
  56 enum arm_core_type {
  57         ARM_CORE_TYPE_STD = -1,
  58         ARM_CORE_TYPE_SEC_EXT = 1,
  59         ARM_CORE_TYPE_VIRT_EXT,
  60         ARM_CORE_TYPE_M_PROFILE,
  61 };
  62
  63 /** ARM Architecture specifying the version and the profile */
  64 enum arm_arch {
  65         ARM_ARCH_UNKNOWN,
  66         ARM_ARCH_V4,
  67         ARM_ARCH_V6M,
  68         ARM_ARCH_V7M,
  69         ARM_ARCH_V8M,
  70 };
  71
  72 /**
  73  * Represent state of an ARM core.
  74  *
  75  * Most numbers match the five low bits of the *PSR registers on
  76  * "classic ARM" processors, which build on the ARMv4 processor
  77  * modes and register set.
  78  *
  79  * ARM_MODE_ANY is a magic value, often used as a wildcard.
  80  *
  81  * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
  82  * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER.  Those are the only modes
  83  * they support.
  84  */
  85 enum arm_mode {
  86         ARM_MODE_USR = 16,
  87         ARM_MODE_FIQ = 17,
  88         ARM_MODE_IRQ = 18,
  89         ARM_MODE_SVC = 19,
  90         ARM_MODE_MON = 22,
  91         ARM_MODE_ABT = 23,
  92         ARM_MODE_HYP = 26,
  93         ARM_MODE_UND = 27,
  94         ARM_MODE_1176_MON = 28,
  95         ARM_MODE_SYS = 31,
  96
  97         ARM_MODE_THREAD = 0,
  98         ARM_MODE_USER_THREAD = 1,
  99         ARM_MODE_HANDLER = 2,
 100
 101         ARMV8_64_EL0T = 0x0,
 102         ARMV8_64_EL1T = 0x4,
 103         ARMV8_64_EL1H = 0x5,
 104         ARMV8_64_EL2T = 0x8,
 105         ARMV8_64_EL2H = 0x9,
 106         ARMV8_64_EL3T = 0xC,
 107         ARMV8_64_EL3H = 0xD,
 108
 109         ARM_MODE_ANY = -1
 110 };
 111
 112 /* VFPv3 internal register numbers mapping to d0:31 */
 113 enum {
 114         ARM_VFP_V3_D0 = 51,
 115         ARM_VFP_V3_D1,
 116         ARM_VFP_V3_D2,
 117         ARM_VFP_V3_D3,
 118         ARM_VFP_V3_D4,
 119         ARM_VFP_V3_D5,
 120         ARM_VFP_V3_D6,
 121         ARM_VFP_V3_D7,
 122         ARM_VFP_V3_D8,
 123         ARM_VFP_V3_D9,
 124         ARM_VFP_V3_D10,
 125         ARM_VFP_V3_D11,
 126         ARM_VFP_V3_D12,
 127         ARM_VFP_V3_D13,
 128         ARM_VFP_V3_D14,
 129         ARM_VFP_V3_D15,
 130         ARM_VFP_V3_D16,
 131         ARM_VFP_V3_D17,
 132         ARM_VFP_V3_D18,
 133         ARM_VFP_V3_D19,
 134         ARM_VFP_V3_D20,
 135         ARM_VFP_V3_D21,
 136         ARM_VFP_V3_D22,
 137         ARM_VFP_V3_D23,
 138         ARM_VFP_V3_D24,
 139         ARM_VFP_V3_D25,
 140         ARM_VFP_V3_D26,
 141         ARM_VFP_V3_D27,
 142         ARM_VFP_V3_D28,
 143         ARM_VFP_V3_D29,
 144         ARM_VFP_V3_D30,
 145         ARM_VFP_V3_D31,
 146         ARM_VFP_V3_FPSCR,
 147 };
 148
 149 const char *arm_mode_name(unsigned psr_mode);
 150 bool is_arm_mode(unsigned psr_mode);
 151
 152 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
 153 enum arm_state {
 154         ARM_STATE_ARM,
 155         ARM_STATE_THUMB,
 156         ARM_STATE_JAZELLE,
 157         ARM_STATE_THUMB_EE,
 158         ARM_STATE_AARCH64,
 159 };
 160
 161 /** ARM vector floating point enabled, if yes which version. */
 162 enum arm_vfp_version {
 163         ARM_VFP_DISABLED,
 164         ARM_VFP_V1,
 165         ARM_VFP_V2,
 166         ARM_VFP_V3,
 167 };
 168
 169 #define ARM_COMMON_MAGIC 0x0A450A45
 170
 171 /**
 172  * Represents a generic ARM core, with standard application registers.
 173  *
 174  * There are sixteen application registers (including PC, SP, LR) and a PSR.
 175  * Cortex-M series cores do not support as many core states or shadowed
 176  * registers as traditional ARM cores, and only support Thumb2 instructions.
 177  */
 178 struct arm {
 179         int common_magic;
 180         struct reg_cache *core_cache;
 181
 182         /** Handle to the PC; valid in all core modes. */
 183         struct reg *pc;
 184
 185         /** Handle to the CPSR/xPSR; valid in all core modes. */
 186         struct reg *cpsr;
 187
 188         /** Handle to the SPSR; valid only in core modes with an SPSR. */
 189         struct reg *spsr;
 190
 191         /** Support for arm_reg_current() */
 192         const int *map;
 193
 194         /** Indicates what registers are in the ARM state core register set. */
 195         enum arm_core_type core_type;
 196
 197         /** Record the current core mode: SVC, USR, or some other mode. */
 198         enum arm_mode core_mode;
 199
 200         /** Record the current core state: ARM, Thumb, or otherwise. */
 201         enum arm_state core_state;
 202
 203         /** ARM architecture version */
 204         enum arm_arch arch;
 205
 206         /** Floating point or VFP version, 0 if disabled. */
 207         int arm_vfp_version;
 208
 209         int (*setup_semihosting)(struct target *target, int enable);
 210
 211         /** Backpointer to the target. */
 212         struct target *target;
 213
 214         /** Handle for the debug module, if one is present. */
 215         struct arm_dpm *dpm;
 216
 217         /** Handle for the Embedded Trace Module, if one is present. */
 218         struct etm_context *etm;
 219
 220         /* FIXME all these methods should take "struct arm *" not target */
 221
 222         /** Retrieve all core registers, for display. */
 223         int (*full_context)(struct target *target);
 224
 225         /** Retrieve a single core register. */
 226         int (*read_core_reg)(struct target *target, struct reg *reg,
 227                         int num, enum arm_mode mode);
 228         int (*write_core_reg)(struct target *target, struct reg *reg,
 229                         int num, enum arm_mode mode, uint8_t *value);
 230
 231         /** Read coprocessor register.  */
 232         int (*mrc)(struct target *target, int cpnum,
 233                         uint32_t op1, uint32_t op2,
 234                         uint32_t crn, uint32_t crm,
 235                         uint32_t *value);
 236
 237         /** Write coprocessor register.  */
 238         int (*mcr)(struct target *target, int cpnum,
 239                         uint32_t op1, uint32_t op2,
 240                         uint32_t crn, uint32_t crm,
 241                         uint32_t value);
 242
 243         void *arch_info;
 244
 245         /** For targets conforming to ARM Debug Interface v5,
 246          * this handle references the Debug Access Port (DAP)
 247          * used to make requests to the target.
 248          */
 249         struct adiv5_dap *dap;
 250 };
 251
 252 /** Convert target handle to generic ARM target state handle. */
 253 static inline struct arm *target_to_arm(struct target *target)
 254 {
 255         assert(target);
 256         return target->arch_info;
 257 }
 258
 259 static inline bool is_arm(struct arm *arm)
 260 {
 261         assert(arm);
 262         return arm->common_magic == ARM_COMMON_MAGIC;
 263 }
 264
 265 struct arm_algorithm {
 266         int common_magic;
 267
 268         enum arm_mode core_mode;
 269         enum arm_state core_state;
 270 };
 271
 272 struct arm_reg {
 273         int num;
 274         enum arm_mode mode;
 275         struct target *target;
 276         struct arm *arm;
 277         uint8_t value[16];
 278 };
 279
 280 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 281 void arm_free_reg_cache(struct arm *arm);
 282
 283 struct reg_cache *armv8_build_reg_cache(struct target *target);
 284
 285 extern const struct command_registration arm_command_handlers[];
 286
 287 int arm_arch_state(struct target *target);
 288 const char *arm_get_gdb_arch(struct target *target);
 289 int arm_get_gdb_reg_list(struct target *target,
 290                 struct reg **reg_list[], int *reg_list_size,
 291                 enum target_register_class reg_class);
 292 const char *armv8_get_gdb_arch(struct target *target);
 293 int armv8_get_gdb_reg_list(struct target *target,
 294                 struct reg **reg_list[], int *reg_list_size,
 295                 enum target_register_class reg_class);
 296
 297 int arm_init_arch_info(struct target *target, struct arm *arm);
 298
 299 /* REVISIT rename this once it's usable by ARMv7-M */
 300 int armv4_5_run_algorithm(struct target *target,
 301                 int num_mem_params, struct mem_param *mem_params,
 302                 int num_reg_params, struct reg_param *reg_params,
 303                 target_addr_t entry_point, target_addr_t exit_point,
 304                 int timeout_ms, void *arch_info);
 305 int armv4_5_run_algorithm_inner(struct target *target,
 306                 int num_mem_params, struct mem_param *mem_params,
 307                 int num_reg_params, struct reg_param *reg_params,
 308                 uint32_t entry_point, uint32_t exit_point,
 309                 int timeout_ms, void *arch_info,
 310                 int (*run_it)(struct target *target, uint32_t exit_point,
 311                                 int timeout_ms, void *arch_info));
 312
 313 int arm_checksum_memory(struct target *target,
 314                 target_addr_t address, uint32_t count, uint32_t *checksum);
 315 int arm_blank_check_memory(struct target *target,
 316                 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 317
 318 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 319 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 320 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
 321
 322 extern struct reg arm_gdb_dummy_fp_reg;
 323 extern struct reg arm_gdb_dummy_fps_reg;
 324
 325 #endif /* OPENOCD_TARGET_ARM_H */