ARM: rename armv4_5_state_* as arm_state_*
[openocd.git] / src / target / mips32.h
blob98186aff93cf507e8432ca15d14f31b8b428d5a8
1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
23 #ifndef MIPS32_H
24 #define MIPS32_H
26 #include <target/target.h>
27 #include <target/mips32_pracc.h>
30 #define MIPS32_COMMON_MAGIC 0xB320B320
32 /* offsets into mips32 core register cache */
33 enum
35 MIPS32_PC = 37,
36 MIPS32NUMCOREREGS
39 struct mips32_comparator
41 int used;
42 //int type;
43 uint32_t bp_value;
44 uint32_t reg_address;
47 struct mips32_common
49 uint32_t common_magic;
50 void *arch_info;
51 struct reg_cache *core_cache;
52 struct mips_ejtag ejtag_info;
53 uint32_t core_regs[MIPS32NUMCOREREGS];
55 int bp_scanned;
56 int num_inst_bpoints;
57 int num_data_bpoints;
58 int num_inst_bpoints_avail;
59 int num_data_bpoints_avail;
60 struct mips32_comparator *inst_break_list;
61 struct mips32_comparator *data_break_list;
63 /* register cache to processor synchronization */
64 int (*read_core_reg)(struct target *target, int num);
65 int (*write_core_reg)(struct target *target, int num);
68 struct mips32_core_reg
70 uint32_t num;
71 struct target *target;
72 struct mips32_common *mips32_common;
75 #define MIPS32_OP_BEQ 0x04
76 #define MIPS32_OP_BNE 0x05
77 #define MIPS32_OP_ADDI 0x08
78 #define MIPS32_OP_AND 0x24
79 #define MIPS32_OP_COP0 0x10
80 #define MIPS32_OP_LUI 0x0F
81 #define MIPS32_OP_LW 0x23
82 #define MIPS32_OP_LBU 0x24
83 #define MIPS32_OP_LHU 0x25
84 #define MIPS32_OP_MFHI 0x10
85 #define MIPS32_OP_MTHI 0x11
86 #define MIPS32_OP_MFLO 0x12
87 #define MIPS32_OP_MTLO 0x13
88 #define MIPS32_OP_SB 0x28
89 #define MIPS32_OP_SH 0x29
90 #define MIPS32_OP_SW 0x2B
91 #define MIPS32_OP_ORI 0x0D
93 #define MIPS32_COP0_MF 0x00
94 #define MIPS32_COP0_MT 0x04
96 #define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
97 #define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
98 #define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
100 #define MIPS32_NOP 0
101 #define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
102 #define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
103 #define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
104 #define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
105 #define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
106 #define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
107 #define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
108 #define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
109 #define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
110 #define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
111 #define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
112 #define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
113 #define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
114 #define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
115 #define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
116 #define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
117 #define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
118 #define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
119 #define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
121 /* ejtag specific instructions */
122 #define MIPS32_DRET 0x4200001F
123 #define MIPS32_SDBBP 0x7000003F
124 #define MIPS16_SDBBP 0xE801
126 int mips32_arch_state(struct target *target);
128 int mips32_init_arch_info(struct target *target,
129 struct mips32_common *mips32, struct jtag_tap *tap);
131 int mips32_restore_context(struct target *target);
132 int mips32_save_context(struct target *target);
134 struct reg_cache *mips32_build_reg_cache(struct target *target);
136 int mips32_run_algorithm(struct target *target,
137 int num_mem_params, struct mem_param *mem_params,
138 int num_reg_params, struct reg_param *reg_params,
139 uint32_t entry_point, uint32_t exit_point,
140 int timeout_ms, void *arch_info);
142 int mips32_configure_break_unit(struct target *target);
144 int mips32_enable_interrupts(struct target *target, int enable);
146 int mips32_examine(struct target *target);
148 int mips32_register_commands(struct command_context *cmd_ctx);
150 int mips32_get_gdb_reg_list(struct target *target,
151 struct reg **reg_list[], int *reg_list_size);
153 #endif /*MIPS32_H*/