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ARM: rename armv4_5_state_* as arm_state_*
[openocd.git] / src / target / arm11.c
blob0486b04c914a0010069b26764569072fa3cd577d
1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
3 * Michael Bruck *
4 * *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
6 * *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "etm.h"
30 #include "breakpoints.h"
31 #include "arm11_dbgtap.h"
32 #include "arm_simulator.h"
33 #include <helper/time_support.h>
34 #include "target_type.h"
35 #include "algorithm.h"
36 #include "register.h"
37
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43
44 /* FIXME none of these flags should be global to all ARM11 cores!
45 * Most of them shouldn't exist at all, once the code works...
46 */
47 static bool arm11_config_memwrite_burst = true;
48 static bool arm11_config_memwrite_error_fatal = true;
49 static uint32_t arm11_vcr = 0;
50 static bool arm11_config_step_irq_enable = false;
51 static bool arm11_config_hardware_step = false;
52
53 static int arm11_step(struct target *target, int current,
54 uint32_t address, int handle_breakpoints);
55
56
57 /** Check and if necessary take control of the system
58 *
59 * \param arm11 Target state variable.
60 */
61 static int arm11_check_init(struct arm11_common *arm11)
62 {
63 CHECK_RETVAL(arm11_read_DSCR(arm11));
64 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
65
66 if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
67 {
68 LOG_DEBUG("Bringing target into debug mode");
69
70 arm11->dscr |= DSCR_HALT_DBG_MODE;
71 arm11_write_DSCR(arm11, arm11->dscr);
72
73 /* add further reset initialization here */
74
75 arm11->simulate_reset_on_next_halt = true;
76
77 if (arm11->dscr & DSCR_CORE_HALTED)
78 {
79 /** \todo TODO: this needs further scrutiny because
80 * arm11_debug_entry() never gets called. (WHY NOT?)
81 * As a result we don't read the actual register states from
82 * the target.
83 */
84
85 arm11->arm.target->state = TARGET_HALTED;
86 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
87 }
88 else
89 {
90 arm11->arm.target->state = TARGET_RUNNING;
91 arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
92 }
93
94 arm11_sc7_clear_vbw(arm11);
95 }
96
97 return ERROR_OK;
98 }
99
100 /**
101 * Save processor state. This is called after a HALT instruction
102 * succeeds, and on other occasions the processor enters debug mode
103 * (breakpoint, watchpoint, etc). Caller has updated arm11->dscr.
104 */
105 static int arm11_debug_entry(struct arm11_common *arm11)
106 {
107 int retval;
108
109 arm11->arm.target->state = TARGET_HALTED;
110 arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
111
112 /* REVISIT entire cache should already be invalid !!! */
113 register_cache_invalidate(arm11->arm.core_cache);
114
115 /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
116
117 /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
118 arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
119 if (arm11->is_wdtr_saved)
120 {
121 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
122
123 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
124
125 struct scan_field chain5_fields[3];
126
127 arm11_setup_field(arm11, 32, NULL,
128 &arm11->saved_wdtr, chain5_fields + 0);
129 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
130 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
131
132 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
133
134 }
135
136 /* DSCR: set the Execute ARM instruction enable bit.
137 *
138 * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
139 * but not to issue ITRs(?). The ARMv7 arch spec says it's required
140 * for executing instructions via ITR.
141 */
142 arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
143
144
145 /* From the spec:
146 Before executing any instruction in debug state you have to drain the write buffer.
147 This ensures that no imprecise Data Aborts can return at a later point:*/
148
149 /** \todo TODO: Test drain write buffer. */
150
151 #if 0
152 while (1)
153 {
154 /* MRC p14,0,R0,c5,c10,0 */
155 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
156
157 /* mcr 15, 0, r0, cr7, cr10, {4} */
158 arm11_run_instr_no_data1(arm11, 0xee070f9a);
159
160 uint32_t dscr = arm11_read_DSCR(arm11);
161
162 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
163
164 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
165 {
166 arm11_run_instr_no_data1(arm11, 0xe320f000);
167
168 dscr = arm11_read_DSCR(arm11);
169
170 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
171
172 break;
173 }
174 }
175 #endif
176
177 /* Save registers.
178 *
179 * NOTE: ARM1136 TRM suggests saving just R0 here now, then
180 * CPSR and PC after the rDTR stuff. We do it all at once.
181 */
182 retval = arm_dpm_read_current_registers(&arm11->dpm);
183 if (retval != ERROR_OK)
184 LOG_ERROR("DPM REG READ -- fail %d", retval);
185
186 retval = arm11_run_instr_data_prepare(arm11);
187 if (retval != ERROR_OK)
188 return retval;
189
190 /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
191 arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
192 if (arm11->is_rdtr_saved)
193 {
194 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
195 retval = arm11_run_instr_data_from_core_via_r0(arm11,
196 0xEE100E15, &arm11->saved_rdtr);
197 if (retval != ERROR_OK)
198 return retval;
199 }
200
201 /* REVISIT Now that we've saved core state, there's may also
202 * be MMU and cache state to care about ...
203 */
204
205 if (arm11->simulate_reset_on_next_halt)
206 {
207 arm11->simulate_reset_on_next_halt = false;
208
209 LOG_DEBUG("Reset c1 Control Register");
210
211 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
212
213 /* MCR p15,0,R0,c1,c0,0 */
214 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
215 if (retval != ERROR_OK)
216 return retval;
217
218 }
219
220 if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
221 uint32_t wfar;
222
223 /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
224 retval = arm11_run_instr_data_from_core_via_r0(arm11,
225 ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
226 &wfar);
227 if (retval != ERROR_OK)
228 return retval;
229 arm_dpm_report_wfar(arm11->arm.dpm, wfar);
230 }
231
232
233 retval = arm11_run_instr_data_finish(arm11);
234 if (retval != ERROR_OK)
235 return retval;
236
237 return ERROR_OK;
238 }
239
240 /**
241 * Restore processor state. This is called in preparation for
242 * the RESTART function.
243 */
244 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
245 {
246 int retval;
247
248 /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
249
250 /* NOTE: the ARM1136 TRM suggests restoring all registers
251 * except R0/PC/CPSR right now. Instead, we do them all
252 * at once, just a bit later on.
253 */
254
255 /* REVISIT once we start caring about MMU and cache state,
256 * address it here ...
257 */
258
259 /* spec says clear wDTR and rDTR; we assume they are clear as
260 otherwise our programming would be sloppy */
261 {
262 CHECK_RETVAL(arm11_read_DSCR(arm11));
263
264 if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
265 {
266 /*
267 The wDTR/rDTR two registers that are used to send/receive data to/from
268 the core in tandem with corresponding instruction codes that are
269 written into the core. The RDTR FULL/WDTR FULL flag indicates that the
270 registers hold data that was written by one side (CPU or JTAG) and not
271 read out by the other side.
272 */
273 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
274 (unsigned) arm11->dscr);
275 return ERROR_FAIL;
276 }
277 }
278
279 /* maybe restore original wDTR */
280 if (arm11->is_wdtr_saved)
281 {
282 retval = arm11_run_instr_data_prepare(arm11);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* MCR p14,0,R0,c0,c5,0 */
287 retval = arm11_run_instr_data_to_core_via_r0(arm11,
288 0xee000e15, arm11->saved_wdtr);
289 if (retval != ERROR_OK)
290 return retval;
291
292 retval = arm11_run_instr_data_finish(arm11);
293 if (retval != ERROR_OK)
294 return retval;
295 }
296
297 /* restore CPSR, PC, and R0 ... after flushing any modified
298 * registers.
299 */
300 retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
301
302 retval = arm11_bpwp_flush(arm11);
303
304 register_cache_invalidate(arm11->arm.core_cache);
305
306 /* restore DSCR */
307 arm11_write_DSCR(arm11, arm11->dscr);
308
309 /* maybe restore rDTR */
310 if (arm11->is_rdtr_saved)
311 {
312 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
313
314 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
315
316 struct scan_field chain5_fields[3];
317
318 uint8_t Ready = 0; /* ignored */
319 uint8_t Valid = 0; /* ignored */
320
321 arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
322 NULL, chain5_fields + 0);
323 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
324 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
325
326 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
327 }
328
329 /* now processor is ready to RESTART */
330
331 return ERROR_OK;
332 }
333
334 /* poll current target status */
335 static int arm11_poll(struct target *target)
336 {
337 int retval;
338 struct arm11_common *arm11 = target_to_arm11(target);
339
340 CHECK_RETVAL(arm11_check_init(arm11));
341
342 if (arm11->dscr & DSCR_CORE_HALTED)
343 {
344 if (target->state != TARGET_HALTED)
345 {
346 enum target_state old_state = target->state;
347
348 LOG_DEBUG("enter TARGET_HALTED");
349 retval = arm11_debug_entry(arm11);
350 if (retval != ERROR_OK)
351 return retval;
352
353 target_call_event_callbacks(target,
354 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
355 }
356 }
357 else
358 {
359 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
360 {
361 LOG_DEBUG("enter TARGET_RUNNING");
362 target->state = TARGET_RUNNING;
363 target->debug_reason = DBG_REASON_NOTHALTED;
364 }
365 }
366
367 return ERROR_OK;
368 }
369 /* architecture specific status reply */
370 static int arm11_arch_state(struct target *target)
371 {
372 struct arm11_common *arm11 = target_to_arm11(target);
373 int retval;
374
375 retval = armv4_5_arch_state(target);
376
377 /* REVISIT also display ARM11-specific MMU and cache status ... */
378
379 if (target->debug_reason == DBG_REASON_WATCHPOINT)
380 LOG_USER("Watchpoint triggered at PC %#08x",
381 (unsigned) arm11->dpm.wp_pc);
382
383 return retval;
384 }
385
386 /* target request support */
387 static int arm11_target_request_data(struct target *target,
388 uint32_t size, uint8_t *buffer)
389 {
390 LOG_WARNING("Not implemented: %s", __func__);
391
392 return ERROR_FAIL;
393 }
394
395 /* target execution control */
396 static int arm11_halt(struct target *target)
397 {
398 struct arm11_common *arm11 = target_to_arm11(target);
399
400 LOG_DEBUG("target->state: %s",
401 target_state_name(target));
402
403 if (target->state == TARGET_UNKNOWN)
404 {
405 arm11->simulate_reset_on_next_halt = true;
406 }
407
408 if (target->state == TARGET_HALTED)
409 {
410 LOG_DEBUG("target was already halted");
411 return ERROR_OK;
412 }
413
414 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
415
416 CHECK_RETVAL(jtag_execute_queue());
417
418 int i = 0;
419
420 while (1)
421 {
422 CHECK_RETVAL(arm11_read_DSCR(arm11));
423
424 if (arm11->dscr & DSCR_CORE_HALTED)
425 break;
426
427
428 long long then = 0;
429 if (i == 1000)
430 {
431 then = timeval_ms();
432 }
433 if (i >= 1000)
434 {
435 if ((timeval_ms()-then) > 1000)
436 {
437 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
438 return ERROR_FAIL;
439 }
440 }
441 i++;
442 }
443
444 enum target_state old_state = target->state;
445
446 arm11_debug_entry(arm11);
447
448 CHECK_RETVAL(
449 target_call_event_callbacks(target,
450 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
451
452 return ERROR_OK;
453 }
454
455 static uint32_t
456 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
457 {
458 void *value = arm11->arm.core_cache->reg_list[15].value;
459
460 if (!current)
461 buf_set_u32(value, 0, 32, address);
462 else
463 address = buf_get_u32(value, 0, 32);
464
465 return address;
466 }
467
468 static int arm11_resume(struct target *target, int current,
469 uint32_t address, int handle_breakpoints, int debug_execution)
470 {
471 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
472 // current, address, handle_breakpoints, debug_execution);
473
474 struct arm11_common *arm11 = target_to_arm11(target);
475
476 LOG_DEBUG("target->state: %s",
477 target_state_name(target));
478
479
480 if (target->state != TARGET_HALTED)
481 {
482 LOG_ERROR("Target not halted");
483 return ERROR_TARGET_NOT_HALTED;
484 }
485
486 address = arm11_nextpc(arm11, current, address);
487
488 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
489
490 /* clear breakpoints/watchpoints and VCR*/
491 arm11_sc7_clear_vbw(arm11);
492
493 if (!debug_execution)
494 target_free_all_working_areas(target);
495
496 /* Set up breakpoints */
497 if (handle_breakpoints)
498 {
499 /* check if one matches PC and step over it if necessary */
500
501 struct breakpoint * bp;
502
503 for (bp = target->breakpoints; bp; bp = bp->next)
504 {
505 if (bp->address == address)
506 {
507 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
508 arm11_step(target, 1, 0, 0);
509 break;
510 }
511 }
512
513 /* set all breakpoints */
514
515 unsigned brp_num = 0;
516
517 for (bp = target->breakpoints; bp; bp = bp->next)
518 {
519 struct arm11_sc7_action brp[2];
520
521 brp[0].write = 1;
522 brp[0].address = ARM11_SC7_BVR0 + brp_num;
523 brp[0].value = bp->address;
524 brp[1].write = 1;
525 brp[1].address = ARM11_SC7_BCR0 + brp_num;
526 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
527
528 arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
529
530 LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
531 bp->address);
532
533 brp_num++;
534 }
535
536 if (arm11_vcr)
537 arm11_sc7_set_vcr(arm11, arm11_vcr);
538 }
539
540 arm11_leave_debug_state(arm11, handle_breakpoints);
541
542 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
543
544 CHECK_RETVAL(jtag_execute_queue());
545
546 int i = 0;
547 while (1)
548 {
549 CHECK_RETVAL(arm11_read_DSCR(arm11));
550
551 LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
552
553 if (arm11->dscr & DSCR_CORE_RESTARTED)
554 break;
555
556
557 long long then = 0;
558 if (i == 1000)
559 {
560 then = timeval_ms();
561 }
562 if (i >= 1000)
563 {
564 if ((timeval_ms()-then) > 1000)
565 {
566 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
567 return ERROR_FAIL;
568 }
569 }
570 i++;
571 }
572
573 target->debug_reason = DBG_REASON_NOTHALTED;
574 if (!debug_execution)
575 target->state = TARGET_RUNNING;
576 else
577 target->state = TARGET_DEBUG_RUNNING;
578 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
579
580 return ERROR_OK;
581 }
582
583 static int arm11_step(struct target *target, int current,
584 uint32_t address, int handle_breakpoints)
585 {
586 LOG_DEBUG("target->state: %s",
587 target_state_name(target));
588
589 if (target->state != TARGET_HALTED)
590 {
591 LOG_WARNING("target was not halted");
592 return ERROR_TARGET_NOT_HALTED;
593 }
594
595 struct arm11_common *arm11 = target_to_arm11(target);
596
597 address = arm11_nextpc(arm11, current, address);
598
599 LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
600
601
602 /** \todo TODO: Thumb not supported here */
603
604 uint32_t next_instruction;
605
606 CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
607
608 /* skip over BKPT */
609 if ((next_instruction & 0xFFF00070) == 0xe1200070)
610 {
611 address = arm11_nextpc(arm11, 0, address + 4);
612 LOG_DEBUG("Skipping BKPT");
613 }
614 /* skip over Wait for interrupt / Standby */
615 /* mcr 15, 0, r?, cr7, cr0, {4} */
616 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
617 {
618 address = arm11_nextpc(arm11, 0, address + 4);
619 LOG_DEBUG("Skipping WFI");
620 }
621 /* ignore B to self */
622 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
623 {
624 LOG_DEBUG("Not stepping jump to self");
625 }
626 else
627 {
628 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
629 * with this. */
630
631 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
632 * the VCR might be something worth looking into. */
633
634
635 /* Set up breakpoint for stepping */
636
637 struct arm11_sc7_action brp[2];
638
639 brp[0].write = 1;
640 brp[0].address = ARM11_SC7_BVR0;
641 brp[1].write = 1;
642 brp[1].address = ARM11_SC7_BCR0;
643
644 if (arm11_config_hardware_step)
645 {
646 /* Hardware single stepping ("instruction address
647 * mismatch") is used if enabled. It's not quite
648 * exactly "run one instruction"; "branch to here"
649 * loops won't break, neither will some other cases,
650 * but it's probably the best default.
651 *
652 * Hardware single stepping isn't supported on v6
653 * debug modules. ARM1176 and v7 can support it...
654 *
655 * FIXME Thumb stepping likely needs to use 0x03
656 * or 0xc0 byte masks, not 0x0f.
657 */
658 brp[0].value = address;
659 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
660 | (0 << 14) | (0 << 16) | (0 << 20)
661 | (2 << 21);
662 } else
663 {
664 /* Sets a breakpoint on the next PC, as calculated
665 * by instruction set simulation.
666 *
667 * REVISIT stepping Thumb on ARM1156 requires Thumb2
668 * support from the simulator.
669 */
670 uint32_t next_pc;
671 int retval;
672
673 retval = arm_simulate_step(target, &next_pc);
674 if (retval != ERROR_OK)
675 return retval;
676
677 brp[0].value = next_pc;
678 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5)
679 | (0 << 14) | (0 << 16) | (0 << 20)
680 | (0 << 21);
681 }
682
683 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
684
685 /* resume */
686
687
688 if (arm11_config_step_irq_enable)
689 /* this disable should be redundant ... */
690 arm11->dscr &= ~DSCR_INT_DIS;
691 else
692 arm11->dscr |= DSCR_INT_DIS;
693
694
695 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
696
697 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
698
699 CHECK_RETVAL(jtag_execute_queue());
700
701 /* wait for halt */
702 int i = 0;
703
704 while (1)
705 {
706 const uint32_t mask = DSCR_CORE_RESTARTED
707 | DSCR_CORE_HALTED;
708
709 CHECK_RETVAL(arm11_read_DSCR(arm11));
710 LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
711
712 if ((arm11->dscr & mask) == mask)
713 break;
714
715 long long then = 0;
716 if (i == 1000)
717 {
718 then = timeval_ms();
719 }
720 if (i >= 1000)
721 {
722 if ((timeval_ms()-then) > 1000)
723 {
724 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
725 return ERROR_FAIL;
726 }
727 }
728 i++;
729 }
730
731 /* clear breakpoint */
732 arm11_sc7_clear_vbw(arm11);
733
734 /* save state */
735 CHECK_RETVAL(arm11_debug_entry(arm11));
736
737 /* restore default state */
738 arm11->dscr &= ~DSCR_INT_DIS;
739
740 }
741
742 target->debug_reason = DBG_REASON_SINGLESTEP;
743
744 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
745
746 return ERROR_OK;
747 }
748
749 static int arm11_assert_reset(struct target *target)
750 {
751 int retval;
752 struct arm11_common *arm11 = target_to_arm11(target);
753
754 retval = arm11_check_init(arm11);
755 if (retval != ERROR_OK)
756 return retval;
757
758 target->state = TARGET_UNKNOWN;
759
760 /* we would very much like to reset into the halted, state,
761 * but resetting and halting is second best... */
762 if (target->reset_halt)
763 {
764 CHECK_RETVAL(target_halt(target));
765 }
766
767
768 /* srst is funny. We can not do *anything* else while it's asserted
769 * and it has unkonwn side effects. Make sure no other code runs
770 * meanwhile.
771 *
772 * Code below assumes srst:
773 *
774 * - Causes power-on-reset (but of what parts of the system?). Bug
775 * in arm11?
776 *
777 * - Messes us TAP state without asserting trst.
778 *
779 * - There is another bug in the arm11 core. When you generate an access to
780 * external logic (for example ddr controller via AHB bus) and that block
781 * is not configured (perhaps it is still held in reset), that transaction
782 * will never complete. This will hang arm11 core but it will also hang
783 * JTAG controller. Nothing, short of srst assertion will bring it out of
784 * this.
785 *
786 * Mysteries:
787 *
788 * - What should the PC be after an srst reset when starting in the halted
789 * state?
790 */
791
792 jtag_add_reset(0, 1);
793 jtag_add_reset(0, 0);
794
795 /* How long do we have to wait? */
796 jtag_add_sleep(5000);
797
798 /* un-mess up TAP state */
799 jtag_add_tlr();
800
801 retval = jtag_execute_queue();
802 if (retval != ERROR_OK)
803 {
804 return retval;
805 }
806
807 return ERROR_OK;
808 }
809
810 static int arm11_deassert_reset(struct target *target)
811 {
812 return ERROR_OK;
813 }
814
815 static int arm11_soft_reset_halt(struct target *target)
816 {
817 LOG_WARNING("Not implemented: %s", __func__);
818
819 return ERROR_FAIL;
820 }
821
822 /* target memory access
823 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
824 * count: number of items of <size>
825 *
826 * arm11_config_memrw_no_increment - in the future we may want to be able
827 * to read/write a range of data to a "port". a "port" is an action on
828 * read memory address for some peripheral.
829 */
830 static int arm11_read_memory_inner(struct target *target,
831 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
832 bool arm11_config_memrw_no_increment)
833 {
834 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
835 int retval;
836
837 if (target->state != TARGET_HALTED)
838 {
839 LOG_WARNING("target was not halted");
840 return ERROR_TARGET_NOT_HALTED;
841 }
842
843 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
844
845 struct arm11_common *arm11 = target_to_arm11(target);
846
847 retval = arm11_run_instr_data_prepare(arm11);
848 if (retval != ERROR_OK)
849 return retval;
850
851 /* MRC p14,0,r0,c0,c5,0 */
852 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
853 if (retval != ERROR_OK)
854 return retval;
855
856 switch (size)
857 {
858 case 1:
859 arm11->arm.core_cache->reg_list[1].dirty = true;
860
861 for (size_t i = 0; i < count; i++)
862 {
863 /* ldrb r1, [r0], #1 */
864 /* ldrb r1, [r0] */
865 arm11_run_instr_no_data1(arm11,
866 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
867
868 uint32_t res;
869 /* MCR p14,0,R1,c0,c5,0 */
870 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
871
872 *buffer++ = res;
873 }
874
875 break;
876
877 case 2:
878 {
879 arm11->arm.core_cache->reg_list[1].dirty = true;
880
881 for (size_t i = 0; i < count; i++)
882 {
883 /* ldrh r1, [r0], #2 */
884 arm11_run_instr_no_data1(arm11,
885 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
886
887 uint32_t res;
888
889 /* MCR p14,0,R1,c0,c5,0 */
890 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
891
892 uint16_t svalue = res;
893 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
894 }
895
896 break;
897 }
898
899 case 4:
900 {
901 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
902 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
903 uint32_t *words = (uint32_t *)buffer;
904
905 /* LDC p14,c5,[R0],#4 */
906 /* LDC p14,c5,[R0] */
907 arm11_run_instr_data_from_core(arm11, instr, words, count);
908 break;
909 }
910 }
911
912 return arm11_run_instr_data_finish(arm11);
913 }
914
915 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
916 {
917 return arm11_read_memory_inner(target, address, size, count, buffer, false);
918 }
919
920 /*
921 * no_increment - in the future we may want to be able
922 * to read/write a range of data to a "port". a "port" is an action on
923 * read memory address for some peripheral.
924 */
925 static int arm11_write_memory_inner(struct target *target,
926 uint32_t address, uint32_t size,
927 uint32_t count, uint8_t *buffer,
928 bool no_increment)
929 {
930 int retval;
931
932 if (target->state != TARGET_HALTED)
933 {
934 LOG_WARNING("target was not halted");
935 return ERROR_TARGET_NOT_HALTED;
936 }
937
938 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
939
940 struct arm11_common *arm11 = target_to_arm11(target);
941
942 retval = arm11_run_instr_data_prepare(arm11);
943 if (retval != ERROR_OK)
944 return retval;
945
946 /* MRC p14,0,r0,c0,c5,0 */
947 retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
948 if (retval != ERROR_OK)
949 return retval;
950
951 /* burst writes are not used for single words as those may well be
952 * reset init script writes.
953 *
954 * The other advantage is that as burst writes are default, we'll
955 * now exercise both burst and non-burst code paths with the
956 * default settings, increasing code coverage.
957 */
958 bool burst = arm11_config_memwrite_burst && (count > 1);
959
960 switch (size)
961 {
962 case 1:
963 {
964 arm11->arm.core_cache->reg_list[1].dirty = true;
965
966 for (size_t i = 0; i < count; i++)
967 {
968 /* MRC p14,0,r1,c0,c5,0 */
969 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
970 if (retval != ERROR_OK)
971 return retval;
972
973 /* strb r1, [r0], #1 */
974 /* strb r1, [r0] */
975 retval = arm11_run_instr_no_data1(arm11,
976 !no_increment
977 ? 0xe4c01001
978 : 0xe5c01000);
979 if (retval != ERROR_OK)
980 return retval;
981 }
982
983 break;
984 }
985
986 case 2:
987 {
988 arm11->arm.core_cache->reg_list[1].dirty = true;
989
990 for (size_t i = 0; i < count; i++)
991 {
992 uint16_t value;
993 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
994
995 /* MRC p14,0,r1,c0,c5,0 */
996 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
997 if (retval != ERROR_OK)
998 return retval;
999
1000 /* strh r1, [r0], #2 */
1001 /* strh r1, [r0] */
1002 retval = arm11_run_instr_no_data1(arm11,
1003 !no_increment
1004 ? 0xe0c010b2
1005 : 0xe1c010b0);
1006 if (retval != ERROR_OK)
1007 return retval;
1008 }
1009
1010 break;
1011 }
1012
1013 case 4: {
1014 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1015
1016 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1017 uint32_t *words = (uint32_t*)buffer;
1018
1019 if (!burst)
1020 {
1021 /* STC p14,c5,[R0],#4 */
1022 /* STC p14,c5,[R0]*/
1023 retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1024 if (retval != ERROR_OK)
1025 return retval;
1026 }
1027 else
1028 {
1029 /* STC p14,c5,[R0],#4 */
1030 /* STC p14,c5,[R0]*/
1031 retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1032 if (retval != ERROR_OK)
1033 return retval;
1034 }
1035
1036 break;
1037 }
1038 }
1039
1040 /* r0 verification */
1041 if (!no_increment)
1042 {
1043 uint32_t r0;
1044
1045 /* MCR p14,0,R0,c0,c5,0 */
1046 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1047 if (retval != ERROR_OK)
1048 return retval;
1049
1050 if (address + size * count != r0)
1051 {
1052 LOG_ERROR("Data transfer failed. Expected end "
1053 "address 0x%08x, got 0x%08x",
1054 (unsigned) (address + size * count),
1055 (unsigned) r0);
1056
1057 if (burst)
1058 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1059
1060 if (arm11_config_memwrite_error_fatal)
1061 return ERROR_FAIL;
1062 }
1063 }
1064
1065 return arm11_run_instr_data_finish(arm11);
1066 }
1067
1068 static int arm11_write_memory(struct target *target,
1069 uint32_t address, uint32_t size,
1070 uint32_t count, uint8_t *buffer)
1071 {
1072 /* pointer increment matters only for multi-unit writes ...
1073 * not e.g. to a "reset the chip" controller.
1074 */
1075 return arm11_write_memory_inner(target, address, size,
1076 count, buffer, count == 1);
1077 }
1078
1079 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1080 static int arm11_bulk_write_memory(struct target *target,
1081 uint32_t address, uint32_t count, uint8_t *buffer)
1082 {
1083 if (target->state != TARGET_HALTED)
1084 {
1085 LOG_WARNING("target was not halted");
1086 return ERROR_TARGET_NOT_HALTED;
1087 }
1088
1089 return arm11_write_memory(target, address, 4, count, buffer);
1090 }
1091
1092 /* target break-/watchpoint control
1093 * rw: 0 = write, 1 = read, 2 = access
1094 */
1095 static int arm11_add_breakpoint(struct target *target,
1096 struct breakpoint *breakpoint)
1097 {
1098 struct arm11_common *arm11 = target_to_arm11(target);
1099
1100 #if 0
1101 if (breakpoint->type == BKPT_SOFT)
1102 {
1103 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1104 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1105 }
1106 #endif
1107
1108 if (!arm11->free_brps)
1109 {
1110 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1111 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1112 }
1113
1114 if (breakpoint->length != 4)
1115 {
1116 LOG_DEBUG("only breakpoints of four bytes length supported");
1117 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1118 }
1119
1120 arm11->free_brps--;
1121
1122 return ERROR_OK;
1123 }
1124
1125 static int arm11_remove_breakpoint(struct target *target,
1126 struct breakpoint *breakpoint)
1127 {
1128 struct arm11_common *arm11 = target_to_arm11(target);
1129
1130 arm11->free_brps++;
1131
1132 return ERROR_OK;
1133 }
1134
1135 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1136 {
1137 struct arm11_common *arm11;
1138
1139 if (target->tap == NULL)
1140 return ERROR_FAIL;
1141
1142 if (target->tap->ir_length != 5)
1143 {
1144 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1145 return ERROR_COMMAND_SYNTAX_ERROR;
1146 }
1147
1148 arm11 = calloc(1, sizeof *arm11);
1149 if (!arm11)
1150 return ERROR_FAIL;
1151
1152 armv4_5_init_arch_info(target, &arm11->arm);
1153
1154 arm11->jtag_info.tap = target->tap;
1155 arm11->jtag_info.scann_size = 5;
1156 arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1157 arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */
1158 arm11->jtag_info.intest_instr = ARM11_INTEST;
1159
1160 return ERROR_OK;
1161 }
1162
1163 static int arm11_init_target(struct command_context *cmd_ctx,
1164 struct target *target)
1165 {
1166 /* Initialize anything we can set up without talking to the target */
1167 return ERROR_OK;
1168 }
1169
1170 /* talk to the target and set things up */
1171 static int arm11_examine(struct target *target)
1172 {
1173 int retval;
1174 char *type;
1175 struct arm11_common *arm11 = target_to_arm11(target);
1176 uint32_t didr, device_id;
1177 uint8_t implementor;
1178
1179 /* FIXME split into do-first-time and do-every-time logic ... */
1180
1181 /* check IDCODE */
1182
1183 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1184
1185 struct scan_field idcode_field;
1186
1187 arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1188
1189 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1190
1191 /* check DIDR */
1192
1193 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1194
1195 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1196
1197 struct scan_field chain0_fields[2];
1198
1199 arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1200 arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
1201
1202 arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1203
1204 CHECK_RETVAL(jtag_execute_queue());
1205
1206 switch (device_id & 0x0FFFF000)
1207 {
1208 case 0x07B36000:
1209 type = "ARM1136";
1210 break;
1211 case 0x07B56000:
1212 type = "ARM1156";
1213 break;
1214 case 0x07B76000:
1215 arm11->arm.core_type = ARM_MODE_MON;
1216 type = "ARM1176";
1217 break;
1218 default:
1219 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1220 return ERROR_FAIL;
1221 }
1222 LOG_INFO("found %s", type);
1223
1224 /* unlikely this could ever fail, but ... */
1225 switch ((didr >> 16) & 0x0F) {
1226 case ARM11_DEBUG_V6:
1227 case ARM11_DEBUG_V61: /* supports security extensions */
1228 break;
1229 default:
1230 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1231 return ERROR_FAIL;
1232 }
1233
1234 arm11->brp = ((didr >> 24) & 0x0F) + 1;
1235
1236 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1237 arm11->free_brps = arm11->brp;
1238
1239 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1240 device_id, implementor, didr);
1241
1242 /* as a side-effect this reads DSCR and thus
1243 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1244 * as suggested by the spec.
1245 */
1246
1247 retval = arm11_check_init(arm11);
1248 if (retval != ERROR_OK)
1249 return retval;
1250
1251 /* Build register cache "late", after target_init(), since we
1252 * want to know if this core supports Secure Monitor mode.
1253 */
1254 if (!target_was_examined(target))
1255 retval = arm11_dpm_init(arm11, didr);
1256
1257 /* ETM on ARM11 still uses original scanchain 6 access mode */
1258 if (arm11->arm.etm && !target_was_examined(target)) {
1259 *register_get_last_cache_p(&target->reg_cache) =
1260 etm_build_reg_cache(target, &arm11->jtag_info,
1261 arm11->arm.etm);
1262 retval = etm_setup(target);
1263 }
1264
1265 target_set_examined(target);
1266
1267 return ERROR_OK;
1268 }
1269
1270
1271 /* FIXME all these BOOL_WRAPPER things should be modifying
1272 * per-instance state, not shared state; ditto the vector
1273 * catch register support. Scan chains with multiple cores
1274 * should be able to say "work with this core like this,
1275 * that core like that". Example, ARM11 MPCore ...
1276 */
1277
1278 #define ARM11_BOOL_WRAPPER(name, print_name) \
1279 COMMAND_HANDLER(arm11_handle_bool_##name) \
1280 { \
1281 return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1282 &arm11_config_##name, print_name); \
1283 }
1284
1285 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1286 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1287 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1288 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1289
1290 COMMAND_HANDLER(arm11_handle_vcr)
1291 {
1292 switch (CMD_ARGC) {
1293 case 0:
1294 break;
1295 case 1:
1296 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1297 break;
1298 default:
1299 return ERROR_COMMAND_SYNTAX_ERROR;
1300 }
1301
1302 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1303 return ERROR_OK;
1304 }
1305
1306 static const struct command_registration arm11_mw_command_handlers[] = {
1307 {
1308 .name = "burst",
1309 .handler = &arm11_handle_bool_memwrite_burst,
1310 .mode = COMMAND_ANY,
1311 .help = "Enable/Disable non-standard but fast burst mode"
1312 " (default: enabled)",
1313 },
1314 {
1315 .name = "error_fatal",
1316 .handler = &arm11_handle_bool_memwrite_error_fatal,
1317 .mode = COMMAND_ANY,
1318 .help = "Terminate program if transfer error was found"
1319 " (default: enabled)",
1320 },
1321 COMMAND_REGISTRATION_DONE
1322 };
1323 static const struct command_registration arm11_any_command_handlers[] = {
1324 {
1325 /* "hardware_step" is only here to check if the default
1326 * simulate + breakpoint implementation is broken.
1327 * TEMPORARY! NOT DOCUMENTED! */
1328 .name = "hardware_step",
1329 .handler = &arm11_handle_bool_hardware_step,
1330 .mode = COMMAND_ANY,
1331 .help = "DEBUG ONLY - Hardware single stepping"
1332 " (default: disabled)",
1333 .usage = "(enable|disable)",
1334 },
1335 {
1336 .name = "memwrite",
1337 .mode = COMMAND_ANY,
1338 .help = "memwrite command group",
1339 .chain = arm11_mw_command_handlers,
1340 },
1341 {
1342 .name = "step_irq_enable",
1343 .handler = &arm11_handle_bool_step_irq_enable,
1344 .mode = COMMAND_ANY,
1345 .help = "Enable interrupts while stepping"
1346 " (default: disabled)",
1347 },
1348 {
1349 .name = "vcr",
1350 .handler = &arm11_handle_vcr,
1351 .mode = COMMAND_ANY,
1352 .help = "Control (Interrupt) Vector Catch Register",
1353 },
1354 COMMAND_REGISTRATION_DONE
1355 };
1356 static const struct command_registration arm11_command_handlers[] = {
1357 {
1358 .chain = arm_command_handlers,
1359 },
1360 {
1361 .chain = etm_command_handlers,
1362 },
1363 {
1364 .name = "arm11",
1365 .mode = COMMAND_ANY,
1366 .help = "ARM11 command group",
1367 .chain = arm11_any_command_handlers,
1368 },
1369 COMMAND_REGISTRATION_DONE
1370 };
1371
1372 /** Holds methods for ARM11xx targets. */
1373 struct target_type arm11_target = {
1374 .name = "arm11",
1375
1376 .poll = arm11_poll,
1377 .arch_state = arm11_arch_state,
1378
1379 .target_request_data = arm11_target_request_data,
1380
1381 .halt = arm11_halt,
1382 .resume = arm11_resume,
1383 .step = arm11_step,
1384
1385 .assert_reset = arm11_assert_reset,
1386 .deassert_reset = arm11_deassert_reset,
1387 .soft_reset_halt = arm11_soft_reset_halt,
1388
1389 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1390
1391 .read_memory = arm11_read_memory,
1392 .write_memory = arm11_write_memory,
1393
1394 .bulk_write_memory = arm11_bulk_write_memory,
1395
1396 .checksum_memory = arm_checksum_memory,
1397 .blank_check_memory = arm_blank_check_memory,
1398
1399 .add_breakpoint = arm11_add_breakpoint,
1400 .remove_breakpoint = arm11_remove_breakpoint,
1401
1402 .run_algorithm = armv4_5_run_algorithm,
1403
1404 .commands = arm11_command_handlers,
1405 .target_create = arm11_target_create,
1406 .init_target = arm11_init_target,
1407 .examine = arm11_examine,
1408 };
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