?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
- Fixes '!=' whitespace
[openocd.git] / src / target / arm9tdmi.c
blob75ae3e8b78e2effef687c990ad061b362ba681c3
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Hongtao Zheng *
9 * hontor@126.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "arm9tdmi.h"
31 #include "target_type.h"
32
33
34 #if 0
35 #define _DEBUG_INSTRUCTION_EXECUTION_
36 #endif
37
38 /* cli handling */
39 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
41 /* forward declarations */
42 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
43
44 int arm9tdmi_quit(void);
45
46 target_type_t arm9tdmi_target =
47 {
48 .name = "arm9tdmi",
49
50 .poll = arm7_9_poll,
51 .arch_state = armv4_5_arch_state,
52
53 .target_request_data = arm7_9_target_request_data,
54
55 .halt = arm7_9_halt,
56 .resume = arm7_9_resume,
57 .step = arm7_9_step,
58
59 .assert_reset = arm7_9_assert_reset,
60 .deassert_reset = arm7_9_deassert_reset,
61 .soft_reset_halt = arm7_9_soft_reset_halt,
62
63 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
64
65 .read_memory = arm7_9_read_memory,
66 .write_memory = arm7_9_write_memory,
67 .bulk_write_memory = arm7_9_bulk_write_memory,
68 .checksum_memory = arm7_9_checksum_memory,
69 .blank_check_memory = arm7_9_blank_check_memory,
70
71 .run_algorithm = armv4_5_run_algorithm,
72
73 .add_breakpoint = arm7_9_add_breakpoint,
74 .remove_breakpoint = arm7_9_remove_breakpoint,
75 .add_watchpoint = arm7_9_add_watchpoint,
76 .remove_watchpoint = arm7_9_remove_watchpoint,
77
78 .register_commands = arm9tdmi_register_commands,
79 .target_create = arm9tdmi_target_create,
80 .init_target = arm9tdmi_init_target,
81 .examine = arm9tdmi_examine,
82 .quit = arm9tdmi_quit
83 };
84
85 arm9tdmi_vector_t arm9tdmi_vectors[] =
86 {
87 {"reset", ARM9TDMI_RESET_VECTOR},
88 {"undef", ARM9TDMI_UNDEF_VECTOR},
89 {"swi", ARM9TDMI_SWI_VECTOR},
90 {"pabt", ARM9TDMI_PABT_VECTOR},
91 {"dabt", ARM9TDMI_DABT_VECTOR},
92 {"reserved", ARM9TDMI_RESERVED_VECTOR},
93 {"irq", ARM9TDMI_IRQ_VECTOR},
94 {"fiq", ARM9TDMI_FIQ_VECTOR},
95 {0, 0},
96 };
97
98 int arm9tdmi_examine_debug_reason(target_t *target)
99 {
100 int retval = ERROR_OK;
101 /* get pointers to arch-specific information */
102 armv4_5_common_t *armv4_5 = target->arch_info;
103 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
104
105 /* only check the debug reason if we don't know it already */
106 if ((target->debug_reason != DBG_REASON_DBGRQ)
107 && (target->debug_reason != DBG_REASON_SINGLESTEP))
108 {
109 scan_field_t fields[3];
110 uint8_t databus[4];
111 uint8_t instructionbus[4];
112 uint8_t debug_reason;
113
114 jtag_set_end_state(TAP_DRPAUSE);
115
116 fields[0].tap = arm7_9->jtag_info.tap;
117 fields[0].num_bits = 32;
118 fields[0].out_value = NULL;
119 fields[0].in_value = databus;
120
121 fields[1].tap = arm7_9->jtag_info.tap;
122 fields[1].num_bits = 3;
123 fields[1].out_value = NULL;
124 fields[1].in_value = &debug_reason;
125
126 fields[2].tap = arm7_9->jtag_info.tap;
127 fields[2].num_bits = 32;
128 fields[2].out_value = NULL;
129 fields[2].in_value = instructionbus;
130
131 if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
132 {
133 return retval;
134 }
135 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
136
137 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
138 if ((retval = jtag_execute_queue()) != ERROR_OK)
139 {
140 return retval;
141 }
142
143 fields[0].in_value = NULL;
144 fields[0].out_value = databus;
145 fields[1].in_value = NULL;
146 fields[1].out_value = &debug_reason;
147 fields[2].in_value = NULL;
148 fields[2].out_value = instructionbus;
149
150 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
151
152 if (debug_reason & 0x4)
153 if (debug_reason & 0x2)
154 target->debug_reason = DBG_REASON_WPTANDBKPT;
155 else
156 target->debug_reason = DBG_REASON_WATCHPOINT;
157 else
158 target->debug_reason = DBG_REASON_BREAKPOINT;
159 }
160
161 return ERROR_OK;
162 }
163
164 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
165 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
166 {
167 int retval = ERROR_OK;
168 scan_field_t fields[3];
169 uint8_t out_buf[4];
170 uint8_t instr_buf[4];
171 uint8_t sysspeed_buf = 0x0;
172
173 /* prepare buffer */
174 buf_set_u32(out_buf, 0, 32, out);
175
176 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
177
178 if (sysspeed)
179 buf_set_u32(&sysspeed_buf, 2, 1, 1);
180
181 jtag_set_end_state(TAP_DRPAUSE);
182 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
183 {
184 return retval;
185 }
186
187 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
188
189 fields[0].tap = jtag_info->tap;
190 fields[0].num_bits = 32;
191 fields[0].out_value = out_buf;
192 fields[0].in_value = NULL;
193
194 fields[1].tap = jtag_info->tap;
195 fields[1].num_bits = 3;
196 fields[1].out_value = &sysspeed_buf;
197 fields[1].in_value = NULL;
198
199 fields[2].tap = jtag_info->tap;
200 fields[2].num_bits = 32;
201 fields[2].out_value = instr_buf;
202 fields[2].in_value = NULL;
203
204 if (in)
205 {
206 fields[0].in_value=(uint8_t *)in;
207 jtag_add_dr_scan(3, fields, jtag_get_end_state());
208
209 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
210 }
211 else
212 {
213 jtag_add_dr_scan(3, fields, jtag_get_end_state());
214 }
215
216 jtag_add_runtest(0, jtag_get_end_state());
217
218 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
219 {
220 if ((retval = jtag_execute_queue()) != ERROR_OK)
221 {
222 return retval;
223 }
224
225 if (in)
226 {
227 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
228 }
229 else
230 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
231 }
232 #endif
233
234 return ERROR_OK;
235 }
236
237 /* just read data (instruction and data-out = don't care) */
238 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
239 {
240 int retval = ERROR_OK;;
241 scan_field_t fields[3];
242
243 jtag_set_end_state(TAP_DRPAUSE);
244 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
245 {
246 return retval;
247 }
248
249 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
250
251 fields[0].tap = jtag_info->tap;
252 fields[0].num_bits = 32;
253 fields[0].out_value = NULL;
254 fields[0].in_value = (uint8_t *)in;
255
256 fields[1].tap = jtag_info->tap;
257 fields[1].num_bits = 3;
258 fields[1].out_value = NULL;
259 fields[1].in_value = NULL;
260
261 fields[2].tap = jtag_info->tap;
262 fields[2].num_bits = 32;
263 fields[2].out_value = NULL;
264 fields[2].in_value = NULL;
265
266 jtag_add_dr_scan(3, fields, jtag_get_end_state());
267
268 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
269
270 jtag_add_runtest(0, jtag_get_end_state());
271
272 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
273 {
274 if ((retval = jtag_execute_queue()) != ERROR_OK)
275 {
276 return retval;
277 }
278
279 if (in)
280 {
281 LOG_DEBUG("in: 0x%8.8x", *in);
282 }
283 else
284 {
285 LOG_ERROR("BUG: called with in == NULL");
286 }
287 }
288 #endif
289
290 return ERROR_OK;
291 }
292
293 extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
294
295 static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
296 {
297 uint8_t *in=(uint8_t *)arg;
298 arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0);
299 return ERROR_OK;
300 }
301
302 /* clock the target, and read the databus
303 * the *in pointer points to a buffer where elements of 'size' bytes
304 * are stored in big (be==1) or little (be==0) endianness
305 */
306 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
307 {
308 int retval = ERROR_OK;
309 scan_field_t fields[3];
310
311 jtag_set_end_state(TAP_DRPAUSE);
312 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
313 {
314 return retval;
315 }
316
317 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
318
319 fields[0].tap = jtag_info->tap;
320 fields[0].num_bits = 32;
321 fields[0].out_value = NULL;
322 jtag_alloc_in_value32(&fields[0]);
323
324 fields[1].tap = jtag_info->tap;
325 fields[1].num_bits = 3;
326 fields[1].out_value = NULL;
327 fields[1].in_value = NULL;
328
329 fields[2].tap = jtag_info->tap;
330 fields[2].num_bits = 32;
331 fields[2].out_value = NULL;
332 fields[2].in_value = NULL;
333
334 jtag_add_dr_scan(3, fields, jtag_get_end_state());
335
336 jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
337
338 jtag_add_runtest(0, jtag_get_end_state());
339
340 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
341 {
342 if ((retval = jtag_execute_queue()) != ERROR_OK)
343 {
344 return retval;
345 }
346
347 if (in)
348 {
349 LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
350 }
351 else
352 {
353 LOG_ERROR("BUG: called with in == NULL");
354 }
355 }
356 #endif
357
358 return ERROR_OK;
359 }
360
361 void arm9tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
362 {
363 int retval = ERROR_OK;
364 /* get pointers to arch-specific information */
365 armv4_5_common_t *armv4_5 = target->arch_info;
366 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
367 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
368
369 /* save r0 before using it and put system in ARM state
370 * to allow common handling of ARM and THUMB debugging */
371
372 /* fetch STR r0, [r0] */
373 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
374 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
375 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
376 /* STR r0, [r0] in Memory */
377 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
378
379 /* MOV r0, r15 fetched, STR in Decode */
380 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
381 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
382 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
383 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
384 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
385 /* nothing fetched, STR r0, [r0] in Memory */
386 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
387
388 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
389 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
390 /* LDR in Decode */
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
392 /* LDR in Execute */
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
394 /* LDR in Memory (to account for interlock) */
395 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
396
397 /* fetch BX */
398 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
399 /* NOP fetched, BX in Decode, MOV in Execute */
400 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
401 /* NOP fetched, BX in Execute (1) */
402 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
403
404 if ((retval = jtag_execute_queue()) != ERROR_OK)
405 {
406 return;
407 }
408
409 /* fix program counter:
410 * MOV r0, r15 was the 5th instruction (+8)
411 * reading PC in Thumb state gives address of instruction + 4
412 */
413 *pc -= 0xc;
414 }
415
416 void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
417 {
418 int i;
419 /* get pointers to arch-specific information */
420 armv4_5_common_t *armv4_5 = target->arch_info;
421 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
422 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
423
424 /* STMIA r0-15, [r0] at debug speed
425 * register values will start to appear on 4th DCLK
426 */
427 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
428
429 /* fetch NOP, STM in DECODE stage */
430 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
431 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
432 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
433
434 for (i = 0; i <= 15; i++)
435 {
436 if (mask & (1 << i))
437 /* nothing fetched, STM in MEMORY (i'th cycle) */
438 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
439 }
440 }
441
442 void arm9tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
443 {
444 int i;
445 /* get pointers to arch-specific information */
446 armv4_5_common_t *armv4_5 = target->arch_info;
447 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
448 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
449 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
450 uint32_t *buf_u32 = buffer;
451 uint16_t *buf_u16 = buffer;
452 uint8_t *buf_u8 = buffer;
453
454 /* STMIA r0-15, [r0] at debug speed
455 * register values will start to appear on 4th DCLK
456 */
457 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
458
459 /* fetch NOP, STM in DECODE stage */
460 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
461 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
462 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
463
464 for (i = 0; i <= 15; i++)
465 {
466 if (mask & (1 << i))
467 /* nothing fetched, STM in MEMORY (i'th cycle) */
468 switch (size)
469 {
470 case 4:
471 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
472 break;
473 case 2:
474 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
475 break;
476 case 1:
477 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
478 break;
479 }
480 }
481 }
482
483 void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
484 {
485 /* get pointers to arch-specific information */
486 armv4_5_common_t *armv4_5 = target->arch_info;
487 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
488 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
489
490 /* MRS r0, cpsr */
491 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
492 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
493 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
494 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
495 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
496
497 /* STR r0, [r15] */
498 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
499 /* fetch NOP, STR in DECODE stage */
500 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
501 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
503 /* nothing fetched, STR in MEMORY */
504 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
505 }
506
507 void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
508 {
509 /* get pointers to arch-specific information */
510 armv4_5_common_t *armv4_5 = target->arch_info;
511 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
512 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
513
514 LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
515
516 /* MSR1 fetched */
517 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
518 /* MSR2 fetched, MSR1 in DECODE */
519 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
520 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
521 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
522 /* nothing fetched, MSR1 in EXECUTE (2) */
523 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
524 /* nothing fetched, MSR1 in EXECUTE (3) */
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
526 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
528 /* nothing fetched, MSR2 in EXECUTE (2) */
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
530 /* nothing fetched, MSR2 in EXECUTE (3) */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 /* nothing fetched, MSR3 in EXECUTE (2) */
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
536 /* nothing fetched, MSR3 in EXECUTE (3) */
537 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
538 /* NOP fetched, MSR4 in EXECUTE (1) */
539 /* last MSR writes flags, which takes only one cycle */
540 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
541 }
542
543 void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
544 {
545 /* get pointers to arch-specific information */
546 armv4_5_common_t *armv4_5 = target->arch_info;
547 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
548 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
549
550 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
551
552 /* MSR fetched */
553 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
554 /* NOP fetched, MSR in DECODE */
555 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
556 /* NOP fetched, MSR in EXECUTE (1) */
557 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
558
559 /* rot == 4 writes flags, which takes only one cycle */
560 if (rot != 4)
561 {
562 /* nothing fetched, MSR in EXECUTE (2) */
563 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
564 /* nothing fetched, MSR in EXECUTE (3) */
565 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
566 }
567 }
568
569 void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
570 {
571 int i;
572 /* get pointers to arch-specific information */
573 armv4_5_common_t *armv4_5 = target->arch_info;
574 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
575 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
576
577 /* LDMIA r0-15, [r0] at debug speed
578 * register values will start to appear on 4th DCLK
579 */
580 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
581
582 /* fetch NOP, LDM in DECODE stage */
583 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
584 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
585 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
586
587 for (i = 0; i <= 15; i++)
588 {
589 if (mask & (1 << i))
590 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
591 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
592 }
593 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
594 }
595
596 void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
597 {
598 /* get pointers to arch-specific information */
599 armv4_5_common_t *armv4_5 = target->arch_info;
600 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
601 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
602
603 /* put system-speed load-multiple into the pipeline */
604 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
605 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
606 }
607
608 void arm9tdmi_load_hword_reg(target_t *target, int num)
609 {
610 /* get pointers to arch-specific information */
611 armv4_5_common_t *armv4_5 = target->arch_info;
612 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
613 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
614
615 /* put system-speed load half-word into the pipeline */
616 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
617 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
618 }
619
620 void arm9tdmi_load_byte_reg(target_t *target, int num)
621 {
622 /* get pointers to arch-specific information */
623 armv4_5_common_t *armv4_5 = target->arch_info;
624 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
625 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
626
627 /* put system-speed load byte into the pipeline */
628 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
629 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
630 }
631
632 void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
633 {
634 /* get pointers to arch-specific information */
635 armv4_5_common_t *armv4_5 = target->arch_info;
636 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
637 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
638
639 /* put system-speed store-multiple into the pipeline */
640 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
641 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
642 }
643
644 void arm9tdmi_store_hword_reg(target_t *target, int num)
645 {
646 /* get pointers to arch-specific information */
647 armv4_5_common_t *armv4_5 = target->arch_info;
648 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
649 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
650
651 /* put system-speed store half-word into the pipeline */
652 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
653 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
654 }
655
656 void arm9tdmi_store_byte_reg(target_t *target, int num)
657 {
658 /* get pointers to arch-specific information */
659 armv4_5_common_t *armv4_5 = target->arch_info;
660 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
661 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
662
663 /* put system-speed store byte into the pipeline */
664 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
665 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
666 }
667
668 void arm9tdmi_write_pc(target_t *target, uint32_t pc)
669 {
670 /* get pointers to arch-specific information */
671 armv4_5_common_t *armv4_5 = target->arch_info;
672 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
673 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
674
675 /* LDMIA r0-15, [r0] at debug speed
676 * register values will start to appear on 4th DCLK
677 */
678 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
679
680 /* fetch NOP, LDM in DECODE stage */
681 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
682 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
683 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
684 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
685 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
686 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
687 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
688 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
689 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
690 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
691 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
692 }
693
694 void arm9tdmi_branch_resume(target_t *target)
695 {
696 /* get pointers to arch-specific information */
697 armv4_5_common_t *armv4_5 = target->arch_info;
698 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
699 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
700
701 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
702 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
703 }
704
705 void arm9tdmi_branch_resume_thumb(target_t *target)
706 {
707 LOG_DEBUG("-");
708
709 /* get pointers to arch-specific information */
710 armv4_5_common_t *armv4_5 = target->arch_info;
711 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
712 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
713 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
714
715 /* LDMIA r0-15, [r0] at debug speed
716 * register values will start to appear on 4th DCLK
717 */
718 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
719
720 /* fetch NOP, LDM in DECODE stage */
721 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
722 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
723 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
724 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
725 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
726 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
727 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
728
729 /* Branch and eXchange */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
731
732 embeddedice_read_reg(dbg_stat);
733
734 /* fetch NOP, BX in DECODE stage */
735 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
736
737 embeddedice_read_reg(dbg_stat);
738
739 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
740 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
741
742 /* target is now in Thumb state */
743 embeddedice_read_reg(dbg_stat);
744
745 /* load r0 value, MOV_IM in Decode*/
746 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
747 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
748 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
749 /* fetch NOP, LDR in Execute */
750 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
751 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
752 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
753 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
754 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
755
756 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
757 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
758
759 embeddedice_read_reg(dbg_stat);
760
761 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
762 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
763 }
764
765 void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
766 {
767 /* get pointers to arch-specific information */
768 armv4_5_common_t *armv4_5 = target->arch_info;
769 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
770
771 if (arm7_9->has_single_step)
772 {
773 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
774 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
775 }
776 else
777 {
778 arm7_9_enable_eice_step(target, next_pc);
779 }
780 }
781
782 void arm9tdmi_disable_single_step(target_t *target)
783 {
784 /* get pointers to arch-specific information */
785 armv4_5_common_t *armv4_5 = target->arch_info;
786 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
787
788 if (arm7_9->has_single_step)
789 {
790 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
791 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
792 }
793 else
794 {
795 arm7_9_disable_eice_step(target);
796 }
797 }
798
799 void arm9tdmi_build_reg_cache(target_t *target)
800 {
801 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
802 /* get pointers to arch-specific information */
803 armv4_5_common_t *armv4_5 = target->arch_info;
804
805 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
806 armv4_5->core_cache = (*cache_p);
807 }
808
809 int arm9tdmi_examine(struct target_s *target)
810 {
811 /* get pointers to arch-specific information */
812 int retval;
813 armv4_5_common_t *armv4_5 = target->arch_info;
814 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
815 if (!target_was_examined(target))
816 {
817 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
818 reg_cache_t *t;
819 /* one extra register (vector catch) */
820 t=embeddedice_build_reg_cache(target, arm7_9);
821 if (t==NULL)
822 return ERROR_FAIL;
823 (*cache_p) = t;
824 arm7_9->eice_cache = (*cache_p);
825
826 if (arm7_9->etm_ctx)
827 {
828 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
829 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
830 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
831 }
832 target_set_examined(target);
833 }
834 if ((retval=embeddedice_setup(target)) != ERROR_OK)
835 return retval;
836 if ((retval=arm7_9_setup(target)) != ERROR_OK)
837 return retval;
838 if (arm7_9->etm_ctx)
839 {
840 if ((retval=etm_setup(target)) != ERROR_OK)
841 return retval;
842 }
843 return ERROR_OK;
844 }
845
846 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
847 {
848
849 arm9tdmi_build_reg_cache(target);
850
851 return ERROR_OK;
852 }
853
854 int arm9tdmi_quit(void)
855 {
856 return ERROR_OK;
857 }
858
859 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
860 {
861 armv4_5_common_t *armv4_5;
862 arm7_9_common_t *arm7_9;
863
864 arm7_9 = &arm9tdmi->arm7_9_common;
865 armv4_5 = &arm7_9->armv4_5_common;
866
867 /* prepare JTAG information for the new target */
868 arm7_9->jtag_info.tap = tap;
869 arm7_9->jtag_info.scann_size = 5;
870
871 /* register arch-specific functions */
872 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
873 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
874 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
875 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
876 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
877
878 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
879 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
880 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
881
882 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
883 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
884 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
885
886 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
887 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
888 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
889
890 arm7_9->write_pc = arm9tdmi_write_pc;
891 arm7_9->branch_resume = arm9tdmi_branch_resume;
892 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
893
894 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
895 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
896
897 arm7_9->pre_debug_entry = NULL;
898 arm7_9->post_debug_entry = NULL;
899
900 arm7_9->pre_restore_context = NULL;
901 arm7_9->post_restore_context = NULL;
902
903 /* initialize arch-specific breakpoint handling */
904 arm7_9->arm_bkpt = 0xdeeedeee;
905 arm7_9->thumb_bkpt = 0xdeee;
906
907 arm7_9->dbgreq_adjust_pc = 3;
908 arm7_9->arch_info = arm9tdmi;
909
910 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
911 arm9tdmi->arch_info = NULL;
912
913 arm7_9_init_arch_info(target, arm7_9);
914
915 /* override use of DBGRQ, this is safe on ARM9TDMI */
916 arm7_9->use_dbgrq = 1;
917
918 /* all ARM9s have the vector catch register */
919 arm7_9->has_vector_catch = 1;
920
921 return ERROR_OK;
922 }
923
924 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
925 {
926 armv4_5_common_t *armv4_5 = target->arch_info;
927 arm7_9_common_t *arm7_9;
928 arm9tdmi_common_t *arm9tdmi;
929
930 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
931 {
932 return -1;
933 }
934
935 arm7_9 = armv4_5->arch_info;
936 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
937 {
938 return -1;
939 }
940
941 arm9tdmi = arm7_9->arch_info;
942 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
943 {
944 return -1;
945 }
946
947 *armv4_5_p = armv4_5;
948 *arm7_9_p = arm7_9;
949 *arm9tdmi_p = arm9tdmi;
950
951 return ERROR_OK;
952 }
953
954 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
955 {
956 arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
957
958 arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
959
960 return ERROR_OK;
961 }
962
963 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
964 {
965 int retval;
966 command_t *arm9tdmi_cmd;
967
968 retval = arm7_9_register_commands(cmd_ctx);
969 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
970 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
971
972 return retval;
973 }
974
975 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
976 {
977 target_t *target = get_current_target(cmd_ctx);
978 armv4_5_common_t *armv4_5;
979 arm7_9_common_t *arm7_9;
980 arm9tdmi_common_t *arm9tdmi;
981 reg_t *vector_catch;
982 uint32_t vector_catch_value;
983 int i, j;
984
985 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
986 {
987 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
988 return ERROR_OK;
989 }
990
991 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
992
993 /* read the vector catch register if necessary */
994 if (!vector_catch->valid)
995 embeddedice_read_reg(vector_catch);
996
997 /* get the current setting */
998 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
999
1000 if (argc > 0)
1001 {
1002 vector_catch_value = 0x0;
1003 if (strcmp(args[0], "all") == 0)
1004 {
1005 vector_catch_value = 0xdf;
1006 }
1007 else if (strcmp(args[0], "none") == 0)
1008 {
1009 /* do nothing */
1010 }
1011 else
1012 {
1013 for (i = 0; i < argc; i++)
1014 {
1015 /* go through list of vectors */
1016 for (j = 0; arm9tdmi_vectors[j].name; j++)
1017 {
1018 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1019 {
1020 vector_catch_value |= arm9tdmi_vectors[j].value;
1021 break;
1022 }
1023 }
1024
1025 /* complain if vector wasn't found */
1026 if (!arm9tdmi_vectors[j].name)
1027 {
1028 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1029
1030 /* reread current setting */
1031 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1032
1033 break;
1034 }
1035 }
1036 }
1037
1038 /* store new settings */
1039 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1040 embeddedice_store_reg(vector_catch);
1041 }
1042
1043 /* output current settings (skip RESERVED vector) */
1044 for (i = 0; i < 8; i++)
1045 {
1046 if (i != 5)
1047 {
1048 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1049 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1050 }
1051 }
1052
1053 return ERROR_OK;
1054 }
Official OpenOCD Mirror