1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2007 by Dominic Rath <Dominic.Rath@gmx.de> *
5 * Copyright (C) 2009 Zachary T Welch <zw@superlucidity.net> *
7 * Partially based on linux/include/linux/mtd/nand.h *
8 * Copyright (C) 2000 David Woodhouse <dwmw2@mvhi.com> *
9 * Copyright (C) 2000 Steven J. Hill <sjhill@realitydiluted.com> *
10 * Copyright (C) 2000 Thomas Gleixner <tglx@linutronix.de> *
11 ***************************************************************************/
13 #ifndef OPENOCD_FLASH_NAND_CORE_H
14 #define OPENOCD_FLASH_NAND_CORE_H
16 #include <flash/common.h>
19 * Representation of a single NAND block in a NAND device.
22 /** Offset to the block. */
25 /** Size of the block. */
28 /** True if the block has been erased. */
31 /** True if the block is bad. */
40 struct nand_ecclayout
{
44 struct nand_oobfree oobfree
[2];
49 struct target
*target
;
50 struct nand_flash_controller
*controller
;
51 void *controller_priv
;
52 struct nand_manufacturer
*manufacturer
;
53 struct nand_info
*device
;
60 struct nand_block
*blocks
;
61 struct nand_device
*next
;
64 /* NAND Flash Manufacturer ID Codes
67 NAND_MFR_TOSHIBA
= 0x98,
68 NAND_MFR_SAMSUNG
= 0xec,
69 NAND_MFR_FUJITSU
= 0x04,
70 NAND_MFR_NATIONAL
= 0x8f,
71 NAND_MFR_RENESAS
= 0x07,
72 NAND_MFR_STMICRO
= 0x20,
73 NAND_MFR_HYNIX
= 0xad,
74 NAND_MFR_MICRON
= 0x2c,
77 struct nand_manufacturer
{
92 /* Option constants for bizarre dysfunctionality and real features
95 /* Chip can not auto increment pages */
96 NAND_NO_AUTOINCR
= 0x00000001,
98 /* Buswitdh is 16 bit */
99 NAND_BUSWIDTH_16
= 0x00000002,
101 /* Device supports partial programming without padding */
102 NAND_NO_PADDING
= 0x00000004,
104 /* Chip has cache program function */
105 NAND_CACHEPRG
= 0x00000008,
107 /* Chip has copy back function */
108 NAND_COPYBACK
= 0x00000010,
110 /* AND Chip which has 4 banks and a confusing page / block
111 * assignment. See Renesas datasheet for further information */
112 NAND_IS_AND
= 0x00000020,
114 /* Chip has a array of 4 pages which can be read without
115 * additional ready /busy waits */
116 NAND_4PAGE_ARRAY
= 0x00000040,
118 /* Chip requires that BBT is periodically rewritten to prevent
119 * bits from adjacent blocks from 'leaking' in altering data.
120 * This happens with the Renesas AG-AND chips, possibly others. */
121 BBT_AUTO_REFRESH
= 0x00000080,
123 /* Chip does not require ready check on read. True
124 * for all large page devices, as they do not support
126 NAND_NO_READRDY
= 0x00000100,
128 /* Options valid for Samsung large page devices */
129 NAND_SAMSUNG_LP_OPTIONS
= (NAND_NO_PADDING
| NAND_CACHEPRG
| NAND_COPYBACK
),
131 /* Options for new chips with large page size. The pagesize and the
132 * erasesize is determined from the extended id bytes
134 LP_OPTIONS
= (NAND_SAMSUNG_LP_OPTIONS
| NAND_NO_READRDY
| NAND_NO_AUTOINCR
),
135 LP_OPTIONS16
= (LP_OPTIONS
| NAND_BUSWIDTH_16
),
139 /* Standard NAND flash commands */
140 NAND_CMD_READ0
= 0x0,
141 NAND_CMD_READ1
= 0x1,
142 NAND_CMD_RNDOUT
= 0x5,
143 NAND_CMD_PAGEPROG
= 0x10,
144 NAND_CMD_READOOB
= 0x50,
145 NAND_CMD_ERASE1
= 0x60,
146 NAND_CMD_STATUS
= 0x70,
147 NAND_CMD_STATUS_MULTI
= 0x71,
148 NAND_CMD_SEQIN
= 0x80,
149 NAND_CMD_RNDIN
= 0x85,
150 NAND_CMD_READID
= 0x90,
151 NAND_CMD_ERASE2
= 0xd0,
152 NAND_CMD_RESET
= 0xff,
154 /* Extended commands for large page devices */
155 NAND_CMD_READSTART
= 0x30,
156 NAND_CMD_RNDOUTSTART
= 0xE0,
157 NAND_CMD_CACHEDPROG
= 0x15,
162 NAND_STATUS_FAIL
= 0x01,
163 NAND_STATUS_FAIL_N1
= 0x02,
164 NAND_STATUS_TRUE_READY
= 0x20,
165 NAND_STATUS_READY
= 0x40,
166 NAND_STATUS_WP
= 0x80,
169 /* OOB (spare) data formats */
171 NAND_OOB_NONE
= 0x0, /* no OOB data at all */
172 NAND_OOB_RAW
= 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for
173 *2048b page sizes) */
174 NAND_OOB_ONLY
= 0x2, /* only OOB data */
175 NAND_OOB_SW_ECC
= 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
176 NAND_OOB_HW_ECC
= 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
177 NAND_OOB_SW_ECC_KW
= 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
178 NAND_OOB_JFFS2
= 0x100, /* when writing, use JFFS2 OOB layout */
179 NAND_OOB_YAFFS2
= 0x100,/* when writing, use YAFFS2 OOB layout */
182 extern struct nand_device
*nand_devices
;
184 struct nand_device
*get_nand_device_by_num(int num
);
186 int nand_page_command(struct nand_device
*nand
, uint32_t page
,
187 uint8_t cmd
, bool oob_only
);
189 int nand_read_data_page(struct nand_device
*nand
, uint8_t *data
, uint32_t size
);
190 int nand_write_data_page(struct nand_device
*nand
,
191 uint8_t *data
, uint32_t size
);
193 int nand_write_finish(struct nand_device
*nand
);
195 int nand_read_page_raw(struct nand_device
*nand
, uint32_t page
,
196 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
);
197 int nand_write_page_raw(struct nand_device
*nand
, uint32_t page
,
198 uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
);
200 int nand_read_status(struct nand_device
*nand
, uint8_t *status
);
202 int nand_calculate_ecc(struct nand_device
*nand
,
203 const uint8_t *dat
, uint8_t *ecc_code
);
204 int nand_calculate_ecc_kw(struct nand_device
*nand
,
205 const uint8_t *dat
, uint8_t *ecc_code
);
206 int nand_correct_data(struct nand_device
*nand
, u_char
*dat
,
207 u_char
*read_ecc
, u_char
*calc_ecc
);
209 int nand_register_commands(struct command_context
*cmd_ctx
);
211 /** helper for parsing a nand device command argument string */
212 COMMAND_HELPER(nand_command_get_device
, unsigned name_index
,
213 struct nand_device
**nand
);
216 #define ERROR_NAND_DEVICE_INVALID (-1100)
217 #define ERROR_NAND_OPERATION_FAILED (-1101)
218 #define ERROR_NAND_OPERATION_TIMEOUT (-1102)
219 #define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
220 #define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
221 #define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
222 #define ERROR_NAND_NO_BUFFER (-1106)
224 #endif /* OPENOCD_FLASH_NAND_CORE_H */