1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # Target configuration for the Samsung 2450 system on chip
4 # Processor : ARM926ejs (wb) rev 0 (v4l)
5 # Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F
8 # FIX!!! what to use here?
14 # Really low clock during reset?
18 if { [info exists CHIPNAME] } {
19 set _CHIPNAME $CHIPNAME
24 if { [info exists ENDIAN] } {
27 # this defaults to a bigendian
31 if { [info exists CPUTAPID] } {
32 set _CPUTAPID $CPUTAPID
34 set _CPUTAPID 0x07926f0f
38 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID
40 set _TARGETNAME $_CHIPNAME.cpu
41 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
43 # FIX!!!!! should this really use srst_pulls_trst?
44 # With srst_pulls_trst "reset halt" will not reset into the
45 # halted mode, but rather "reset run" and then halt the target.
47 # However, without "srst_pulls_trst", then "reset halt" produces weird
49 # WARNING: unknown debug reason: 0x0
50 reset_config trst_and_srst