1 # SPDX-License-Identifier: BSD-3-Clause
2 # Copyright (C) 2022 by NanoXplore, France - all rights reserved
4 # configuration file for NG-Ultra SoC from NanoXplore.
5 # NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA.
10 if { [info exists CHIPNAME] } {
11 set _CHIPNAME $CHIPNAME
16 if { [info exists CHIPCORES] } {
22 set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000}
23 set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000}
25 # Coresight access to the SoC
26 jtag newtap $_CHIPNAME.coresight cpu -irlen 4 -expected-id 0x6BA00477
29 jtag newtap $_CHIPNAME.soc cpu -irlen 7 -expected-id 0xFAAA0555
30 jtag newtap $_CHIPNAME.pmb unknown1 -irlen 5 -expected-id 0xBA20A005
31 jtag newtap $_CHIPNAME.fpga fpga -irlen 4 -ignore-version -ignore-bypass
33 # Create the Coresight DAP
34 dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu
36 for { set _core 0 } { $_core < $_cores } { incr _core } {
37 cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \
38 -baseaddr [lindex $CTIBASE $_core]
39 # Cores are armv8-r but works with aarch64 (since armv8-r not directly supported by openocd yet).
41 target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
42 -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core
44 target create core.$_core aarch64 -dap $_CHIPNAME.coresight.dap \
45 -ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine
49 # Create direct APB and AXI interfaces
50 target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0
51 target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1