1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Configuration script for Cypress PSoC6 family of microcontrollers (CY8C6xxx)
5 # PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share
6 # the same Flash/RAM/MMIO address space.
9 source [find target/swj-dp.tcl]
14 if { [info exists CHIPNAME] } {
15 set _CHIPNAME $CHIPNAME
21 set TARGET $_CHIPNAME.cpu
23 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
24 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
26 # Is CM0 Debugging enabled ?
28 if { [info exists ENABLE_CM0] } {
29 set _ENABLE_CM0 $ENABLE_CM0
34 # Is CM4 Debugging enabled ?
36 if { [info exists ENABLE_CM4] } {
37 set _ENABLE_CM4 $ENABLE_CM4
42 global _WORKAREASIZE_CM0
43 if { [info exists WORKAREASIZE_CM0] } {
44 set _WORKAREASIZE_CM0 $WORKAREASIZE_CM0
46 set _WORKAREASIZE_CM0 0x4000
49 global _WORKAREASIZE_CM4
50 if { [info exists WORKAREASIZE_CM4] } {
51 set _WORKAREASIZE_CM4 $WORKAREASIZE_CM4
53 set _WORKAREASIZE_CM4 0x4000
56 global _WORKAREAADDR_CM0
57 if { [info exists WORKAREAADDR_CM0] } {
58 set _WORKAREAADDR_CM0 $WORKAREAADDR_CM0
60 set _WORKAREAADDR_CM0 0x08000000
63 global _WORKAREAADDR_CM4
64 if { [info exists WORKAREAADDR_CM4] } {
65 set _WORKAREAADDR_CM4 $WORKAREAADDR_CM4
67 set _WORKAREAADDR_CM4 0x08000000
70 proc init_reset { mode } {
79 # Utility to make 'reset halt' work as reset;halt on a target
80 # It does not prevent running code after reset
81 proc psoc6_deassert_post { target } {
82 # PSoC6 cleared AP registers including TAR during reset
83 # Force examine to synchronize OpenOCD target status
89 if { $RESET_MODE ne "run" } {
92 set st [$target curstate]
94 if { $st eq "reset" } {
95 # we assume running state follows
96 # if reset accidentally halts, waiting is useless
97 catch { $target arp_waitstate running 100 }
98 set st [$target curstate]
101 if { $st eq "running" } {
102 echo "$target: Ran after reset and before halt..."
103 if { $target eq "${TARGET}.cm0" } {
104 # Try to cleanly reset whole system
105 # and halt the CM0 at entry point
107 $target arp_waitstate halted 100
115 if { $_ENABLE_CM0 } {
116 target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
117 ${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
119 flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
120 flash bank work_flash_cm0 psoc6 0x14000000 0 0 0 ${TARGET}.cm0
121 flash bank super_flash_user_cm0 psoc6 0x16000800 0 0 0 ${TARGET}.cm0
122 flash bank super_flash_nar_cm0 psoc6 0x16001A00 0 0 0 ${TARGET}.cm0
123 flash bank super_flash_key_cm0 psoc6 0x16005A00 0 0 0 ${TARGET}.cm0
124 flash bank super_flash_toc2_cm0 psoc6 0x16007C00 0 0 0 ${TARGET}.cm0
126 ${TARGET}.cm0 cortex_m reset_config sysresetreq
127 ${TARGET}.cm0 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm0"
130 if { $_ENABLE_CM4 } {
131 target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
132 ${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
134 flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4
135 flash bank work_flash_cm4 psoc6 0x14000000 0 0 0 ${TARGET}.cm4
136 flash bank super_flash_user_cm4 psoc6 0x16000800 0 0 0 ${TARGET}.cm4
137 flash bank super_flash_nar_cm4 psoc6 0x16001A00 0 0 0 ${TARGET}.cm4
138 flash bank super_flash_key_cm4 psoc6 0x16005A00 0 0 0 ${TARGET}.cm4
139 flash bank super_flash_toc2_cm4 psoc6 0x16007C00 0 0 0 ${TARGET}.cm4
141 ${TARGET}.cm4 cortex_m reset_config vectreset
142 ${TARGET}.cm4 configure -event reset-deassert-post "psoc6_deassert_post ${TARGET}.cm4"
145 if { $_ENABLE_CM0 } {
146 # Use CM0+ by default on dual-core devices
147 targets ${TARGET}.cm0
151 jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069