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cortex_m: fix stepping on FPB rev 1
[openocd.git] / src / target / cortex_m.c
blob34a19e741d8683156e86a5d2af2608fc122a77bf
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2006 by Magnus Lundin *
6 * lundin@mlu.mine.nu *
7 * *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 * *
24 * *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
26 * *
27 ***************************************************************************/
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
34 #include "cortex_m.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
38 #include "register.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
42
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
48 *
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
51 * any longer.
52 */
53
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target *target,
56 uint32_t num, uint32_t value);
57 static void cortex_m_dwt_free(struct target *target);
58
59 static int cortexm_dap_read_coreregister_u32(struct target *target,
60 uint32_t *value, int regnum)
61 {
62 struct armv7m_common *armv7m = target_to_armv7m(target);
63 int retval;
64 uint32_t dcrdr;
65
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target->dbg_msg_enabled) {
69 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
70 if (retval != ERROR_OK)
71 return retval;
72 }
73
74 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
75 if (retval != ERROR_OK)
76 return retval;
77
78 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DCRDR, value);
79 if (retval != ERROR_OK)
80 return retval;
81
82 if (target->dbg_msg_enabled) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval == ERROR_OK)
86 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
87 }
88
89 return retval;
90 }
91
92 static int cortexm_dap_write_coreregister_u32(struct target *target,
93 uint32_t value, int regnum)
94 {
95 struct armv7m_common *armv7m = target_to_armv7m(target);
96 int retval;
97 uint32_t dcrdr;
98
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target->dbg_msg_enabled) {
102 retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DCRDR, &dcrdr);
103 if (retval != ERROR_OK)
104 return retval;
105 }
106
107 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, value);
108 if (retval != ERROR_OK)
109 return retval;
110
111 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
112 if (retval != ERROR_OK)
113 return retval;
114
115 if (target->dbg_msg_enabled) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval == ERROR_OK)
119 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
120 }
121
122 return retval;
123 }
124
125 static int cortex_m_write_debug_halt_mask(struct target *target,
126 uint32_t mask_on, uint32_t mask_off)
127 {
128 struct cortex_m_common *cortex_m = target_to_cm(target);
129 struct armv7m_common *armv7m = &cortex_m->armv7m;
130
131 /* mask off status bits */
132 cortex_m->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
133 /* create new register mask */
134 cortex_m->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
135
136 return mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR, cortex_m->dcb_dhcsr);
137 }
138
139 static int cortex_m_clear_halt(struct target *target)
140 {
141 struct cortex_m_common *cortex_m = target_to_cm(target);
142 struct armv7m_common *armv7m = &cortex_m->armv7m;
143 int retval;
144
145 /* clear step if any */
146 cortex_m_write_debug_halt_mask(target, C_HALT, C_STEP);
147
148 /* Read Debug Fault Status Register */
149 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR, &cortex_m->nvic_dfsr);
150 if (retval != ERROR_OK)
151 return retval;
152
153 /* Clear Debug Fault Status */
154 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
155 if (retval != ERROR_OK)
156 return retval;
157 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
158
159 return ERROR_OK;
160 }
161
162 static int cortex_m_single_step_core(struct target *target)
163 {
164 struct cortex_m_common *cortex_m = target_to_cm(target);
165 struct armv7m_common *armv7m = &cortex_m->armv7m;
166 int retval;
167
168 /* Mask interrupts before clearing halt, if not done already. This avoids
169 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
170 * HALT can put the core into an unknown state.
171 */
172 if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
173 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
174 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
175 if (retval != ERROR_OK)
176 return retval;
177 }
178 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
179 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
180 if (retval != ERROR_OK)
181 return retval;
182 LOG_DEBUG(" ");
183
184 /* restore dhcsr reg */
185 cortex_m_clear_halt(target);
186
187 return ERROR_OK;
188 }
189
190 static int cortex_m_enable_fpb(struct target *target)
191 {
192 int retval = target_write_u32(target, FP_CTRL, 3);
193 if (retval != ERROR_OK)
194 return retval;
195
196 /* check the fpb is actually enabled */
197 uint32_t fpctrl;
198 retval = target_read_u32(target, FP_CTRL, &fpctrl);
199 if (retval != ERROR_OK)
200 return retval;
201
202 if (fpctrl & 1)
203 return ERROR_OK;
204
205 return ERROR_FAIL;
206 }
207
208 static int cortex_m_endreset_event(struct target *target)
209 {
210 int i;
211 int retval;
212 uint32_t dcb_demcr;
213 struct cortex_m_common *cortex_m = target_to_cm(target);
214 struct armv7m_common *armv7m = &cortex_m->armv7m;
215 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
216 struct cortex_m_fp_comparator *fp_list = cortex_m->fp_comparator_list;
217 struct cortex_m_dwt_comparator *dwt_list = cortex_m->dwt_comparator_list;
218
219 /* REVISIT The four debug monitor bits are currently ignored... */
220 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
221 if (retval != ERROR_OK)
222 return retval;
223 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
224
225 /* this register is used for emulated dcc channel */
226 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
227 if (retval != ERROR_OK)
228 return retval;
229
230 /* Enable debug requests */
231 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
232 if (retval != ERROR_OK)
233 return retval;
234 if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
235 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
236 if (retval != ERROR_OK)
237 return retval;
238 }
239
240 /* Restore proper interrupt masking setting. */
241 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
242 cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
243 else
244 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
245
246 /* Enable features controlled by ITM and DWT blocks, and catch only
247 * the vectors we were told to pay attention to.
248 *
249 * Target firmware is responsible for all fault handling policy
250 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
251 * or manual updates to the NVIC SHCSR and CCR registers.
252 */
253 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, TRCENA | armv7m->demcr);
254 if (retval != ERROR_OK)
255 return retval;
256
257 /* Paranoia: evidently some (early?) chips don't preserve all the
258 * debug state (including FPB, DWT, etc) across reset...
259 */
260
261 /* Enable FPB */
262 retval = cortex_m_enable_fpb(target);
263 if (retval != ERROR_OK) {
264 LOG_ERROR("Failed to enable the FPB");
265 return retval;
266 }
267
268 cortex_m->fpb_enabled = 1;
269
270 /* Restore FPB registers */
271 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
272 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
273 if (retval != ERROR_OK)
274 return retval;
275 }
276
277 /* Restore DWT registers */
278 for (i = 0; i < cortex_m->dwt_num_comp; i++) {
279 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
280 dwt_list[i].comp);
281 if (retval != ERROR_OK)
282 return retval;
283 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
284 dwt_list[i].mask);
285 if (retval != ERROR_OK)
286 return retval;
287 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
288 dwt_list[i].function);
289 if (retval != ERROR_OK)
290 return retval;
291 }
292 retval = dap_run(swjdp);
293 if (retval != ERROR_OK)
294 return retval;
295
296 register_cache_invalidate(armv7m->arm.core_cache);
297
298 /* make sure we have latest dhcsr flags */
299 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
300
301 return retval;
302 }
303
304 static int cortex_m_examine_debug_reason(struct target *target)
305 {
306 struct cortex_m_common *cortex_m = target_to_cm(target);
307
308 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
309 * only check the debug reason if we don't know it already */
310
311 if ((target->debug_reason != DBG_REASON_DBGRQ)
312 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
313 if (cortex_m->nvic_dfsr & DFSR_BKPT) {
314 target->debug_reason = DBG_REASON_BREAKPOINT;
315 if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
316 target->debug_reason = DBG_REASON_WPTANDBKPT;
317 } else if (cortex_m->nvic_dfsr & DFSR_DWTTRAP)
318 target->debug_reason = DBG_REASON_WATCHPOINT;
319 else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
320 target->debug_reason = DBG_REASON_BREAKPOINT;
321 else /* EXTERNAL, HALTED */
322 target->debug_reason = DBG_REASON_UNDEFINED;
323 }
324
325 return ERROR_OK;
326 }
327
328 static int cortex_m_examine_exception_reason(struct target *target)
329 {
330 uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
331 struct armv7m_common *armv7m = target_to_armv7m(target);
332 struct adiv5_dap *swjdp = armv7m->arm.dap;
333 int retval;
334
335 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SHCSR, &shcsr);
336 if (retval != ERROR_OK)
337 return retval;
338 switch (armv7m->exception_number) {
339 case 2: /* NMI */
340 break;
341 case 3: /* Hard Fault */
342 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr);
343 if (retval != ERROR_OK)
344 return retval;
345 if (except_sr & 0x40000000) {
346 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr);
347 if (retval != ERROR_OK)
348 return retval;
349 }
350 break;
351 case 4: /* Memory Management */
352 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
353 if (retval != ERROR_OK)
354 return retval;
355 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar);
356 if (retval != ERROR_OK)
357 return retval;
358 break;
359 case 5: /* Bus Fault */
360 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
361 if (retval != ERROR_OK)
362 return retval;
363 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar);
364 if (retval != ERROR_OK)
365 return retval;
366 break;
367 case 6: /* Usage Fault */
368 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr);
369 if (retval != ERROR_OK)
370 return retval;
371 break;
372 case 11: /* SVCall */
373 break;
374 case 12: /* Debug Monitor */
375 retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr);
376 if (retval != ERROR_OK)
377 return retval;
378 break;
379 case 14: /* PendSV */
380 break;
381 case 15: /* SysTick */
382 break;
383 default:
384 except_sr = 0;
385 break;
386 }
387 retval = dap_run(swjdp);
388 if (retval == ERROR_OK)
389 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
390 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
391 armv7m_exception_string(armv7m->exception_number),
392 shcsr, except_sr, cfsr, except_ar);
393 return retval;
394 }
395
396 static int cortex_m_debug_entry(struct target *target)
397 {
398 int i;
399 uint32_t xPSR;
400 int retval;
401 struct cortex_m_common *cortex_m = target_to_cm(target);
402 struct armv7m_common *armv7m = &cortex_m->armv7m;
403 struct arm *arm = &armv7m->arm;
404 struct reg *r;
405
406 LOG_DEBUG(" ");
407
408 cortex_m_clear_halt(target);
409 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
410 if (retval != ERROR_OK)
411 return retval;
412
413 retval = armv7m->examine_debug_reason(target);
414 if (retval != ERROR_OK)
415 return retval;
416
417 /* Examine target state and mode
418 * First load register accessible through core debug port */
419 int num_regs = arm->core_cache->num_regs;
420
421 for (i = 0; i < num_regs; i++) {
422 r = &armv7m->arm.core_cache->reg_list[i];
423 if (!r->valid)
424 arm->read_core_reg(target, r, i, ARM_MODE_ANY);
425 }
426
427 r = arm->cpsr;
428 xPSR = buf_get_u32(r->value, 0, 32);
429
430 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
431 if (xPSR & 0xf00) {
432 r->dirty = r->valid;
433 cortex_m_store_core_reg_u32(target, 16, xPSR & ~0xff);
434 }
435
436 /* Are we in an exception handler */
437 if (xPSR & 0x1FF) {
438 armv7m->exception_number = (xPSR & 0x1FF);
439
440 arm->core_mode = ARM_MODE_HANDLER;
441 arm->map = armv7m_msp_reg_map;
442 } else {
443 unsigned control = buf_get_u32(arm->core_cache
444 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
445
446 /* is this thread privileged? */
447 arm->core_mode = control & 1
448 ? ARM_MODE_USER_THREAD
449 : ARM_MODE_THREAD;
450
451 /* which stack is it using? */
452 if (control & 2)
453 arm->map = armv7m_psp_reg_map;
454 else
455 arm->map = armv7m_msp_reg_map;
456
457 armv7m->exception_number = 0;
458 }
459
460 if (armv7m->exception_number)
461 cortex_m_examine_exception_reason(target);
462
463 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
464 arm_mode_name(arm->core_mode),
465 buf_get_u32(arm->pc->value, 0, 32),
466 target_state_name(target));
467
468 if (armv7m->post_debug_entry) {
469 retval = armv7m->post_debug_entry(target);
470 if (retval != ERROR_OK)
471 return retval;
472 }
473
474 return ERROR_OK;
475 }
476
477 static int cortex_m_poll(struct target *target)
478 {
479 int detected_failure = ERROR_OK;
480 int retval = ERROR_OK;
481 enum target_state prev_target_state = target->state;
482 struct cortex_m_common *cortex_m = target_to_cm(target);
483 struct armv7m_common *armv7m = &cortex_m->armv7m;
484
485 /* Read from Debug Halting Control and Status Register */
486 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
487 if (retval != ERROR_OK) {
488 target->state = TARGET_UNKNOWN;
489 return retval;
490 }
491
492 /* Recover from lockup. See ARMv7-M architecture spec,
493 * section B1.5.15 "Unrecoverable exception cases".
494 */
495 if (cortex_m->dcb_dhcsr & S_LOCKUP) {
496 LOG_ERROR("%s -- clearing lockup after double fault",
497 target_name(target));
498 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
499 target->debug_reason = DBG_REASON_DBGRQ;
500
501 /* We have to execute the rest (the "finally" equivalent, but
502 * still throw this exception again).
503 */
504 detected_failure = ERROR_FAIL;
505
506 /* refresh status bits */
507 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
508 if (retval != ERROR_OK)
509 return retval;
510 }
511
512 if (cortex_m->dcb_dhcsr & S_RESET_ST) {
513 if (target->state != TARGET_RESET) {
514 target->state = TARGET_RESET;
515 LOG_INFO("%s: external reset detected", target_name(target));
516 }
517 return ERROR_OK;
518 }
519
520 if (target->state == TARGET_RESET) {
521 /* Cannot switch context while running so endreset is
522 * called with target->state == TARGET_RESET
523 */
524 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
525 cortex_m->dcb_dhcsr);
526 retval = cortex_m_endreset_event(target);
527 if (retval != ERROR_OK) {
528 target->state = TARGET_UNKNOWN;
529 return retval;
530 }
531 target->state = TARGET_RUNNING;
532 prev_target_state = TARGET_RUNNING;
533 }
534
535 if (cortex_m->dcb_dhcsr & S_HALT) {
536 target->state = TARGET_HALTED;
537
538 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
539 retval = cortex_m_debug_entry(target);
540 if (retval != ERROR_OK)
541 return retval;
542
543 if (arm_semihosting(target, &retval) != 0)
544 return retval;
545
546 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
547 }
548 if (prev_target_state == TARGET_DEBUG_RUNNING) {
549 LOG_DEBUG(" ");
550 retval = cortex_m_debug_entry(target);
551 if (retval != ERROR_OK)
552 return retval;
553
554 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
555 }
556 }
557
558 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
559 * How best to model low power modes?
560 */
561
562 if (target->state == TARGET_UNKNOWN) {
563 /* check if processor is retiring instructions */
564 if (cortex_m->dcb_dhcsr & S_RETIRE_ST) {
565 target->state = TARGET_RUNNING;
566 retval = ERROR_OK;
567 }
568 }
569
570 /* Check that target is truly halted, since the target could be resumed externally */
571 if ((prev_target_state == TARGET_HALTED) && !(cortex_m->dcb_dhcsr & S_HALT)) {
572 /* registers are now invalid */
573 register_cache_invalidate(armv7m->arm.core_cache);
574
575 target->state = TARGET_RUNNING;
576 LOG_WARNING("%s: external resume detected", target_name(target));
577 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
578 retval = ERROR_OK;
579 }
580
581 /* Did we detect a failure condition that we cleared? */
582 if (detected_failure != ERROR_OK)
583 retval = detected_failure;
584 return retval;
585 }
586
587 static int cortex_m_halt(struct target *target)
588 {
589 LOG_DEBUG("target->state: %s",
590 target_state_name(target));
591
592 if (target->state == TARGET_HALTED) {
593 LOG_DEBUG("target was already halted");
594 return ERROR_OK;
595 }
596
597 if (target->state == TARGET_UNKNOWN)
598 LOG_WARNING("target was in unknown state when halt was requested");
599
600 if (target->state == TARGET_RESET) {
601 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
602 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
603 return ERROR_TARGET_FAILURE;
604 } else {
605 /* we came here in a reset_halt or reset_init sequence
606 * debug entry was already prepared in cortex_m3_assert_reset()
607 */
608 target->debug_reason = DBG_REASON_DBGRQ;
609
610 return ERROR_OK;
611 }
612 }
613
614 /* Write to Debug Halting Control and Status Register */
615 cortex_m_write_debug_halt_mask(target, C_HALT, 0);
616
617 target->debug_reason = DBG_REASON_DBGRQ;
618
619 return ERROR_OK;
620 }
621
622 static int cortex_m_soft_reset_halt(struct target *target)
623 {
624 struct cortex_m_common *cortex_m = target_to_cm(target);
625 struct armv7m_common *armv7m = &cortex_m->armv7m;
626 uint32_t dcb_dhcsr = 0;
627 int retval, timeout = 0;
628
629 /* soft_reset_halt is deprecated on cortex_m as the same functionality
630 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
631 * As this reset only used VC_CORERESET it would only ever reset the cortex_m
632 * core, not the peripherals */
633 LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
634
635 /* Enter debug state on reset; restore DEMCR in endreset_event() */
636 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
637 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
638 if (retval != ERROR_OK)
639 return retval;
640
641 /* Request a core-only reset */
642 retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
643 AIRCR_VECTKEY | AIRCR_VECTRESET);
644 if (retval != ERROR_OK)
645 return retval;
646 target->state = TARGET_RESET;
647
648 /* registers are now invalid */
649 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
650
651 while (timeout < 100) {
652 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
653 if (retval == ERROR_OK) {
654 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
655 &cortex_m->nvic_dfsr);
656 if (retval != ERROR_OK)
657 return retval;
658 if ((dcb_dhcsr & S_HALT)
659 && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
660 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
661 "DFSR 0x%08x",
662 (unsigned) dcb_dhcsr,
663 (unsigned) cortex_m->nvic_dfsr);
664 cortex_m_poll(target);
665 /* FIXME restore user's vector catch config */
666 return ERROR_OK;
667 } else
668 LOG_DEBUG("waiting for system reset-halt, "
669 "DHCSR 0x%08x, %d ms",
670 (unsigned) dcb_dhcsr, timeout);
671 }
672 timeout++;
673 alive_sleep(1);
674 }
675
676 return ERROR_OK;
677 }
678
679 void cortex_m_enable_breakpoints(struct target *target)
680 {
681 struct breakpoint *breakpoint = target->breakpoints;
682
683 /* set any pending breakpoints */
684 while (breakpoint) {
685 if (!breakpoint->set)
686 cortex_m_set_breakpoint(target, breakpoint);
687 breakpoint = breakpoint->next;
688 }
689 }
690
691 static int cortex_m_resume(struct target *target, int current,
692 target_addr_t address, int handle_breakpoints, int debug_execution)
693 {
694 struct armv7m_common *armv7m = target_to_armv7m(target);
695 struct breakpoint *breakpoint = NULL;
696 uint32_t resume_pc;
697 struct reg *r;
698
699 if (target->state != TARGET_HALTED) {
700 LOG_WARNING("target not halted");
701 return ERROR_TARGET_NOT_HALTED;
702 }
703
704 if (!debug_execution) {
705 target_free_all_working_areas(target);
706 cortex_m_enable_breakpoints(target);
707 cortex_m_enable_watchpoints(target);
708 }
709
710 if (debug_execution) {
711 r = armv7m->arm.core_cache->reg_list + ARMV7M_PRIMASK;
712
713 /* Disable interrupts */
714 /* We disable interrupts in the PRIMASK register instead of
715 * masking with C_MASKINTS. This is probably the same issue
716 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
717 * in parallel with disabled interrupts can cause local faults
718 * to not be taken.
719 *
720 * REVISIT this clearly breaks non-debug execution, since the
721 * PRIMASK register state isn't saved/restored... workaround
722 * by never resuming app code after debug execution.
723 */
724 buf_set_u32(r->value, 0, 1, 1);
725 r->dirty = true;
726 r->valid = true;
727
728 /* Make sure we are in Thumb mode */
729 r = armv7m->arm.cpsr;
730 buf_set_u32(r->value, 24, 1, 1);
731 r->dirty = true;
732 r->valid = true;
733 }
734
735 /* current = 1: continue on current pc, otherwise continue at <address> */
736 r = armv7m->arm.pc;
737 if (!current) {
738 buf_set_u32(r->value, 0, 32, address);
739 r->dirty = true;
740 r->valid = true;
741 }
742
743 /* if we halted last time due to a bkpt instruction
744 * then we have to manually step over it, otherwise
745 * the core will break again */
746
747 if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
748 && !debug_execution)
749 armv7m_maybe_skip_bkpt_inst(target, NULL);
750
751 resume_pc = buf_get_u32(r->value, 0, 32);
752
753 armv7m_restore_context(target);
754
755 /* the front-end may request us not to handle breakpoints */
756 if (handle_breakpoints) {
757 /* Single step past breakpoint at current address */
758 breakpoint = breakpoint_find(target, resume_pc);
759 if (breakpoint) {
760 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
761 breakpoint->address,
762 breakpoint->unique_id);
763 cortex_m_unset_breakpoint(target, breakpoint);
764 cortex_m_single_step_core(target);
765 cortex_m_set_breakpoint(target, breakpoint);
766 }
767 }
768
769 /* Restart core */
770 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
771
772 target->debug_reason = DBG_REASON_NOTHALTED;
773
774 /* registers are now invalid */
775 register_cache_invalidate(armv7m->arm.core_cache);
776
777 if (!debug_execution) {
778 target->state = TARGET_RUNNING;
779 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
780 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
781 } else {
782 target->state = TARGET_DEBUG_RUNNING;
783 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
784 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
785 }
786
787 return ERROR_OK;
788 }
789
790 /* int irqstepcount = 0; */
791 static int cortex_m_step(struct target *target, int current,
792 target_addr_t address, int handle_breakpoints)
793 {
794 struct cortex_m_common *cortex_m = target_to_cm(target);
795 struct armv7m_common *armv7m = &cortex_m->armv7m;
796 struct breakpoint *breakpoint = NULL;
797 struct reg *pc = armv7m->arm.pc;
798 bool bkpt_inst_found = false;
799 int retval;
800 bool isr_timed_out = false;
801
802 if (target->state != TARGET_HALTED) {
803 LOG_WARNING("target not halted");
804 return ERROR_TARGET_NOT_HALTED;
805 }
806
807 /* current = 1: continue on current pc, otherwise continue at <address> */
808 if (!current)
809 buf_set_u32(pc->value, 0, 32, address);
810
811 uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
812
813 /* the front-end may request us not to handle breakpoints */
814 if (handle_breakpoints) {
815 breakpoint = breakpoint_find(target, pc_value);
816 if (breakpoint)
817 cortex_m_unset_breakpoint(target, breakpoint);
818 }
819
820 armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
821
822 target->debug_reason = DBG_REASON_SINGLESTEP;
823
824 armv7m_restore_context(target);
825
826 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
827
828 /* if no bkpt instruction is found at pc then we can perform
829 * a normal step, otherwise we have to manually step over the bkpt
830 * instruction - as such simulate a step */
831 if (bkpt_inst_found == false) {
832 /* Automatic ISR masking mode off: Just step over the next instruction */
833 if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO))
834 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
835 else {
836 /* Process interrupts during stepping in a way they don't interfere
837 * debugging.
838 *
839 * Principle:
840 *
841 * Set a temporary break point at the current pc and let the core run
842 * with interrupts enabled. Pending interrupts get served and we run
843 * into the breakpoint again afterwards. Then we step over the next
844 * instruction with interrupts disabled.
845 *
846 * If the pending interrupts don't complete within time, we leave the
847 * core running. This may happen if the interrupts trigger faster
848 * than the core can process them or the handler doesn't return.
849 *
850 * If no more breakpoints are available we simply do a step with
851 * interrupts enabled.
852 *
853 */
854
855 /* 2012-09-29 ph
856 *
857 * If a break point is already set on the lower half word then a break point on
858 * the upper half word will not break again when the core is restarted. So we
859 * just step over the instruction with interrupts disabled.
860 *
861 * The documentation has no information about this, it was found by observation
862 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
863 * suffer from this problem.
864 *
865 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
866 * address has it always cleared. The former is done to indicate thumb mode
867 * to gdb.
868 *
869 */
870 if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
871 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
872 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
873 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
874 /* Re-enable interrupts */
875 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
876 }
877 else {
878
879 /* Set a temporary break point */
880 if (breakpoint) {
881 retval = cortex_m_set_breakpoint(target, breakpoint);
882 } else {
883 enum breakpoint_type type = BKPT_HARD;
884 if (cortex_m->fp_rev == 0 && pc_value > 0x1FFFFFFF) {
885 /* FPB rev.1 cannot handle such addr, try BKPT instr */
886 type = BKPT_SOFT;
887 }
888 retval = breakpoint_add(target, pc_value, 2, type);
889 }
890
891 bool tmp_bp_set = (retval == ERROR_OK);
892
893 /* No more breakpoints left, just do a step */
894 if (!tmp_bp_set)
895 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
896 else {
897 /* Start the core */
898 LOG_DEBUG("Starting core to serve pending interrupts");
899 int64_t t_start = timeval_ms();
900 cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
901
902 /* Wait for pending handlers to complete or timeout */
903 do {
904 retval = mem_ap_read_atomic_u32(armv7m->debug_ap,
905 DCB_DHCSR,
906 &cortex_m->dcb_dhcsr);
907 if (retval != ERROR_OK) {
908 target->state = TARGET_UNKNOWN;
909 return retval;
910 }
911 isr_timed_out = ((timeval_ms() - t_start) > 500);
912 } while (!((cortex_m->dcb_dhcsr & S_HALT) || isr_timed_out));
913
914 /* only remove breakpoint if we created it */
915 if (breakpoint)
916 cortex_m_unset_breakpoint(target, breakpoint);
917 else {
918 /* Remove the temporary breakpoint */
919 breakpoint_remove(target, pc_value);
920 }
921
922 if (isr_timed_out) {
923 LOG_DEBUG("Interrupt handlers didn't complete within time, "
924 "leaving target running");
925 } else {
926 /* Step over next instruction with interrupts disabled */
927 cortex_m_write_debug_halt_mask(target,
928 C_HALT | C_MASKINTS,
929 0);
930 cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
931 /* Re-enable interrupts */
932 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
933 }
934 }
935 }
936 }
937 }
938
939 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
940 if (retval != ERROR_OK)
941 return retval;
942
943 /* registers are now invalid */
944 register_cache_invalidate(armv7m->arm.core_cache);
945
946 if (breakpoint)
947 cortex_m_set_breakpoint(target, breakpoint);
948
949 if (isr_timed_out) {
950 /* Leave the core running. The user has to stop execution manually. */
951 target->debug_reason = DBG_REASON_NOTHALTED;
952 target->state = TARGET_RUNNING;
953 return ERROR_OK;
954 }
955
956 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
957 " nvic_icsr = 0x%" PRIx32,
958 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
959
960 retval = cortex_m_debug_entry(target);
961 if (retval != ERROR_OK)
962 return retval;
963 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
964
965 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
966 " nvic_icsr = 0x%" PRIx32,
967 cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
968
969 return ERROR_OK;
970 }
971
972 static int cortex_m_assert_reset(struct target *target)
973 {
974 struct cortex_m_common *cortex_m = target_to_cm(target);
975 struct armv7m_common *armv7m = &cortex_m->armv7m;
976 enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
977
978 LOG_DEBUG("target->state: %s",
979 target_state_name(target));
980
981 enum reset_types jtag_reset_config = jtag_get_reset_config();
982
983 if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
984 /* allow scripts to override the reset event */
985
986 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
987 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
988 target->state = TARGET_RESET;
989
990 return ERROR_OK;
991 }
992
993 /* some cores support connecting while srst is asserted
994 * use that mode is it has been configured */
995
996 bool srst_asserted = false;
997
998 if (!target_was_examined(target)) {
999 if (jtag_reset_config & RESET_HAS_SRST) {
1000 adapter_assert_reset();
1001 if (target->reset_halt)
1002 LOG_ERROR("Target not examined, will not halt after reset!");
1003 return ERROR_OK;
1004 } else {
1005 LOG_ERROR("Target not examined, reset NOT asserted!");
1006 return ERROR_FAIL;
1007 }
1008 }
1009
1010 if ((jtag_reset_config & RESET_HAS_SRST) &&
1011 (jtag_reset_config & RESET_SRST_NO_GATING)) {
1012 adapter_assert_reset();
1013 srst_asserted = true;
1014 }
1015
1016 /* Enable debug requests */
1017 int retval;
1018 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
1019 /* Store important errors instead of failing and proceed to reset assert */
1020
1021 if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
1022 retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
1023
1024 /* If the processor is sleeping in a WFI or WFE instruction, the
1025 * C_HALT bit must be asserted to regain control */
1026 if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
1027 retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
1028
1029 mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
1030 /* Ignore less important errors */
1031
1032 if (!target->reset_halt) {
1033 /* Set/Clear C_MASKINTS in a separate operation */
1034 if (cortex_m->dcb_dhcsr & C_MASKINTS)
1035 cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
1036
1037 /* clear any debug flags before resuming */
1038 cortex_m_clear_halt(target);
1039
1040 /* clear C_HALT in dhcsr reg */
1041 cortex_m_write_debug_halt_mask(target, 0, C_HALT);
1042 } else {
1043 /* Halt in debug on reset; endreset_event() restores DEMCR.
1044 *
1045 * REVISIT catching BUSERR presumably helps to defend against
1046 * bad vector table entries. Should this include MMERR or
1047 * other flags too?
1048 */
1049 int retval2;
1050 retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
1051 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1052 if (retval != ERROR_OK || retval2 != ERROR_OK)
1053 LOG_INFO("AP write error, reset will not halt");
1054 }
1055
1056 if (jtag_reset_config & RESET_HAS_SRST) {
1057 /* default to asserting srst */
1058 if (!srst_asserted)
1059 adapter_assert_reset();
1060
1061 /* srst is asserted, ignore AP access errors */
1062 retval = ERROR_OK;
1063 } else {
1064 /* Use a standard Cortex-M3 software reset mechanism.
1065 * We default to using VECRESET as it is supported on all current cores
1066 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1067 * This has the disadvantage of not resetting the peripherals, so a
1068 * reset-init event handler is needed to perform any peripheral resets.
1069 */
1070 if (!cortex_m->vectreset_supported
1071 && reset_config == CORTEX_M_RESET_VECTRESET) {
1072 reset_config = CORTEX_M_RESET_SYSRESETREQ;
1073 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1074 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1075 }
1076
1077 LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
1078 ? "SYSRESETREQ" : "VECTRESET");
1079
1080 if (reset_config == CORTEX_M_RESET_VECTRESET) {
1081 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1082 "handler to reset any peripherals or configure hardware srst support.");
1083 }
1084
1085 int retval3;
1086 retval3 = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_AIRCR,
1087 AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
1088 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1089 if (retval3 != ERROR_OK)
1090 LOG_DEBUG("Ignoring AP write error right after reset");
1091
1092 retval3 = dap_dp_init(armv7m->debug_ap->dap);
1093 if (retval3 != ERROR_OK)
1094 LOG_ERROR("DP initialisation failed");
1095
1096 else {
1097 /* I do not know why this is necessary, but it
1098 * fixes strange effects (step/resume cause NMI
1099 * after reset) on LM3S6918 -- Michael Schwingen
1100 */
1101 uint32_t tmp;
1102 mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_AIRCR, &tmp);
1103 }
1104 }
1105
1106 target->state = TARGET_RESET;
1107 jtag_add_sleep(50000);
1108
1109 register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
1110
1111 /* now return stored error code if any */
1112 if (retval != ERROR_OK)
1113 return retval;
1114
1115 if (target->reset_halt) {
1116 retval = target_halt(target);
1117 if (retval != ERROR_OK)
1118 return retval;
1119 }
1120
1121 return ERROR_OK;
1122 }
1123
1124 static int cortex_m_deassert_reset(struct target *target)
1125 {
1126 struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
1127
1128 LOG_DEBUG("target->state: %s",
1129 target_state_name(target));
1130
1131 /* deassert reset lines */
1132 adapter_deassert_reset();
1133
1134 enum reset_types jtag_reset_config = jtag_get_reset_config();
1135
1136 if ((jtag_reset_config & RESET_HAS_SRST) &&
1137 !(jtag_reset_config & RESET_SRST_NO_GATING) &&
1138 target_was_examined(target)) {
1139 int retval = dap_dp_init(armv7m->debug_ap->dap);
1140 if (retval != ERROR_OK) {
1141 LOG_ERROR("DP initialisation failed");
1142 return retval;
1143 }
1144 }
1145
1146 return ERROR_OK;
1147 }
1148
1149 int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1150 {
1151 int retval;
1152 int fp_num = 0;
1153 struct cortex_m_common *cortex_m = target_to_cm(target);
1154 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1155
1156 if (breakpoint->set) {
1157 LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
1158 return ERROR_OK;
1159 }
1160
1161 if (breakpoint->type == BKPT_HARD) {
1162 uint32_t fpcr_value;
1163 while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
1164 fp_num++;
1165 if (fp_num >= cortex_m->fp_num_code) {
1166 LOG_ERROR("Can not find free FPB Comparator!");
1167 return ERROR_FAIL;
1168 }
1169 breakpoint->set = fp_num + 1;
1170 fpcr_value = breakpoint->address | 1;
1171 if (cortex_m->fp_rev == 0) {
1172 if (breakpoint->address > 0x1FFFFFFF) {
1173 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1174 return ERROR_FAIL;
1175 }
1176 uint32_t hilo;
1177 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1178 fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
1179 } else if (cortex_m->fp_rev > 1) {
1180 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1181 return ERROR_FAIL;
1182 }
1183 comparator_list[fp_num].used = 1;
1184 comparator_list[fp_num].fpcr_value = fpcr_value;
1185 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1186 comparator_list[fp_num].fpcr_value);
1187 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1188 fp_num,
1189 comparator_list[fp_num].fpcr_value);
1190 if (!cortex_m->fpb_enabled) {
1191 LOG_DEBUG("FPB wasn't enabled, do it now");
1192 retval = cortex_m_enable_fpb(target);
1193 if (retval != ERROR_OK) {
1194 LOG_ERROR("Failed to enable the FPB");
1195 return retval;
1196 }
1197
1198 cortex_m->fpb_enabled = 1;
1199 }
1200 } else if (breakpoint->type == BKPT_SOFT) {
1201 uint8_t code[4];
1202
1203 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1204 * semihosting; don't use that. Otherwise the BKPT
1205 * parameter is arbitrary.
1206 */
1207 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1208 retval = target_read_memory(target,
1209 breakpoint->address & 0xFFFFFFFE,
1210 breakpoint->length, 1,
1211 breakpoint->orig_instr);
1212 if (retval != ERROR_OK)
1213 return retval;
1214 retval = target_write_memory(target,
1215 breakpoint->address & 0xFFFFFFFE,
1216 breakpoint->length, 1,
1217 code);
1218 if (retval != ERROR_OK)
1219 return retval;
1220 breakpoint->set = true;
1221 }
1222
1223 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1224 breakpoint->unique_id,
1225 (int)(breakpoint->type),
1226 breakpoint->address,
1227 breakpoint->length,
1228 breakpoint->set);
1229
1230 return ERROR_OK;
1231 }
1232
1233 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1234 {
1235 int retval;
1236 struct cortex_m_common *cortex_m = target_to_cm(target);
1237 struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
1238
1239 if (!breakpoint->set) {
1240 LOG_WARNING("breakpoint not set");
1241 return ERROR_OK;
1242 }
1243
1244 LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
1245 breakpoint->unique_id,
1246 (int)(breakpoint->type),
1247 breakpoint->address,
1248 breakpoint->length,
1249 breakpoint->set);
1250
1251 if (breakpoint->type == BKPT_HARD) {
1252 int fp_num = breakpoint->set - 1;
1253 if ((fp_num < 0) || (fp_num >= cortex_m->fp_num_code)) {
1254 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1255 return ERROR_OK;
1256 }
1257 comparator_list[fp_num].used = 0;
1258 comparator_list[fp_num].fpcr_value = 0;
1259 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1260 comparator_list[fp_num].fpcr_value);
1261 } else {
1262 /* restore original instruction (kept in target endianness) */
1263 if (breakpoint->length == 4) {
1264 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1265 breakpoint->orig_instr);
1266 if (retval != ERROR_OK)
1267 return retval;
1268 } else {
1269 retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1270 breakpoint->orig_instr);
1271 if (retval != ERROR_OK)
1272 return retval;
1273 }
1274 }
1275 breakpoint->set = false;
1276
1277 return ERROR_OK;
1278 }
1279
1280 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1281 {
1282 struct cortex_m_common *cortex_m = target_to_cm(target);
1283
1284 if ((breakpoint->type == BKPT_HARD) && (cortex_m->fp_code_available < 1)) {
1285 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1286 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1287 }
1288
1289 if (breakpoint->length == 3) {
1290 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1291 breakpoint->length = 2;
1292 }
1293
1294 if ((breakpoint->length != 2)) {
1295 LOG_INFO("only breakpoints of two bytes length supported");
1296 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1297 }
1298
1299 if (breakpoint->type == BKPT_HARD)
1300 cortex_m->fp_code_available--;
1301
1302 return cortex_m_set_breakpoint(target, breakpoint);
1303 }
1304
1305 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1306 {
1307 struct cortex_m_common *cortex_m = target_to_cm(target);
1308
1309 /* REVISIT why check? FPB can be updated with core running ... */
1310 if (target->state != TARGET_HALTED) {
1311 LOG_WARNING("target not halted");
1312 return ERROR_TARGET_NOT_HALTED;
1313 }
1314
1315 if (breakpoint->set)
1316 cortex_m_unset_breakpoint(target, breakpoint);
1317
1318 if (breakpoint->type == BKPT_HARD)
1319 cortex_m->fp_code_available++;
1320
1321 return ERROR_OK;
1322 }
1323
1324 int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1325 {
1326 int dwt_num = 0;
1327 uint32_t mask, temp;
1328 struct cortex_m_common *cortex_m = target_to_cm(target);
1329
1330 /* watchpoint params were validated earlier */
1331 mask = 0;
1332 temp = watchpoint->length;
1333 while (temp) {
1334 temp >>= 1;
1335 mask++;
1336 }
1337 mask--;
1338
1339 /* REVISIT Don't fully trust these "not used" records ... users
1340 * may set up breakpoints by hand, e.g. dual-address data value
1341 * watchpoint using comparator #1; comparator #0 matching cycle
1342 * count; send data trace info through ITM and TPIU; etc
1343 */
1344 struct cortex_m_dwt_comparator *comparator;
1345
1346 for (comparator = cortex_m->dwt_comparator_list;
1347 comparator->used && dwt_num < cortex_m->dwt_num_comp;
1348 comparator++, dwt_num++)
1349 continue;
1350 if (dwt_num >= cortex_m->dwt_num_comp) {
1351 LOG_ERROR("Can not find free DWT Comparator");
1352 return ERROR_FAIL;
1353 }
1354 comparator->used = 1;
1355 watchpoint->set = dwt_num + 1;
1356
1357 comparator->comp = watchpoint->address;
1358 target_write_u32(target, comparator->dwt_comparator_address + 0,
1359 comparator->comp);
1360
1361 comparator->mask = mask;
1362 target_write_u32(target, comparator->dwt_comparator_address + 4,
1363 comparator->mask);
1364
1365 switch (watchpoint->rw) {
1366 case WPT_READ:
1367 comparator->function = 5;
1368 break;
1369 case WPT_WRITE:
1370 comparator->function = 6;
1371 break;
1372 case WPT_ACCESS:
1373 comparator->function = 7;
1374 break;
1375 }
1376 target_write_u32(target, comparator->dwt_comparator_address + 8,
1377 comparator->function);
1378
1379 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1380 watchpoint->unique_id, dwt_num,
1381 (unsigned) comparator->comp,
1382 (unsigned) comparator->mask,
1383 (unsigned) comparator->function);
1384 return ERROR_OK;
1385 }
1386
1387 int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1388 {
1389 struct cortex_m_common *cortex_m = target_to_cm(target);
1390 struct cortex_m_dwt_comparator *comparator;
1391 int dwt_num;
1392
1393 if (!watchpoint->set) {
1394 LOG_WARNING("watchpoint (wpid: %d) not set",
1395 watchpoint->unique_id);
1396 return ERROR_OK;
1397 }
1398
1399 dwt_num = watchpoint->set - 1;
1400
1401 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1402 watchpoint->unique_id, dwt_num,
1403 (unsigned) watchpoint->address);
1404
1405 if ((dwt_num < 0) || (dwt_num >= cortex_m->dwt_num_comp)) {
1406 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1407 return ERROR_OK;
1408 }
1409
1410 comparator = cortex_m->dwt_comparator_list + dwt_num;
1411 comparator->used = 0;
1412 comparator->function = 0;
1413 target_write_u32(target, comparator->dwt_comparator_address + 8,
1414 comparator->function);
1415
1416 watchpoint->set = false;
1417
1418 return ERROR_OK;
1419 }
1420
1421 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1422 {
1423 struct cortex_m_common *cortex_m = target_to_cm(target);
1424
1425 if (cortex_m->dwt_comp_available < 1) {
1426 LOG_DEBUG("no comparators?");
1427 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1428 }
1429
1430 /* hardware doesn't support data value masking */
1431 if (watchpoint->mask != ~(uint32_t)0) {
1432 LOG_DEBUG("watchpoint value masks not supported");
1433 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1434 }
1435
1436 /* hardware allows address masks of up to 32K */
1437 unsigned mask;
1438
1439 for (mask = 0; mask < 16; mask++) {
1440 if ((1u << mask) == watchpoint->length)
1441 break;
1442 }
1443 if (mask == 16) {
1444 LOG_DEBUG("unsupported watchpoint length");
1445 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1446 }
1447 if (watchpoint->address & ((1 << mask) - 1)) {
1448 LOG_DEBUG("watchpoint address is unaligned");
1449 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1450 }
1451
1452 /* Caller doesn't seem to be able to describe watching for data
1453 * values of zero; that flags "no value".
1454 *
1455 * REVISIT This DWT may well be able to watch for specific data
1456 * values. Requires comparator #1 to set DATAVMATCH and match
1457 * the data, and another comparator (DATAVADDR0) matching addr.
1458 */
1459 if (watchpoint->value) {
1460 LOG_DEBUG("data value watchpoint not YET supported");
1461 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1462 }
1463
1464 cortex_m->dwt_comp_available--;
1465 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1466
1467 return ERROR_OK;
1468 }
1469
1470 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1471 {
1472 struct cortex_m_common *cortex_m = target_to_cm(target);
1473
1474 /* REVISIT why check? DWT can be updated with core running ... */
1475 if (target->state != TARGET_HALTED) {
1476 LOG_WARNING("target not halted");
1477 return ERROR_TARGET_NOT_HALTED;
1478 }
1479
1480 if (watchpoint->set)
1481 cortex_m_unset_watchpoint(target, watchpoint);
1482
1483 cortex_m->dwt_comp_available++;
1484 LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
1485
1486 return ERROR_OK;
1487 }
1488
1489 void cortex_m_enable_watchpoints(struct target *target)
1490 {
1491 struct watchpoint *watchpoint = target->watchpoints;
1492
1493 /* set any pending watchpoints */
1494 while (watchpoint) {
1495 if (!watchpoint->set)
1496 cortex_m_set_watchpoint(target, watchpoint);
1497 watchpoint = watchpoint->next;
1498 }
1499 }
1500
1501 static int cortex_m_load_core_reg_u32(struct target *target,
1502 uint32_t num, uint32_t *value)
1503 {
1504 int retval;
1505
1506 /* NOTE: we "know" here that the register identifiers used
1507 * in the v7m header match the Cortex-M3 Debug Core Register
1508 * Selector values for R0..R15, xPSR, MSP, and PSP.
1509 */
1510 switch (num) {
1511 case 0 ... 18:
1512 /* read a normal core register */
1513 retval = cortexm_dap_read_coreregister_u32(target, value, num);
1514
1515 if (retval != ERROR_OK) {
1516 LOG_ERROR("JTAG failure %i", retval);
1517 return ERROR_JTAG_DEVICE_ERROR;
1518 }
1519 LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
1520 break;
1521
1522 case ARMV7M_FPSCR:
1523 /* Floating-point Status and Registers */
1524 retval = target_write_u32(target, DCB_DCRSR, 0x21);
1525 if (retval != ERROR_OK)
1526 return retval;
1527 retval = target_read_u32(target, DCB_DCRDR, value);
1528 if (retval != ERROR_OK)
1529 return retval;
1530 LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
1531 break;
1532
1533 case ARMV7M_S0 ... ARMV7M_S31:
1534 /* Floating-point Status and Registers */
1535 retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
1536 if (retval != ERROR_OK)
1537 return retval;
1538 retval = target_read_u32(target, DCB_DCRDR, value);
1539 if (retval != ERROR_OK)
1540 return retval;
1541 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
1542 (int)(num - ARMV7M_S0), *value);
1543 break;
1544
1545 case ARMV7M_PRIMASK:
1546 case ARMV7M_BASEPRI:
1547 case ARMV7M_FAULTMASK:
1548 case ARMV7M_CONTROL:
1549 /* Cortex-M3 packages these four registers as bitfields
1550 * in one Debug Core register. So say r0 and r2 docs;
1551 * it was removed from r1 docs, but still works.
1552 */
1553 cortexm_dap_read_coreregister_u32(target, value, 20);
1554
1555 switch (num) {
1556 case ARMV7M_PRIMASK:
1557 *value = buf_get_u32((uint8_t *)value, 0, 1);
1558 break;
1559
1560 case ARMV7M_BASEPRI:
1561 *value = buf_get_u32((uint8_t *)value, 8, 8);
1562 break;
1563
1564 case ARMV7M_FAULTMASK:
1565 *value = buf_get_u32((uint8_t *)value, 16, 1);
1566 break;
1567
1568 case ARMV7M_CONTROL:
1569 *value = buf_get_u32((uint8_t *)value, 24, 2);
1570 break;
1571 }
1572
1573 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1574 break;
1575
1576 default:
1577 return ERROR_COMMAND_SYNTAX_ERROR;
1578 }
1579
1580 return ERROR_OK;
1581 }
1582
1583 static int cortex_m_store_core_reg_u32(struct target *target,
1584 uint32_t num, uint32_t value)
1585 {
1586 int retval;
1587 uint32_t reg;
1588 struct armv7m_common *armv7m = target_to_armv7m(target);
1589
1590 /* NOTE: we "know" here that the register identifiers used
1591 * in the v7m header match the Cortex-M3 Debug Core Register
1592 * Selector values for R0..R15, xPSR, MSP, and PSP.
1593 */
1594 switch (num) {
1595 case 0 ... 18:
1596 retval = cortexm_dap_write_coreregister_u32(target, value, num);
1597 if (retval != ERROR_OK) {
1598 struct reg *r;
1599
1600 LOG_ERROR("JTAG failure");
1601 r = armv7m->arm.core_cache->reg_list + num;
1602 r->dirty = r->valid;
1603 return ERROR_JTAG_DEVICE_ERROR;
1604 }
1605 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1606 break;
1607
1608 case ARMV7M_FPSCR:
1609 /* Floating-point Status and Registers */
1610 retval = target_write_u32(target, DCB_DCRDR, value);
1611 if (retval != ERROR_OK)
1612 return retval;
1613 retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
1614 if (retval != ERROR_OK)
1615 return retval;
1616 LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
1617 break;
1618
1619 case ARMV7M_S0 ... ARMV7M_S31:
1620 /* Floating-point Status and Registers */
1621 retval = target_write_u32(target, DCB_DCRDR, value);
1622 if (retval != ERROR_OK)
1623 return retval;
1624 retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
1625 if (retval != ERROR_OK)
1626 return retval;
1627 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
1628 (int)(num - ARMV7M_S0), value);
1629 break;
1630
1631 case ARMV7M_PRIMASK:
1632 case ARMV7M_BASEPRI:
1633 case ARMV7M_FAULTMASK:
1634 case ARMV7M_CONTROL:
1635 /* Cortex-M3 packages these four registers as bitfields
1636 * in one Debug Core register. So say r0 and r2 docs;
1637 * it was removed from r1 docs, but still works.
1638 */
1639 cortexm_dap_read_coreregister_u32(target, &reg, 20);
1640
1641 switch (num) {
1642 case ARMV7M_PRIMASK:
1643 buf_set_u32((uint8_t *)&reg, 0, 1, value);
1644 break;
1645
1646 case ARMV7M_BASEPRI:
1647 buf_set_u32((uint8_t *)&reg, 8, 8, value);
1648 break;
1649
1650 case ARMV7M_FAULTMASK:
1651 buf_set_u32((uint8_t *)&reg, 16, 1, value);
1652 break;
1653
1654 case ARMV7M_CONTROL:
1655 buf_set_u32((uint8_t *)&reg, 24, 2, value);
1656 break;
1657 }
1658
1659 cortexm_dap_write_coreregister_u32(target, reg, 20);
1660
1661 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1662 break;
1663
1664 default:
1665 return ERROR_COMMAND_SYNTAX_ERROR;
1666 }
1667
1668 return ERROR_OK;
1669 }
1670
1671 static int cortex_m_read_memory(struct target *target, target_addr_t address,
1672 uint32_t size, uint32_t count, uint8_t *buffer)
1673 {
1674 struct armv7m_common *armv7m = target_to_armv7m(target);
1675
1676 if (armv7m->arm.is_armv6m) {
1677 /* armv6m does not handle unaligned memory access */
1678 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1679 return ERROR_TARGET_UNALIGNED_ACCESS;
1680 }
1681
1682 return mem_ap_read_buf(armv7m->debug_ap, buffer, size, count, address);
1683 }
1684
1685 static int cortex_m_write_memory(struct target *target, target_addr_t address,
1686 uint32_t size, uint32_t count, const uint8_t *buffer)
1687 {
1688 struct armv7m_common *armv7m = target_to_armv7m(target);
1689
1690 if (armv7m->arm.is_armv6m) {
1691 /* armv6m does not handle unaligned memory access */
1692 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1693 return ERROR_TARGET_UNALIGNED_ACCESS;
1694 }
1695
1696 return mem_ap_write_buf(armv7m->debug_ap, buffer, size, count, address);
1697 }
1698
1699 static int cortex_m_init_target(struct command_context *cmd_ctx,
1700 struct target *target)
1701 {
1702 armv7m_build_reg_cache(target);
1703 arm_semihosting_init(target);
1704 return ERROR_OK;
1705 }
1706
1707 void cortex_m_deinit_target(struct target *target)
1708 {
1709 struct cortex_m_common *cortex_m = target_to_cm(target);
1710
1711 free(cortex_m->fp_comparator_list);
1712
1713 cortex_m_dwt_free(target);
1714 armv7m_free_reg_cache(target);
1715
1716 free(target->private_config);
1717 free(cortex_m);
1718 }
1719
1720 int cortex_m_profiling(struct target *target, uint32_t *samples,
1721 uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds)
1722 {
1723 struct timeval timeout, now;
1724 struct armv7m_common *armv7m = target_to_armv7m(target);
1725 uint32_t reg_value;
1726 bool use_pcsr = false;
1727 int retval = ERROR_OK;
1728 struct reg *reg;
1729
1730 gettimeofday(&timeout, NULL);
1731 timeval_add_time(&timeout, seconds, 0);
1732
1733 retval = target_read_u32(target, DWT_PCSR, &reg_value);
1734 if (retval != ERROR_OK) {
1735 LOG_ERROR("Error while reading PCSR");
1736 return retval;
1737 }
1738
1739 if (reg_value != 0) {
1740 use_pcsr = true;
1741 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1742 } else {
1743 LOG_INFO("Starting profiling. Halting and resuming the"
1744 " target as often as we can...");
1745 reg = register_get_by_name(target->reg_cache, "pc", 1);
1746 }
1747
1748 /* Make sure the target is running */
1749 target_poll(target);
1750 if (target->state == TARGET_HALTED)
1751 retval = target_resume(target, 1, 0, 0, 0);
1752
1753 if (retval != ERROR_OK) {
1754 LOG_ERROR("Error while resuming target");
1755 return retval;
1756 }
1757
1758 uint32_t sample_count = 0;
1759
1760 for (;;) {
1761 if (use_pcsr) {
1762 if (armv7m && armv7m->debug_ap) {
1763 uint32_t read_count = max_num_samples - sample_count;
1764 if (read_count > 1024)
1765 read_count = 1024;
1766
1767 retval = mem_ap_read_buf_noincr(armv7m->debug_ap,
1768 (void *)&samples[sample_count],
1769 4, read_count, DWT_PCSR);
1770 sample_count += read_count;
1771 } else {
1772 target_read_u32(target, DWT_PCSR, &samples[sample_count++]);
1773 }
1774 } else {
1775 target_poll(target);
1776 if (target->state == TARGET_HALTED) {
1777 reg_value = buf_get_u32(reg->value, 0, 32);
1778 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1779 retval = target_resume(target, 1, 0, 0, 0);
1780 samples[sample_count++] = reg_value;
1781 target_poll(target);
1782 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1783 } else if (target->state == TARGET_RUNNING) {
1784 /* We want to quickly sample the PC. */
1785 retval = target_halt(target);
1786 } else {
1787 LOG_INFO("Target not halted or running");
1788 retval = ERROR_OK;
1789 break;
1790 }
1791 }
1792
1793 if (retval != ERROR_OK) {
1794 LOG_ERROR("Error while reading %s", use_pcsr ? "PCSR" : "target pc");
1795 return retval;
1796 }
1797
1798
1799 gettimeofday(&now, NULL);
1800 if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
1801 LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
1802 break;
1803 }
1804 }
1805
1806 *num_samples = sample_count;
1807 return retval;
1808 }
1809
1810
1811 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1812 * on r/w if the core is not running, and clear on resume or reset ... or
1813 * at least, in a post_restore_context() method.
1814 */
1815
1816 struct dwt_reg_state {
1817 struct target *target;
1818 uint32_t addr;
1819 uint8_t value[4]; /* scratch/cache */
1820 };
1821
1822 static int cortex_m_dwt_get_reg(struct reg *reg)
1823 {
1824 struct dwt_reg_state *state = reg->arch_info;
1825
1826 uint32_t tmp;
1827 int retval = target_read_u32(state->target, state->addr, &tmp);
1828 if (retval != ERROR_OK)
1829 return retval;
1830
1831 buf_set_u32(state->value, 0, 32, tmp);
1832 return ERROR_OK;
1833 }
1834
1835 static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
1836 {
1837 struct dwt_reg_state *state = reg->arch_info;
1838
1839 return target_write_u32(state->target, state->addr,
1840 buf_get_u32(buf, 0, reg->size));
1841 }
1842
1843 struct dwt_reg {
1844 uint32_t addr;
1845 const char *name;
1846 unsigned size;
1847 };
1848
1849 static const struct dwt_reg dwt_base_regs[] = {
1850 { DWT_CTRL, "dwt_ctrl", 32, },
1851 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1852 * increments while the core is asleep.
1853 */
1854 { DWT_CYCCNT, "dwt_cyccnt", 32, },
1855 /* plus some 8 bit counters, useful for profiling with TPIU */
1856 };
1857
1858 static const struct dwt_reg dwt_comp[] = {
1859 #define DWT_COMPARATOR(i) \
1860 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1861 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1862 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1863 DWT_COMPARATOR(0),
1864 DWT_COMPARATOR(1),
1865 DWT_COMPARATOR(2),
1866 DWT_COMPARATOR(3),
1867 DWT_COMPARATOR(4),
1868 DWT_COMPARATOR(5),
1869 DWT_COMPARATOR(6),
1870 DWT_COMPARATOR(7),
1871 DWT_COMPARATOR(8),
1872 DWT_COMPARATOR(9),
1873 DWT_COMPARATOR(10),
1874 DWT_COMPARATOR(11),
1875 DWT_COMPARATOR(12),
1876 DWT_COMPARATOR(13),
1877 DWT_COMPARATOR(14),
1878 DWT_COMPARATOR(15),
1879 #undef DWT_COMPARATOR
1880 };
1881
1882 static const struct reg_arch_type dwt_reg_type = {
1883 .get = cortex_m_dwt_get_reg,
1884 .set = cortex_m_dwt_set_reg,
1885 };
1886
1887 static void cortex_m_dwt_addreg(struct target *t, struct reg *r, const struct dwt_reg *d)
1888 {
1889 struct dwt_reg_state *state;
1890
1891 state = calloc(1, sizeof *state);
1892 if (!state)
1893 return;
1894 state->addr = d->addr;
1895 state->target = t;
1896
1897 r->name = d->name;
1898 r->size = d->size;
1899 r->value = state->value;
1900 r->arch_info = state;
1901 r->type = &dwt_reg_type;
1902 }
1903
1904 void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target)
1905 {
1906 uint32_t dwtcr;
1907 struct reg_cache *cache;
1908 struct cortex_m_dwt_comparator *comparator;
1909 int reg, i;
1910
1911 target_read_u32(target, DWT_CTRL, &dwtcr);
1912 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
1913 if (!dwtcr) {
1914 LOG_DEBUG("no DWT");
1915 return;
1916 }
1917
1918 cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
1919 cm->dwt_comp_available = cm->dwt_num_comp;
1920 cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
1921 sizeof(struct cortex_m_dwt_comparator));
1922 if (!cm->dwt_comparator_list) {
1923 fail0:
1924 cm->dwt_num_comp = 0;
1925 LOG_ERROR("out of mem");
1926 return;
1927 }
1928
1929 cache = calloc(1, sizeof *cache);
1930 if (!cache) {
1931 fail1:
1932 free(cm->dwt_comparator_list);
1933 goto fail0;
1934 }
1935 cache->name = "Cortex-M DWT registers";
1936 cache->num_regs = 2 + cm->dwt_num_comp * 3;
1937 cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1938 if (!cache->reg_list) {
1939 free(cache);
1940 goto fail1;
1941 }
1942
1943 for (reg = 0; reg < 2; reg++)
1944 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1945 dwt_base_regs + reg);
1946
1947 comparator = cm->dwt_comparator_list;
1948 for (i = 0; i < cm->dwt_num_comp; i++, comparator++) {
1949 int j;
1950
1951 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1952 for (j = 0; j < 3; j++, reg++)
1953 cortex_m_dwt_addreg(target, cache->reg_list + reg,
1954 dwt_comp + 3 * i + j);
1955
1956 /* make sure we clear any watchpoints enabled on the target */
1957 target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
1958 }
1959
1960 *register_get_last_cache_p(&target->reg_cache) = cache;
1961 cm->dwt_cache = cache;
1962
1963 LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1964 dwtcr, cm->dwt_num_comp,
1965 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1966
1967 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1968 * implement single-address data value watchpoints ... so we
1969 * won't need to check it later, when asked to set one up.
1970 */
1971 }
1972
1973 static void cortex_m_dwt_free(struct target *target)
1974 {
1975 struct cortex_m_common *cm = target_to_cm(target);
1976 struct reg_cache *cache = cm->dwt_cache;
1977
1978 free(cm->dwt_comparator_list);
1979 cm->dwt_comparator_list = NULL;
1980 cm->dwt_num_comp = 0;
1981
1982 if (cache) {
1983 register_unlink_cache(&target->reg_cache, cache);
1984
1985 if (cache->reg_list) {
1986 for (size_t i = 0; i < cache->num_regs; i++)
1987 free(cache->reg_list[i].arch_info);
1988 free(cache->reg_list);
1989 }
1990 free(cache);
1991 }
1992 cm->dwt_cache = NULL;
1993 }
1994
1995 #define MVFR0 0xe000ef40
1996 #define MVFR1 0xe000ef44
1997
1998 #define MVFR0_DEFAULT_M4 0x10110021
1999 #define MVFR1_DEFAULT_M4 0x11000011
2000
2001 #define MVFR0_DEFAULT_M7_SP 0x10110021
2002 #define MVFR0_DEFAULT_M7_DP 0x10110221
2003 #define MVFR1_DEFAULT_M7_SP 0x11000011
2004 #define MVFR1_DEFAULT_M7_DP 0x12000011
2005
2006 int cortex_m_examine(struct target *target)
2007 {
2008 int retval;
2009 uint32_t cpuid, fpcr, mvfr0, mvfr1;
2010 int i;
2011 struct cortex_m_common *cortex_m = target_to_cm(target);
2012 struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
2013 struct armv7m_common *armv7m = target_to_armv7m(target);
2014
2015 /* stlink shares the examine handler but does not support
2016 * all its calls */
2017 if (!armv7m->stlink) {
2018 if (cortex_m->apsel == DP_APSEL_INVALID) {
2019 /* Search for the MEM-AP */
2020 retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
2021 if (retval != ERROR_OK) {
2022 LOG_ERROR("Could not find MEM-AP to control the core");
2023 return retval;
2024 }
2025 } else {
2026 armv7m->debug_ap = dap_ap(swjdp, cortex_m->apsel);
2027 }
2028
2029 /* Leave (only) generic DAP stuff for debugport_init(); */
2030 armv7m->debug_ap->memaccess_tck = 8;
2031
2032 retval = mem_ap_init(armv7m->debug_ap);
2033 if (retval != ERROR_OK)
2034 return retval;
2035 }
2036
2037 if (!target_was_examined(target)) {
2038 target_set_examined(target);
2039
2040 /* Read from Device Identification Registers */
2041 retval = target_read_u32(target, CPUID, &cpuid);
2042 if (retval != ERROR_OK)
2043 return retval;
2044
2045 /* Get CPU Type */
2046 i = (cpuid >> 4) & 0xf;
2047
2048 LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
2049 i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
2050 if (i == 7) {
2051 uint8_t rev, patch;
2052 rev = (cpuid >> 20) & 0xf;
2053 patch = (cpuid >> 0) & 0xf;
2054 if ((rev == 0) && (patch < 2))
2055 LOG_WARNING("Silicon bug: single stepping will enter pending exception handler!");
2056 }
2057 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
2058
2059 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2060 cortex_m->vectreset_supported = i > 1;
2061
2062 if (i == 4) {
2063 target_read_u32(target, MVFR0, &mvfr0);
2064 target_read_u32(target, MVFR1, &mvfr1);
2065
2066 /* test for floating point feature on Cortex-M4 */
2067 if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
2068 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
2069 armv7m->fp_feature = FPv4_SP;
2070 }
2071 } else if (i == 7) {
2072 target_read_u32(target, MVFR0, &mvfr0);
2073 target_read_u32(target, MVFR1, &mvfr1);
2074
2075 /* test for floating point features on Cortex-M7 */
2076 if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
2077 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
2078 armv7m->fp_feature = FPv5_SP;
2079 } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
2080 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
2081 armv7m->fp_feature = FPv5_DP;
2082 }
2083 } else if (i == 0) {
2084 /* Cortex-M0 does not support unaligned memory access */
2085 armv7m->arm.is_armv6m = true;
2086 }
2087
2088 if (armv7m->fp_feature == FP_NONE &&
2089 armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
2090 /* free unavailable FPU registers */
2091 size_t idx;
2092
2093 for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
2094 idx < armv7m->arm.core_cache->num_regs;
2095 idx++) {
2096 free(armv7m->arm.core_cache->reg_list[idx].value);
2097 free(armv7m->arm.core_cache->reg_list[idx].feature);
2098 free(armv7m->arm.core_cache->reg_list[idx].reg_data_type);
2099 }
2100 armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
2101 }
2102
2103 if (!armv7m->stlink) {
2104 if (i == 3 || i == 4)
2105 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2106 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2107 armv7m->debug_ap->tar_autoincr_block = (1 << 12);
2108 else if (i == 7)
2109 /* Cortex-M7 has only 1024 bytes autoincrement range */
2110 armv7m->debug_ap->tar_autoincr_block = (1 << 10);
2111 }
2112
2113 /* Configure trace modules */
2114 retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
2115 if (retval != ERROR_OK)
2116 return retval;
2117
2118 if (armv7m->trace_config.config_type != TRACE_CONFIG_TYPE_DISABLED) {
2119 armv7m_trace_tpiu_config(target);
2120 armv7m_trace_itm_config(target);
2121 }
2122
2123 /* NOTE: FPB and DWT are both optional. */
2124
2125 /* Setup FPB */
2126 target_read_u32(target, FP_CTRL, &fpcr);
2127 /* bits [14:12] and [7:4] */
2128 cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
2129 cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
2130 cortex_m->fp_code_available = cortex_m->fp_num_code;
2131 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2132 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2133 cortex_m->fp_rev = (fpcr >> 28) & 0xf;
2134 free(cortex_m->fp_comparator_list);
2135 cortex_m->fp_comparator_list = calloc(
2136 cortex_m->fp_num_code + cortex_m->fp_num_lit,
2137 sizeof(struct cortex_m_fp_comparator));
2138 cortex_m->fpb_enabled = fpcr & 1;
2139 for (i = 0; i < cortex_m->fp_num_code + cortex_m->fp_num_lit; i++) {
2140 cortex_m->fp_comparator_list[i].type =
2141 (i < cortex_m->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
2142 cortex_m->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
2143
2144 /* make sure we clear any breakpoints enabled on the target */
2145 target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
2146 }
2147 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
2148 fpcr,
2149 cortex_m->fp_num_code,
2150 cortex_m->fp_num_lit);
2151
2152 /* Setup DWT */
2153 cortex_m_dwt_free(target);
2154 cortex_m_dwt_setup(cortex_m, target);
2155
2156 /* These hardware breakpoints only work for code in flash! */
2157 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2158 target_name(target),
2159 cortex_m->fp_num_code,
2160 cortex_m->dwt_num_comp);
2161 }
2162
2163 return ERROR_OK;
2164 }
2165
2166 static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
2167 {
2168 struct armv7m_common *armv7m = target_to_armv7m(target);
2169 uint16_t dcrdr;
2170 uint8_t buf[2];
2171 int retval;
2172
2173 retval = mem_ap_read_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2174 if (retval != ERROR_OK)
2175 return retval;
2176
2177 dcrdr = target_buffer_get_u16(target, buf);
2178 *ctrl = (uint8_t)dcrdr;
2179 *value = (uint8_t)(dcrdr >> 8);
2180
2181 LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
2182
2183 /* write ack back to software dcc register
2184 * signify we have read data */
2185 if (dcrdr & (1 << 0)) {
2186 target_buffer_set_u16(target, buf, 0);
2187 retval = mem_ap_write_buf_noincr(armv7m->debug_ap, buf, 2, 1, DCB_DCRDR);
2188 if (retval != ERROR_OK)
2189 return retval;
2190 }
2191
2192 return ERROR_OK;
2193 }
2194
2195 static int cortex_m_target_request_data(struct target *target,
2196 uint32_t size, uint8_t *buffer)
2197 {
2198 uint8_t data;
2199 uint8_t ctrl;
2200 uint32_t i;
2201
2202 for (i = 0; i < (size * 4); i++) {
2203 int retval = cortex_m_dcc_read(target, &data, &ctrl);
2204 if (retval != ERROR_OK)
2205 return retval;
2206 buffer[i] = data;
2207 }
2208
2209 return ERROR_OK;
2210 }
2211
2212 static int cortex_m_handle_target_request(void *priv)
2213 {
2214 struct target *target = priv;
2215 if (!target_was_examined(target))
2216 return ERROR_OK;
2217
2218 if (!target->dbg_msg_enabled)
2219 return ERROR_OK;
2220
2221 if (target->state == TARGET_RUNNING) {
2222 uint8_t data;
2223 uint8_t ctrl;
2224 int retval;
2225
2226 retval = cortex_m_dcc_read(target, &data, &ctrl);
2227 if (retval != ERROR_OK)
2228 return retval;
2229
2230 /* check if we have data */
2231 if (ctrl & (1 << 0)) {
2232 uint32_t request;
2233
2234 /* we assume target is quick enough */
2235 request = data;
2236 for (int i = 1; i <= 3; i++) {
2237 retval = cortex_m_dcc_read(target, &data, &ctrl);
2238 if (retval != ERROR_OK)
2239 return retval;
2240 request |= ((uint32_t)data << (i * 8));
2241 }
2242 target_request(target, request);
2243 }
2244 }
2245
2246 return ERROR_OK;
2247 }
2248
2249 static int cortex_m_init_arch_info(struct target *target,
2250 struct cortex_m_common *cortex_m, struct adiv5_dap *dap)
2251 {
2252 struct armv7m_common *armv7m = &cortex_m->armv7m;
2253
2254 armv7m_init_arch_info(target, armv7m);
2255
2256 /* default reset mode is to use srst if fitted
2257 * if not it will use CORTEX_M3_RESET_VECTRESET */
2258 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2259
2260 armv7m->arm.dap = dap;
2261
2262 /* register arch-specific functions */
2263 armv7m->examine_debug_reason = cortex_m_examine_debug_reason;
2264
2265 armv7m->post_debug_entry = NULL;
2266
2267 armv7m->pre_restore_context = NULL;
2268
2269 armv7m->load_core_reg_u32 = cortex_m_load_core_reg_u32;
2270 armv7m->store_core_reg_u32 = cortex_m_store_core_reg_u32;
2271
2272 target_register_timer_callback(cortex_m_handle_target_request, 1, 1, target);
2273
2274 return ERROR_OK;
2275 }
2276
2277 static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
2278 {
2279 struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
2280 cortex_m->common_magic = CORTEX_M_COMMON_MAGIC;
2281 struct adiv5_private_config *pc;
2282
2283 pc = (struct adiv5_private_config *)target->private_config;
2284 if (adiv5_verify_config(pc) != ERROR_OK)
2285 return ERROR_FAIL;
2286
2287 cortex_m->apsel = pc->ap_num;
2288
2289 cortex_m_init_arch_info(target, cortex_m, pc->dap);
2290
2291 return ERROR_OK;
2292 }
2293
2294 /*--------------------------------------------------------------------------*/
2295
2296 static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
2297 struct cortex_m_common *cm)
2298 {
2299 if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
2300 command_print(cmd_ctx, "target is not a Cortex-M");
2301 return ERROR_TARGET_INVALID;
2302 }
2303 return ERROR_OK;
2304 }
2305
2306 /*
2307 * Only stuff below this line should need to verify that its target
2308 * is a Cortex-M3. Everything else should have indirected through the
2309 * cortexm3_target structure, which is only used with CM3 targets.
2310 */
2311
2312 COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
2313 {
2314 struct target *target = get_current_target(CMD_CTX);
2315 struct cortex_m_common *cortex_m = target_to_cm(target);
2316 struct armv7m_common *armv7m = &cortex_m->armv7m;
2317 uint32_t demcr = 0;
2318 int retval;
2319
2320 static const struct {
2321 char name[10];
2322 unsigned mask;
2323 } vec_ids[] = {
2324 { "hard_err", VC_HARDERR, },
2325 { "int_err", VC_INTERR, },
2326 { "bus_err", VC_BUSERR, },
2327 { "state_err", VC_STATERR, },
2328 { "chk_err", VC_CHKERR, },
2329 { "nocp_err", VC_NOCPERR, },
2330 { "mm_err", VC_MMERR, },
2331 { "reset", VC_CORERESET, },
2332 };
2333
2334 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2335 if (retval != ERROR_OK)
2336 return retval;
2337
2338 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2339 if (retval != ERROR_OK)
2340 return retval;
2341
2342 if (CMD_ARGC > 0) {
2343 unsigned catch = 0;
2344
2345 if (CMD_ARGC == 1) {
2346 if (strcmp(CMD_ARGV[0], "all") == 0) {
2347 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2348 | VC_STATERR | VC_CHKERR | VC_NOCPERR
2349 | VC_MMERR | VC_CORERESET;
2350 goto write;
2351 } else if (strcmp(CMD_ARGV[0], "none") == 0)
2352 goto write;
2353 }
2354 while (CMD_ARGC-- > 0) {
2355 unsigned i;
2356 for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2357 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2358 continue;
2359 catch |= vec_ids[i].mask;
2360 break;
2361 }
2362 if (i == ARRAY_SIZE(vec_ids)) {
2363 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2364 return ERROR_COMMAND_SYNTAX_ERROR;
2365 }
2366 }
2367 write:
2368 /* For now, armv7m->demcr only stores vector catch flags. */
2369 armv7m->demcr = catch;
2370
2371 demcr &= ~0xffff;
2372 demcr |= catch;
2373
2374 /* write, but don't assume it stuck (why not??) */
2375 retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR, demcr);
2376 if (retval != ERROR_OK)
2377 return retval;
2378 retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
2379 if (retval != ERROR_OK)
2380 return retval;
2381
2382 /* FIXME be sure to clear DEMCR on clean server shutdown.
2383 * Otherwise the vector catch hardware could fire when there's
2384 * no debugger hooked up, causing much confusion...
2385 */
2386 }
2387
2388 for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2389 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2390 (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2391 }
2392
2393 return ERROR_OK;
2394 }
2395
2396 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command)
2397 {
2398 struct target *target = get_current_target(CMD_CTX);
2399 struct cortex_m_common *cortex_m = target_to_cm(target);
2400 int retval;
2401
2402 static const Jim_Nvp nvp_maskisr_modes[] = {
2403 { .name = "auto", .value = CORTEX_M_ISRMASK_AUTO },
2404 { .name = "off", .value = CORTEX_M_ISRMASK_OFF },
2405 { .name = "on", .value = CORTEX_M_ISRMASK_ON },
2406 { .name = NULL, .value = -1 },
2407 };
2408 const Jim_Nvp *n;
2409
2410
2411 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2412 if (retval != ERROR_OK)
2413 return retval;
2414
2415 if (target->state != TARGET_HALTED) {
2416 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2417 return ERROR_OK;
2418 }
2419
2420 if (CMD_ARGC > 0) {
2421 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2422 if (n->name == NULL)
2423 return ERROR_COMMAND_SYNTAX_ERROR;
2424 cortex_m->isrmasking_mode = n->value;
2425
2426
2427 if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
2428 cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2429 else
2430 cortex_m_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2431 }
2432
2433 n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
2434 command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
2435
2436 return ERROR_OK;
2437 }
2438
2439 COMMAND_HANDLER(handle_cortex_m_reset_config_command)
2440 {
2441 struct target *target = get_current_target(CMD_CTX);
2442 struct cortex_m_common *cortex_m = target_to_cm(target);
2443 int retval;
2444 char *reset_config;
2445
2446 retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
2447 if (retval != ERROR_OK)
2448 return retval;
2449
2450 if (CMD_ARGC > 0) {
2451 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2452 cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
2453
2454 else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
2455 if (target_was_examined(target)
2456 && !cortex_m->vectreset_supported)
2457 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2458 else
2459 cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
2460
2461 } else
2462 return ERROR_COMMAND_SYNTAX_ERROR;
2463 }
2464
2465 switch (cortex_m->soft_reset_config) {
2466 case CORTEX_M_RESET_SYSRESETREQ:
2467 reset_config = "sysresetreq";
2468 break;
2469
2470 case CORTEX_M_RESET_VECTRESET:
2471 reset_config = "vectreset";
2472 break;
2473
2474 default:
2475 reset_config = "unknown";
2476 break;
2477 }
2478
2479 command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
2480
2481 return ERROR_OK;
2482 }
2483
2484 static const struct command_registration cortex_m_exec_command_handlers[] = {
2485 {
2486 .name = "maskisr",
2487 .handler = handle_cortex_m_mask_interrupts_command,
2488 .mode = COMMAND_EXEC,
2489 .help = "mask cortex_m interrupts",
2490 .usage = "['auto'|'on'|'off']",
2491 },
2492 {
2493 .name = "vector_catch",
2494 .handler = handle_cortex_m_vector_catch_command,
2495 .mode = COMMAND_EXEC,
2496 .help = "configure hardware vectors to trigger debug entry",
2497 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2498 },
2499 {
2500 .name = "reset_config",
2501 .handler = handle_cortex_m_reset_config_command,
2502 .mode = COMMAND_ANY,
2503 .help = "configure software reset handling",
2504 .usage = "['sysresetreq'|'vectreset']",
2505 },
2506 COMMAND_REGISTRATION_DONE
2507 };
2508 static const struct command_registration cortex_m_command_handlers[] = {
2509 {
2510 .chain = armv7m_command_handlers,
2511 },
2512 {
2513 .chain = armv7m_trace_command_handlers,
2514 },
2515 {
2516 .name = "cortex_m",
2517 .mode = COMMAND_EXEC,
2518 .help = "Cortex-M command group",
2519 .usage = "",
2520 .chain = cortex_m_exec_command_handlers,
2521 },
2522 COMMAND_REGISTRATION_DONE
2523 };
2524
2525 struct target_type cortexm_target = {
2526 .name = "cortex_m",
2527 .deprecated_name = "cortex_m3",
2528
2529 .poll = cortex_m_poll,
2530 .arch_state = armv7m_arch_state,
2531
2532 .target_request_data = cortex_m_target_request_data,
2533
2534 .halt = cortex_m_halt,
2535 .resume = cortex_m_resume,
2536 .step = cortex_m_step,
2537
2538 .assert_reset = cortex_m_assert_reset,
2539 .deassert_reset = cortex_m_deassert_reset,
2540 .soft_reset_halt = cortex_m_soft_reset_halt,
2541
2542 .get_gdb_arch = arm_get_gdb_arch,
2543 .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2544
2545 .read_memory = cortex_m_read_memory,
2546 .write_memory = cortex_m_write_memory,
2547 .checksum_memory = armv7m_checksum_memory,
2548 .blank_check_memory = armv7m_blank_check_memory,
2549
2550 .run_algorithm = armv7m_run_algorithm,
2551 .start_algorithm = armv7m_start_algorithm,
2552 .wait_algorithm = armv7m_wait_algorithm,
2553
2554 .add_breakpoint = cortex_m_add_breakpoint,
2555 .remove_breakpoint = cortex_m_remove_breakpoint,
2556 .add_watchpoint = cortex_m_add_watchpoint,
2557 .remove_watchpoint = cortex_m_remove_watchpoint,
2558
2559 .commands = cortex_m_command_handlers,
2560 .target_create = cortex_m_target_create,
2561 .target_jim_configure = adiv5_jim_configure,
2562 .init_target = cortex_m_init_target,
2563 .examine = cortex_m_examine,
2564 .deinit_target = cortex_m_deinit_target,
2565
2566 .profiling = cortex_m_profiling,
2567 };
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