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SAM3: Remove unused reference to SUPC registers
[openocd.git] / src / flash / nor / at91sam3.c
blob50f522f94e41bd178a50e8138fbe5475254e2091
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
17 * GNU General public License for more details. *
18 * *
19 * You should have received a copy of the GNU General public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ****************************************************************************/
24
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
27
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
33 *
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
38 *
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
41 *
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
44 *
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
56 */
57 /* END ATMEL COPYRIGHT */
58
59 #ifdef HAVE_CONFIG_H
60 #include "config.h"
61 #endif
62
63 #include "imp.h"
64 #include <helper/time_support.h>
65
66 #define REG_NAME_WIDTH (12)
67
68 /* at91sam3u series (has one or two flash banks) */
69 #define FLASH_BANK0_BASE_U 0x00080000
70 #define FLASH_BANK1_BASE_U 0x00100000
71
72 /* at91sam3s series (has always one flash bank) */
73 #define FLASH_BANK_BASE_S 0x00400000
74
75 /* at91sam3n series (has always one flash bank) */
76 #define FLASH_BANK_BASE_N 0x00400000
77
78 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
79 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
80 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
81 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
82 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page
83 * then Lock */
84 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
85 /* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
86 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
87 /* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
88 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
97
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
102
103 extern struct flash_driver at91sam3_flash;
104
105 static float _tomhz(uint32_t freq_hz)
106 {
107 float f;
108
109 f = ((float)(freq_hz)) / 1000000.0;
110 return f;
111 }
112
113 /* How the chip is configured. */
114 struct sam3_cfg {
115 uint32_t unique_id[4];
116
117 uint32_t slow_freq;
118 uint32_t rc_freq;
119 uint32_t mainosc_freq;
120 uint32_t plla_freq;
121 uint32_t mclk_freq;
122 uint32_t cpu_freq;
123 uint32_t fclk_freq;
124 uint32_t pclk0_freq;
125 uint32_t pclk1_freq;
126 uint32_t pclk2_freq;
127
128
129 #define SAM3_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR;
131 #define SAM3_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID;
133
134 #define SAM3_PMC_BASE (0x400E0400)
135 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
136 uint32_t PMC_SCSR;
137 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
138 uint32_t PMC_PCSR;
139 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
140 uint32_t CKGR_UCKR;
141 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
142 uint32_t CKGR_MOR;
143 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
144 uint32_t CKGR_MCFR;
145 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
146 uint32_t CKGR_PLLAR;
147 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
148 uint32_t PMC_MCKR;
149 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
150 uint32_t PMC_PCK0;
151 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
152 uint32_t PMC_PCK1;
153 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
154 uint32_t PMC_PCK2;
155 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
156 uint32_t PMC_SR;
157 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
158 uint32_t PMC_IMR;
159 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
160 uint32_t PMC_FSMR;
161 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
162 uint32_t PMC_FSPR;
163 };
164
165 /*
166 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
167 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
168 * the flash wait state (FWS) should be set to 6. It seems like that the
169 * cause of the problem is not the flash itself, but the flash write
170 * buffer. Ie the wait states have to be set before writing into the
171 * buffer.
172 * Tested and confirmed with SAM3N and SAM3U
173 */
174
175 struct sam3_bank_private {
176 int probed;
177 /* DANGER: THERE ARE DRAGONS HERE.. */
178 /* NOTE: If you add more 'ghost' pointers */
179 /* be aware that you must *manually* update */
180 /* these pointers in the function sam3_GetDetails() */
181 /* See the comment "Here there be dragons" */
182
183 /* so we can find the chip we belong to */
184 struct sam3_chip *pChip;
185 /* so we can find the orginal bank pointer */
186 struct flash_bank *pBank;
187 unsigned bank_number;
188 uint32_t controller_address;
189 uint32_t base_address;
190 uint32_t flash_wait_states;
191 bool present;
192 unsigned size_bytes;
193 unsigned nsectors;
194 unsigned sector_size;
195 unsigned page_size;
196 };
197
198 struct sam3_chip_details {
199 /* THERE ARE DRAGONS HERE.. */
200 /* note: If you add pointers here */
201 /* becareful about them as they */
202 /* may need to be updated inside */
203 /* the function: "sam3_GetDetails() */
204 /* which copy/overwrites the */
205 /* 'runtime' copy of this structure */
206 uint32_t chipid_cidr;
207 const char *name;
208
209 unsigned n_gpnvms;
210 #define SAM3_N_NVM_BITS 3
211 unsigned gpnvm[SAM3_N_NVM_BITS];
212 unsigned total_flash_size;
213 unsigned total_sram_size;
214 unsigned n_banks;
215 #define SAM3_MAX_FLASH_BANKS 2
216 /* these are "initialized" from the global const data */
217 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
218 };
219
220 struct sam3_chip {
221 struct sam3_chip *next;
222 int probed;
223
224 /* this is "initialized" from the global const structure */
225 struct sam3_chip_details details;
226 struct target *target;
227 struct sam3_cfg cfg;
228 };
229
230
231 struct sam3_reg_list {
232 uint32_t address; size_t struct_offset; const char *name;
233 void (*explain_func)(struct sam3_chip *pInfo);
234 };
235
236 static struct sam3_chip *all_sam3_chips;
237
238 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
239 {
240 struct target *t;
241 static struct sam3_chip *p;
242
243 t = get_current_target(cmd_ctx);
244 if (!t) {
245 command_print(cmd_ctx, "No current target?");
246 return NULL;
247 }
248
249 p = all_sam3_chips;
250 if (!p) {
251 /* this should not happen */
252 /* the command is not registered until the chip is created? */
253 command_print(cmd_ctx, "No SAM3 chips exist?");
254 return NULL;
255 }
256
257 while (p) {
258 if (p->target == t)
259 return p;
260 p = p->next;
261 }
262 command_print(cmd_ctx, "Cannot find SAM3 chip?");
263 return NULL;
264 }
265
266 /* these are used to *initialize* the "pChip->details" structure. */
267 static const struct sam3_chip_details all_sam3_details[] = {
268 /* Start at91sam3u* series */
269 {
270 .chipid_cidr = 0x28100960,
271 .name = "at91sam3u4e",
272 .total_flash_size = 256 * 1024,
273 .total_sram_size = 52 * 1024,
274 .n_gpnvms = 3,
275 .n_banks = 2,
276
277 /* System boots at address 0x0 */
278 /* gpnvm[1] = selects boot code */
279 /* if gpnvm[1] == 0 */
280 /* boot is via "SAMBA" (rom) */
281 /* else */
282 /* boot is via FLASH */
283 /* Selection is via gpnvm[2] */
284 /* endif */
285 /* */
286 /* NOTE: banks 0 & 1 switch places */
287 /* if gpnvm[2] == 0 */
288 /* Bank0 is the boot rom */
289 /* else */
290 /* Bank1 is the boot rom */
291 /* endif */
292 /* .bank[0] = { */
293 {
294 {
295 .probed = 0,
296 .pChip = NULL,
297 .pBank = NULL,
298 .bank_number = 0,
299 .base_address = FLASH_BANK0_BASE_U,
300 .controller_address = 0x400e0800,
301 .flash_wait_states = 6, /* workaround silicon bug */
302 .present = 1,
303 .size_bytes = 128 * 1024,
304 .nsectors = 16,
305 .sector_size = 8192,
306 .page_size = 256,
307 },
308
309 /* .bank[1] = { */
310 {
311 .probed = 0,
312 .pChip = NULL,
313 .pBank = NULL,
314 .bank_number = 1,
315 .base_address = FLASH_BANK1_BASE_U,
316 .controller_address = 0x400e0a00,
317 .flash_wait_states = 6, /* workaround silicon bug */
318 .present = 1,
319 .size_bytes = 128 * 1024,
320 .nsectors = 16,
321 .sector_size = 8192,
322 .page_size = 256,
323 },
324 },
325 },
326
327 {
328 .chipid_cidr = 0x281a0760,
329 .name = "at91sam3u2e",
330 .total_flash_size = 128 * 1024,
331 .total_sram_size = 36 * 1024,
332 .n_gpnvms = 2,
333 .n_banks = 1,
334
335 /* System boots at address 0x0 */
336 /* gpnvm[1] = selects boot code */
337 /* if gpnvm[1] == 0 */
338 /* boot is via "SAMBA" (rom) */
339 /* else */
340 /* boot is via FLASH */
341 /* Selection is via gpnvm[2] */
342 /* endif */
343 /* .bank[0] = { */
344 {
345 {
346 .probed = 0,
347 .pChip = NULL,
348 .pBank = NULL,
349 .bank_number = 0,
350 .base_address = FLASH_BANK0_BASE_U,
351 .controller_address = 0x400e0800,
352 .flash_wait_states = 6, /* workaround silicon bug */
353 .present = 1,
354 .size_bytes = 128 * 1024,
355 .nsectors = 16,
356 .sector_size = 8192,
357 .page_size = 256,
358 },
359 /* .bank[1] = { */
360 {
361 .present = 0,
362 .probed = 0,
363 .bank_number = 1,
364 },
365 },
366 },
367 {
368 .chipid_cidr = 0x28190560,
369 .name = "at91sam3u1e",
370 .total_flash_size = 64 * 1024,
371 .total_sram_size = 20 * 1024,
372 .n_gpnvms = 2,
373 .n_banks = 1,
374
375 /* System boots at address 0x0 */
376 /* gpnvm[1] = selects boot code */
377 /* if gpnvm[1] == 0 */
378 /* boot is via "SAMBA" (rom) */
379 /* else */
380 /* boot is via FLASH */
381 /* Selection is via gpnvm[2] */
382 /* endif */
383 /* */
384
385 /* .bank[0] = { */
386 {
387 {
388 .probed = 0,
389 .pChip = NULL,
390 .pBank = NULL,
391 .bank_number = 0,
392 .base_address = FLASH_BANK0_BASE_U,
393 .controller_address = 0x400e0800,
394 .flash_wait_states = 6, /* workaround silicon bug */
395 .present = 1,
396 .size_bytes = 64 * 1024,
397 .nsectors = 8,
398 .sector_size = 8192,
399 .page_size = 256,
400 },
401
402 /* .bank[1] = { */
403 {
404 .present = 0,
405 .probed = 0,
406 .bank_number = 1,
407 },
408 },
409 },
410
411 {
412 .chipid_cidr = 0x28000960,
413 .name = "at91sam3u4c",
414 .total_flash_size = 256 * 1024,
415 .total_sram_size = 52 * 1024,
416 .n_gpnvms = 3,
417 .n_banks = 2,
418
419 /* System boots at address 0x0 */
420 /* gpnvm[1] = selects boot code */
421 /* if gpnvm[1] == 0 */
422 /* boot is via "SAMBA" (rom) */
423 /* else */
424 /* boot is via FLASH */
425 /* Selection is via gpnvm[2] */
426 /* endif */
427 /* */
428 /* NOTE: banks 0 & 1 switch places */
429 /* if gpnvm[2] == 0 */
430 /* Bank0 is the boot rom */
431 /* else */
432 /* Bank1 is the boot rom */
433 /* endif */
434 {
435 {
436 /* .bank[0] = { */
437 .probed = 0,
438 .pChip = NULL,
439 .pBank = NULL,
440 .bank_number = 0,
441 .base_address = FLASH_BANK0_BASE_U,
442 .controller_address = 0x400e0800,
443 .flash_wait_states = 6, /* workaround silicon bug */
444 .present = 1,
445 .size_bytes = 128 * 1024,
446 .nsectors = 16,
447 .sector_size = 8192,
448 .page_size = 256,
449 },
450 /* .bank[1] = { */
451 {
452 .probed = 0,
453 .pChip = NULL,
454 .pBank = NULL,
455 .bank_number = 1,
456 .base_address = FLASH_BANK1_BASE_U,
457 .controller_address = 0x400e0a00,
458 .flash_wait_states = 6, /* workaround silicon bug */
459 .present = 1,
460 .size_bytes = 128 * 1024,
461 .nsectors = 16,
462 .sector_size = 8192,
463 .page_size = 256,
464 },
465 },
466 },
467
468 {
469 .chipid_cidr = 0x280a0760,
470 .name = "at91sam3u2c",
471 .total_flash_size = 128 * 1024,
472 .total_sram_size = 36 * 1024,
473 .n_gpnvms = 2,
474 .n_banks = 1,
475
476 /* System boots at address 0x0 */
477 /* gpnvm[1] = selects boot code */
478 /* if gpnvm[1] == 0 */
479 /* boot is via "SAMBA" (rom) */
480 /* else */
481 /* boot is via FLASH */
482 /* Selection is via gpnvm[2] */
483 /* endif */
484 {
485 /* .bank[0] = { */
486 {
487 .probed = 0,
488 .pChip = NULL,
489 .pBank = NULL,
490 .bank_number = 0,
491 .base_address = FLASH_BANK0_BASE_U,
492 .controller_address = 0x400e0800,
493 .flash_wait_states = 6, /* workaround silicon bug */
494 .present = 1,
495 .size_bytes = 128 * 1024,
496 .nsectors = 16,
497 .sector_size = 8192,
498 .page_size = 256,
499 },
500 /* .bank[1] = { */
501 {
502 .present = 0,
503 .probed = 0,
504 .bank_number = 1,
505 },
506 },
507 },
508 {
509 .chipid_cidr = 0x28090560,
510 .name = "at91sam3u1c",
511 .total_flash_size = 64 * 1024,
512 .total_sram_size = 20 * 1024,
513 .n_gpnvms = 2,
514 .n_banks = 1,
515
516 /* System boots at address 0x0 */
517 /* gpnvm[1] = selects boot code */
518 /* if gpnvm[1] == 0 */
519 /* boot is via "SAMBA" (rom) */
520 /* else */
521 /* boot is via FLASH */
522 /* Selection is via gpnvm[2] */
523 /* endif */
524 /* */
525
526 {
527 /* .bank[0] = { */
528 {
529 .probed = 0,
530 .pChip = NULL,
531 .pBank = NULL,
532 .bank_number = 0,
533 .base_address = FLASH_BANK0_BASE_U,
534 .controller_address = 0x400e0800,
535 .flash_wait_states = 6, /* workaround silicon bug */
536 .present = 1,
537 .size_bytes = 64 * 1024,
538 .nsectors = 8,
539 .sector_size = 8192,
540 .page_size = 256,
541 },
542 /* .bank[1] = { */
543 {
544 .present = 0,
545 .probed = 0,
546 .bank_number = 1,
547
548 },
549 },
550 },
551
552 /* Start at91sam3s* series */
553
554 /* Note: The preliminary at91sam3s datasheet says on page 302 */
555 /* that the flash controller is at address 0x400E0800. */
556 /* This is _not_ the case, the controller resides at address 0x400e0a0. */
557 {
558 .chipid_cidr = 0x28A00960,
559 .name = "at91sam3s4c",
560 .total_flash_size = 256 * 1024,
561 .total_sram_size = 48 * 1024,
562 .n_gpnvms = 2,
563 .n_banks = 1,
564 {
565 /* .bank[0] = { */
566 {
567 .probed = 0,
568 .pChip = NULL,
569 .pBank = NULL,
570 .bank_number = 0,
571 .base_address = FLASH_BANK_BASE_S,
572 .controller_address = 0x400e0a00,
573 .flash_wait_states = 6, /* workaround silicon bug */
574 .present = 1,
575 .size_bytes = 256 * 1024,
576 .nsectors = 16,
577 .sector_size = 16384,
578 .page_size = 256,
579 },
580 /* .bank[1] = { */
581 {
582 .present = 0,
583 .probed = 0,
584 .bank_number = 1,
585
586 },
587 },
588 },
589
590 {
591 .chipid_cidr = 0x28900960,
592 .name = "at91sam3s4b",
593 .total_flash_size = 256 * 1024,
594 .total_sram_size = 48 * 1024,
595 .n_gpnvms = 2,
596 .n_banks = 1,
597 {
598 /* .bank[0] = { */
599 {
600 .probed = 0,
601 .pChip = NULL,
602 .pBank = NULL,
603 .bank_number = 0,
604 .base_address = FLASH_BANK_BASE_S,
605 .controller_address = 0x400e0a00,
606 .flash_wait_states = 6, /* workaround silicon bug */
607 .present = 1,
608 .size_bytes = 256 * 1024,
609 .nsectors = 16,
610 .sector_size = 16384,
611 .page_size = 256,
612 },
613 /* .bank[1] = { */
614 {
615 .present = 0,
616 .probed = 0,
617 .bank_number = 1,
618
619 },
620 },
621 },
622 {
623 .chipid_cidr = 0x28800960,
624 .name = "at91sam3s4a",
625 .total_flash_size = 256 * 1024,
626 .total_sram_size = 48 * 1024,
627 .n_gpnvms = 2,
628 .n_banks = 1,
629 {
630 /* .bank[0] = { */
631 {
632 .probed = 0,
633 .pChip = NULL,
634 .pBank = NULL,
635 .bank_number = 0,
636 .base_address = FLASH_BANK_BASE_S,
637 .controller_address = 0x400e0a00,
638 .flash_wait_states = 6, /* workaround silicon bug */
639 .present = 1,
640 .size_bytes = 256 * 1024,
641 .nsectors = 16,
642 .sector_size = 16384,
643 .page_size = 256,
644 },
645 /* .bank[1] = { */
646 {
647 .present = 0,
648 .probed = 0,
649 .bank_number = 1,
650
651 },
652 },
653 },
654 {
655 .chipid_cidr = 0x28AA0760,
656 .name = "at91sam3s2c",
657 .total_flash_size = 128 * 1024,
658 .total_sram_size = 32 * 1024,
659 .n_gpnvms = 2,
660 .n_banks = 1,
661 {
662 /* .bank[0] = { */
663 {
664 .probed = 0,
665 .pChip = NULL,
666 .pBank = NULL,
667 .bank_number = 0,
668 .base_address = FLASH_BANK_BASE_S,
669 .controller_address = 0x400e0a00,
670 .flash_wait_states = 6, /* workaround silicon bug */
671 .present = 1,
672 .size_bytes = 128 * 1024,
673 .nsectors = 8,
674 .sector_size = 16384,
675 .page_size = 256,
676 },
677 /* .bank[1] = { */
678 {
679 .present = 0,
680 .probed = 0,
681 .bank_number = 1,
682
683 },
684 },
685 },
686 {
687 .chipid_cidr = 0x289A0760,
688 .name = "at91sam3s2b",
689 .total_flash_size = 128 * 1024,
690 .total_sram_size = 32 * 1024,
691 .n_gpnvms = 2,
692 .n_banks = 1,
693 {
694 /* .bank[0] = { */
695 {
696 .probed = 0,
697 .pChip = NULL,
698 .pBank = NULL,
699 .bank_number = 0,
700 .base_address = FLASH_BANK_BASE_S,
701 .controller_address = 0x400e0a00,
702 .flash_wait_states = 6, /* workaround silicon bug */
703 .present = 1,
704 .size_bytes = 128 * 1024,
705 .nsectors = 8,
706 .sector_size = 16384,
707 .page_size = 256,
708 },
709 /* .bank[1] = { */
710 {
711 .present = 0,
712 .probed = 0,
713 .bank_number = 1,
714
715 },
716 },
717 },
718 {
719 .chipid_cidr = 0x288A0760,
720 .name = "at91sam3s2a",
721 .total_flash_size = 128 * 1024,
722 .total_sram_size = 32 * 1024,
723 .n_gpnvms = 2,
724 .n_banks = 1,
725 {
726 /* .bank[0] = { */
727 {
728 .probed = 0,
729 .pChip = NULL,
730 .pBank = NULL,
731 .bank_number = 0,
732 .base_address = FLASH_BANK_BASE_S,
733 .controller_address = 0x400e0a00,
734 .flash_wait_states = 6, /* workaround silicon bug */
735 .present = 1,
736 .size_bytes = 128 * 1024,
737 .nsectors = 8,
738 .sector_size = 16384,
739 .page_size = 256,
740 },
741 /* .bank[1] = { */
742 {
743 .present = 0,
744 .probed = 0,
745 .bank_number = 1,
746
747 },
748 },
749 },
750 {
751 .chipid_cidr = 0x28A90560,
752 .name = "at91sam3s1c",
753 .total_flash_size = 64 * 1024,
754 .total_sram_size = 16 * 1024,
755 .n_gpnvms = 2,
756 .n_banks = 1,
757 {
758 /* .bank[0] = { */
759 {
760 .probed = 0,
761 .pChip = NULL,
762 .pBank = NULL,
763 .bank_number = 0,
764 .base_address = FLASH_BANK_BASE_S,
765 .controller_address = 0x400e0a00,
766 .flash_wait_states = 6, /* workaround silicon bug */
767 .present = 1,
768 .size_bytes = 64 * 1024,
769 .nsectors = 4,
770 .sector_size = 16384,
771 .page_size = 256,
772 },
773 /* .bank[1] = { */
774 {
775 .present = 0,
776 .probed = 0,
777 .bank_number = 1,
778
779 },
780 },
781 },
782 {
783 .chipid_cidr = 0x28990560,
784 .name = "at91sam3s1b",
785 .total_flash_size = 64 * 1024,
786 .total_sram_size = 16 * 1024,
787 .n_gpnvms = 2,
788 .n_banks = 1,
789 {
790 /* .bank[0] = { */
791 {
792 .probed = 0,
793 .pChip = NULL,
794 .pBank = NULL,
795 .bank_number = 0,
796 .base_address = FLASH_BANK_BASE_S,
797 .controller_address = 0x400e0a00,
798 .flash_wait_states = 6, /* workaround silicon bug */
799 .present = 1,
800 .size_bytes = 64 * 1024,
801 .nsectors = 4,
802 .sector_size = 16384,
803 .page_size = 256,
804 },
805 /* .bank[1] = { */
806 {
807 .present = 0,
808 .probed = 0,
809 .bank_number = 1,
810
811 },
812 },
813 },
814 {
815 .chipid_cidr = 0x28890560,
816 .name = "at91sam3s1a",
817 .total_flash_size = 64 * 1024,
818 .total_sram_size = 16 * 1024,
819 .n_gpnvms = 2,
820 .n_banks = 1,
821 {
822 /* .bank[0] = { */
823 {
824 .probed = 0,
825 .pChip = NULL,
826 .pBank = NULL,
827 .bank_number = 0,
828 .base_address = FLASH_BANK_BASE_S,
829 .controller_address = 0x400e0a00,
830 .flash_wait_states = 6, /* workaround silicon bug */
831 .present = 1,
832 .size_bytes = 64 * 1024,
833 .nsectors = 4,
834 .sector_size = 16384,
835 .page_size = 256,
836 },
837 /* .bank[1] = { */
838 {
839 .present = 0,
840 .probed = 0,
841 .bank_number = 1,
842
843 },
844 },
845 },
846
847 /* Start at91sam3n* series */
848 {
849 .chipid_cidr = 0x29540960,
850 .name = "at91sam3n4c",
851 .total_flash_size = 256 * 1024,
852 .total_sram_size = 24 * 1024,
853 .n_gpnvms = 3,
854 .n_banks = 1,
855
856 /* System boots at address 0x0 */
857 /* gpnvm[1] = selects boot code */
858 /* if gpnvm[1] == 0 */
859 /* boot is via "SAMBA" (rom) */
860 /* else */
861 /* boot is via FLASH */
862 /* Selection is via gpnvm[2] */
863 /* endif */
864 /* */
865 /* NOTE: banks 0 & 1 switch places */
866 /* if gpnvm[2] == 0 */
867 /* Bank0 is the boot rom */
868 /* else */
869 /* Bank1 is the boot rom */
870 /* endif */
871 /* .bank[0] = { */
872 {
873 {
874 .probed = 0,
875 .pChip = NULL,
876 .pBank = NULL,
877 .bank_number = 0,
878 .base_address = FLASH_BANK_BASE_N,
879 .controller_address = 0x400e0A00,
880 .flash_wait_states = 6, /* workaround silicon bug */
881 .present = 1,
882 .size_bytes = 256 * 1024,
883 .nsectors = 16,
884 .sector_size = 16384,
885 .page_size = 256,
886 },
887
888 /* .bank[1] = { */
889 {
890 .present = 0,
891 .probed = 0,
892 .bank_number = 1,
893 },
894 },
895 },
896
897 {
898 .chipid_cidr = 0x29440960,
899 .name = "at91sam3n4b",
900 .total_flash_size = 256 * 1024,
901 .total_sram_size = 24 * 1024,
902 .n_gpnvms = 3,
903 .n_banks = 1,
904
905 /* System boots at address 0x0 */
906 /* gpnvm[1] = selects boot code */
907 /* if gpnvm[1] == 0 */
908 /* boot is via "SAMBA" (rom) */
909 /* else */
910 /* boot is via FLASH */
911 /* Selection is via gpnvm[2] */
912 /* endif */
913 /* */
914 /* NOTE: banks 0 & 1 switch places */
915 /* if gpnvm[2] == 0 */
916 /* Bank0 is the boot rom */
917 /* else */
918 /* Bank1 is the boot rom */
919 /* endif */
920 /* .bank[0] = { */
921 {
922 {
923 .probed = 0,
924 .pChip = NULL,
925 .pBank = NULL,
926 .bank_number = 0,
927 .base_address = FLASH_BANK_BASE_N,
928 .controller_address = 0x400e0A00,
929 .flash_wait_states = 6, /* workaround silicon bug */
930 .present = 1,
931 .size_bytes = 256 * 1024,
932 .nsectors = 16,
933 .sector_size = 16384,
934 .page_size = 256,
935 },
936
937 /* .bank[1] = { */
938 {
939 .present = 0,
940 .probed = 0,
941 .bank_number = 1,
942 },
943 },
944 },
945
946 {
947 .chipid_cidr = 0x29340960,
948 .name = "at91sam3n4a",
949 .total_flash_size = 256 * 1024,
950 .total_sram_size = 24 * 1024,
951 .n_gpnvms = 3,
952 .n_banks = 1,
953
954 /* System boots at address 0x0 */
955 /* gpnvm[1] = selects boot code */
956 /* if gpnvm[1] == 0 */
957 /* boot is via "SAMBA" (rom) */
958 /* else */
959 /* boot is via FLASH */
960 /* Selection is via gpnvm[2] */
961 /* endif */
962 /* */
963 /* NOTE: banks 0 & 1 switch places */
964 /* if gpnvm[2] == 0 */
965 /* Bank0 is the boot rom */
966 /* else */
967 /* Bank1 is the boot rom */
968 /* endif */
969 /* .bank[0] = { */
970 {
971 {
972 .probed = 0,
973 .pChip = NULL,
974 .pBank = NULL,
975 .bank_number = 0,
976 .base_address = FLASH_BANK_BASE_N,
977 .controller_address = 0x400e0A00,
978 .flash_wait_states = 6, /* workaround silicon bug */
979 .present = 1,
980 .size_bytes = 256 * 1024,
981 .nsectors = 16,
982 .sector_size = 16384,
983 .page_size = 256,
984 },
985
986 /* .bank[1] = { */
987 {
988 .present = 0,
989 .probed = 0,
990 .bank_number = 1,
991 },
992 },
993 },
994
995 {
996 .chipid_cidr = 0x29590760,
997 .name = "at91sam3n2c",
998 .total_flash_size = 128 * 1024,
999 .total_sram_size = 16 * 1024,
1000 .n_gpnvms = 3,
1001 .n_banks = 1,
1002
1003 /* System boots at address 0x0 */
1004 /* gpnvm[1] = selects boot code */
1005 /* if gpnvm[1] == 0 */
1006 /* boot is via "SAMBA" (rom) */
1007 /* else */
1008 /* boot is via FLASH */
1009 /* Selection is via gpnvm[2] */
1010 /* endif */
1011 /* */
1012 /* NOTE: banks 0 & 1 switch places */
1013 /* if gpnvm[2] == 0 */
1014 /* Bank0 is the boot rom */
1015 /* else */
1016 /* Bank1 is the boot rom */
1017 /* endif */
1018 /* .bank[0] = { */
1019 {
1020 {
1021 .probed = 0,
1022 .pChip = NULL,
1023 .pBank = NULL,
1024 .bank_number = 0,
1025 .base_address = FLASH_BANK_BASE_N,
1026 .controller_address = 0x400e0A00,
1027 .flash_wait_states = 6, /* workaround silicon bug */
1028 .present = 1,
1029 .size_bytes = 128 * 1024,
1030 .nsectors = 8,
1031 .sector_size = 16384,
1032 .page_size = 256,
1033 },
1034
1035 /* .bank[1] = { */
1036 {
1037 .present = 0,
1038 .probed = 0,
1039 .bank_number = 1,
1040 },
1041 },
1042 },
1043
1044 {
1045 .chipid_cidr = 0x29490760,
1046 .name = "at91sam3n2b",
1047 .total_flash_size = 128 * 1024,
1048 .total_sram_size = 16 * 1024,
1049 .n_gpnvms = 3,
1050 .n_banks = 1,
1051
1052 /* System boots at address 0x0 */
1053 /* gpnvm[1] = selects boot code */
1054 /* if gpnvm[1] == 0 */
1055 /* boot is via "SAMBA" (rom) */
1056 /* else */
1057 /* boot is via FLASH */
1058 /* Selection is via gpnvm[2] */
1059 /* endif */
1060 /* */
1061 /* NOTE: banks 0 & 1 switch places */
1062 /* if gpnvm[2] == 0 */
1063 /* Bank0 is the boot rom */
1064 /* else */
1065 /* Bank1 is the boot rom */
1066 /* endif */
1067 /* .bank[0] = { */
1068 {
1069 {
1070 .probed = 0,
1071 .pChip = NULL,
1072 .pBank = NULL,
1073 .bank_number = 0,
1074 .base_address = FLASH_BANK_BASE_N,
1075 .controller_address = 0x400e0A00,
1076 .flash_wait_states = 6, /* workaround silicon bug */
1077 .present = 1,
1078 .size_bytes = 128 * 1024,
1079 .nsectors = 8,
1080 .sector_size = 16384,
1081 .page_size = 256,
1082 },
1083
1084 /* .bank[1] = { */
1085 {
1086 .present = 0,
1087 .probed = 0,
1088 .bank_number = 1,
1089 },
1090 },
1091 },
1092
1093 {
1094 .chipid_cidr = 0x29390760,
1095 .name = "at91sam3n2a",
1096 .total_flash_size = 128 * 1024,
1097 .total_sram_size = 16 * 1024,
1098 .n_gpnvms = 3,
1099 .n_banks = 1,
1100
1101 /* System boots at address 0x0 */
1102 /* gpnvm[1] = selects boot code */
1103 /* if gpnvm[1] == 0 */
1104 /* boot is via "SAMBA" (rom) */
1105 /* else */
1106 /* boot is via FLASH */
1107 /* Selection is via gpnvm[2] */
1108 /* endif */
1109 /* */
1110 /* NOTE: banks 0 & 1 switch places */
1111 /* if gpnvm[2] == 0 */
1112 /* Bank0 is the boot rom */
1113 /* else */
1114 /* Bank1 is the boot rom */
1115 /* endif */
1116 /* .bank[0] = { */
1117 {
1118 {
1119 .probed = 0,
1120 .pChip = NULL,
1121 .pBank = NULL,
1122 .bank_number = 0,
1123 .base_address = FLASH_BANK_BASE_N,
1124 .controller_address = 0x400e0A00,
1125 .flash_wait_states = 6, /* workaround silicon bug */
1126 .present = 1,
1127 .size_bytes = 128 * 1024,
1128 .nsectors = 8,
1129 .sector_size = 16384,
1130 .page_size = 256,
1131 },
1132
1133 /* .bank[1] = { */
1134 {
1135 .present = 0,
1136 .probed = 0,
1137 .bank_number = 1,
1138 },
1139 },
1140 },
1141
1142 {
1143 .chipid_cidr = 0x29580560,
1144 .name = "at91sam3n1c",
1145 .total_flash_size = 64 * 1024,
1146 .total_sram_size = 8 * 1024,
1147 .n_gpnvms = 3,
1148 .n_banks = 1,
1149
1150 /* System boots at address 0x0 */
1151 /* gpnvm[1] = selects boot code */
1152 /* if gpnvm[1] == 0 */
1153 /* boot is via "SAMBA" (rom) */
1154 /* else */
1155 /* boot is via FLASH */
1156 /* Selection is via gpnvm[2] */
1157 /* endif */
1158 /* */
1159 /* NOTE: banks 0 & 1 switch places */
1160 /* if gpnvm[2] == 0 */
1161 /* Bank0 is the boot rom */
1162 /* else */
1163 /* Bank1 is the boot rom */
1164 /* endif */
1165 /* .bank[0] = { */
1166 {
1167 {
1168 .probed = 0,
1169 .pChip = NULL,
1170 .pBank = NULL,
1171 .bank_number = 0,
1172 .base_address = FLASH_BANK_BASE_N,
1173 .controller_address = 0x400e0A00,
1174 .flash_wait_states = 6, /* workaround silicon bug */
1175 .present = 1,
1176 .size_bytes = 64 * 1024,
1177 .nsectors = 4,
1178 .sector_size = 16384,
1179 .page_size = 256,
1180 },
1181
1182 /* .bank[1] = { */
1183 {
1184 .present = 0,
1185 .probed = 0,
1186 .bank_number = 1,
1187 },
1188 },
1189 },
1190
1191 {
1192 .chipid_cidr = 0x29480560,
1193 .name = "at91sam3n1b",
1194 .total_flash_size = 64 * 1024,
1195 .total_sram_size = 8 * 1024,
1196 .n_gpnvms = 3,
1197 .n_banks = 1,
1198
1199 /* System boots at address 0x0 */
1200 /* gpnvm[1] = selects boot code */
1201 /* if gpnvm[1] == 0 */
1202 /* boot is via "SAMBA" (rom) */
1203 /* else */
1204 /* boot is via FLASH */
1205 /* Selection is via gpnvm[2] */
1206 /* endif */
1207 /* */
1208 /* NOTE: banks 0 & 1 switch places */
1209 /* if gpnvm[2] == 0 */
1210 /* Bank0 is the boot rom */
1211 /* else */
1212 /* Bank1 is the boot rom */
1213 /* endif */
1214 /* .bank[0] = { */
1215 {
1216 {
1217 .probed = 0,
1218 .pChip = NULL,
1219 .pBank = NULL,
1220 .bank_number = 0,
1221 .base_address = FLASH_BANK_BASE_N,
1222 .controller_address = 0x400e0A00,
1223 .flash_wait_states = 6, /* workaround silicon bug */
1224 .present = 1,
1225 .size_bytes = 64 * 1024,
1226 .nsectors = 4,
1227 .sector_size = 16384,
1228 .page_size = 256,
1229 },
1230
1231 /* .bank[1] = { */
1232 {
1233 .present = 0,
1234 .probed = 0,
1235 .bank_number = 1,
1236 },
1237 },
1238 },
1239
1240 {
1241 .chipid_cidr = 0x29380560,
1242 .name = "at91sam3n1a",
1243 .total_flash_size = 64 * 1024,
1244 .total_sram_size = 8 * 1024,
1245 .n_gpnvms = 3,
1246 .n_banks = 1,
1247
1248 /* System boots at address 0x0 */
1249 /* gpnvm[1] = selects boot code */
1250 /* if gpnvm[1] == 0 */
1251 /* boot is via "SAMBA" (rom) */
1252 /* else */
1253 /* boot is via FLASH */
1254 /* Selection is via gpnvm[2] */
1255 /* endif */
1256 /* */
1257 /* NOTE: banks 0 & 1 switch places */
1258 /* if gpnvm[2] == 0 */
1259 /* Bank0 is the boot rom */
1260 /* else */
1261 /* Bank1 is the boot rom */
1262 /* endif */
1263 /* .bank[0] = { */
1264 {
1265 {
1266 .probed = 0,
1267 .pChip = NULL,
1268 .pBank = NULL,
1269 .bank_number = 0,
1270 .base_address = FLASH_BANK_BASE_N,
1271 .controller_address = 0x400e0A00,
1272 .flash_wait_states = 6, /* workaround silicon bug */
1273 .present = 1,
1274 .size_bytes = 64 * 1024,
1275 .nsectors = 4,
1276 .sector_size = 16384,
1277 .page_size = 256,
1278 },
1279
1280 /* .bank[1] = { */
1281 {
1282 .present = 0,
1283 .probed = 0,
1284 .bank_number = 1,
1285 },
1286 },
1287 },
1288
1289 /* terminate */
1290 {
1291 .chipid_cidr = 0,
1292 .name = NULL,
1293 }
1294 };
1295
1296 /* Globals above */
1297 /***********************************************************************
1298 **********************************************************************
1299 **********************************************************************
1300 **********************************************************************
1301 **********************************************************************
1302 **********************************************************************/
1303 /* *ATMEL* style code - from the SAM3 driver code */
1304
1305 /**
1306 * Get the current status of the EEFC and
1307 * the value of some status bits (LOCKE, PROGE).
1308 * @param pPrivate - info about the bank
1309 * @param v - result goes here
1310 */
1311 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1312 {
1313 int r;
1314 r = target_read_u32(pPrivate->pChip->target,
1315 pPrivate->controller_address + offset_EFC_FSR,
1316 v);
1317 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1318 (unsigned int)(*v),
1319 ((unsigned int)((*v >> 2) & 1)),
1320 ((unsigned int)((*v >> 1) & 1)),
1321 ((unsigned int)((*v >> 0) & 1)));
1322
1323 return r;
1324 }
1325
1326 /**
1327 * Get the result of the last executed command.
1328 * @param pPrivate - info about the bank
1329 * @param v - result goes here
1330 */
1331 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1332 {
1333 int r;
1334 uint32_t rv;
1335 r = target_read_u32(pPrivate->pChip->target,
1336 pPrivate->controller_address + offset_EFC_FRR,
1337 &rv);
1338 if (v)
1339 *v = rv;
1340 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1341 return r;
1342 }
1343
1344 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1345 unsigned command, unsigned argument)
1346 {
1347 uint32_t n, v;
1348 int r;
1349 int retry;
1350
1351 retry = 0;
1352 do_retry:
1353
1354 /* Check command & argument */
1355 switch (command) {
1356
1357 case AT91C_EFC_FCMD_WP:
1358 case AT91C_EFC_FCMD_WPL:
1359 case AT91C_EFC_FCMD_EWP:
1360 case AT91C_EFC_FCMD_EWPL:
1361 /* case AT91C_EFC_FCMD_EPL: */
1362 /* case AT91C_EFC_FCMD_EPA: */
1363 case AT91C_EFC_FCMD_SLB:
1364 case AT91C_EFC_FCMD_CLB:
1365 n = (pPrivate->size_bytes / pPrivate->page_size);
1366 if (argument >= n)
1367 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1368 break;
1369
1370 case AT91C_EFC_FCMD_SFB:
1371 case AT91C_EFC_FCMD_CFB:
1372 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1373 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1374 pPrivate->pChip->details.n_gpnvms);
1375 }
1376 break;
1377
1378 case AT91C_EFC_FCMD_GETD:
1379 case AT91C_EFC_FCMD_EA:
1380 case AT91C_EFC_FCMD_GLB:
1381 case AT91C_EFC_FCMD_GFB:
1382 case AT91C_EFC_FCMD_STUI:
1383 case AT91C_EFC_FCMD_SPUI:
1384 if (argument != 0)
1385 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1386 break;
1387 default:
1388 LOG_ERROR("Unknown command %d", command);
1389 break;
1390 }
1391
1392 if (command == AT91C_EFC_FCMD_SPUI) {
1393 /* this is a very special situation. */
1394 /* Situation (1) - error/retry - see below */
1395 /* And we are being called recursively */
1396 /* Situation (2) - normal, finished reading unique id */
1397 } else {
1398 /* it should be "ready" */
1399 EFC_GetStatus(pPrivate, &v);
1400 if (v & 1) {
1401 /* then it is ready */
1402 /* we go on */
1403 } else {
1404 if (retry) {
1405 /* we have done this before */
1406 /* the controller is not responding. */
1407 LOG_ERROR("flash controller(%d) is not ready! Error",
1408 pPrivate->bank_number);
1409 return ERROR_FAIL;
1410 } else {
1411 retry++;
1412 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1413 pPrivate->bank_number);
1414 /* we do that by issuing the *STOP* command */
1415 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1416 /* above is recursive, and further recursion is blocked by */
1417 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1418 goto do_retry;
1419 }
1420 }
1421 }
1422
1423 v = (0x5A << 24) | (argument << 8) | command;
1424 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1425 r = target_write_u32(pPrivate->pBank->target,
1426 pPrivate->controller_address + offset_EFC_FCR, v);
1427 if (r != ERROR_OK)
1428 LOG_DEBUG("Error Write failed");
1429 return r;
1430 }
1431
1432 /**
1433 * Performs the given command and wait until its completion (or an error).
1434 * @param pPrivate - info about the bank
1435 * @param command - Command to perform.
1436 * @param argument - Optional command argument.
1437 * @param status - put command status bits here
1438 */
1439 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1440 unsigned command,
1441 unsigned argument,
1442 uint32_t *status)
1443 {
1444
1445 int r;
1446 uint32_t v;
1447 long long ms_now, ms_end;
1448
1449 /* default */
1450 if (status)
1451 *status = 0;
1452
1453 r = EFC_StartCommand(pPrivate, command, argument);
1454 if (r != ERROR_OK)
1455 return r;
1456
1457 ms_end = 500 + timeval_ms();
1458
1459 do {
1460 r = EFC_GetStatus(pPrivate, &v);
1461 if (r != ERROR_OK)
1462 return r;
1463 ms_now = timeval_ms();
1464 if (ms_now > ms_end) {
1465 /* error */
1466 LOG_ERROR("Command timeout");
1467 return ERROR_FAIL;
1468 }
1469 } while ((v & 1) == 0);
1470
1471 /* error bits.. */
1472 if (status)
1473 *status = (v & 0x6);
1474 return ERROR_OK;
1475
1476 }
1477
1478 /**
1479 * Read the unique ID.
1480 * @param pPrivate - info about the bank
1481 * The unique ID is stored in the 'pPrivate' structure.
1482 */
1483 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1484 {
1485 int r;
1486 uint32_t v;
1487 int x;
1488 /* assume 0 */
1489 pPrivate->pChip->cfg.unique_id[0] = 0;
1490 pPrivate->pChip->cfg.unique_id[1] = 0;
1491 pPrivate->pChip->cfg.unique_id[2] = 0;
1492 pPrivate->pChip->cfg.unique_id[3] = 0;
1493
1494 LOG_DEBUG("Begin");
1495 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1496 if (r < 0)
1497 return r;
1498
1499 for (x = 0; x < 4; x++) {
1500 r = target_read_u32(pPrivate->pChip->target,
1501 pPrivate->pBank->base + (x * 4),
1502 &v);
1503 if (r < 0)
1504 return r;
1505 pPrivate->pChip->cfg.unique_id[x] = v;
1506 }
1507
1508 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1509 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1510 r,
1511 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1512 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1513 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1514 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1515 return r;
1516
1517 }
1518
1519 /**
1520 * Erases the entire flash.
1521 * @param pPrivate - the info about the bank.
1522 */
1523 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
1524 {
1525 LOG_DEBUG("Here");
1526 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1527 }
1528
1529 /**
1530 * Gets current GPNVM state.
1531 * @param pPrivate - info about the bank.
1532 * @param gpnvm - GPNVM bit index.
1533 * @param puthere - result stored here.
1534 */
1535 /* ------------------------------------------------------------------------------ */
1536 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1537 {
1538 uint32_t v;
1539 int r;
1540
1541 LOG_DEBUG("Here");
1542 if (pPrivate->bank_number != 0) {
1543 LOG_ERROR("GPNVM only works with Bank0");
1544 return ERROR_FAIL;
1545 }
1546
1547 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1548 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1549 gpnvm, pPrivate->pChip->details.n_gpnvms);
1550 return ERROR_FAIL;
1551 }
1552
1553 /* Get GPNVMs status */
1554 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1555 if (r != ERROR_OK) {
1556 LOG_ERROR("Failed");
1557 return r;
1558 }
1559
1560 r = EFC_GetResult(pPrivate, &v);
1561
1562 if (puthere) {
1563 /* Check if GPNVM is set */
1564 /* get the bit and make it a 0/1 */
1565 *puthere = (v >> gpnvm) & 1;
1566 }
1567
1568 return r;
1569 }
1570
1571 /**
1572 * Clears the selected GPNVM bit.
1573 * @param pPrivate info about the bank
1574 * @param gpnvm GPNVM index.
1575 * @returns 0 if successful; otherwise returns an error code.
1576 */
1577 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1578 {
1579 int r;
1580 unsigned v;
1581
1582 LOG_DEBUG("Here");
1583 if (pPrivate->bank_number != 0) {
1584 LOG_ERROR("GPNVM only works with Bank0");
1585 return ERROR_FAIL;
1586 }
1587
1588 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1589 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1590 gpnvm, pPrivate->pChip->details.n_gpnvms);
1591 return ERROR_FAIL;
1592 }
1593
1594 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1595 if (r != ERROR_OK) {
1596 LOG_DEBUG("Failed: %d", r);
1597 return r;
1598 }
1599 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1600 LOG_DEBUG("End: %d", r);
1601 return r;
1602 }
1603
1604 /**
1605 * Sets the selected GPNVM bit.
1606 * @param pPrivate info about the bank
1607 * @param gpnvm GPNVM index.
1608 */
1609 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
1610 {
1611 int r;
1612 unsigned v;
1613
1614 if (pPrivate->bank_number != 0) {
1615 LOG_ERROR("GPNVM only works with Bank0");
1616 return ERROR_FAIL;
1617 }
1618
1619 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1620 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1621 gpnvm, pPrivate->pChip->details.n_gpnvms);
1622 return ERROR_FAIL;
1623 }
1624
1625 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1626 if (r != ERROR_OK)
1627 return r;
1628 if (v) {
1629 /* already set */
1630 r = ERROR_OK;
1631 } else {
1632 /* set it */
1633 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1634 }
1635 return r;
1636 }
1637
1638 /**
1639 * Returns a bit field (at most 64) of locked regions within a page.
1640 * @param pPrivate info about the bank
1641 * @param v where to store locked bits
1642 */
1643 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
1644 {
1645 int r;
1646 LOG_DEBUG("Here");
1647 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1648 if (r == ERROR_OK)
1649 r = EFC_GetResult(pPrivate, v);
1650 LOG_DEBUG("End: %d", r);
1651 return r;
1652 }
1653
1654 /**
1655 * Unlocks all the regions in the given address range.
1656 * @param pPrivate info about the bank
1657 * @param start_sector first sector to unlock
1658 * @param end_sector last (inclusive) to unlock
1659 */
1660
1661 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
1662 unsigned start_sector,
1663 unsigned end_sector)
1664 {
1665 int r;
1666 uint32_t status;
1667 uint32_t pg;
1668 uint32_t pages_per_sector;
1669
1670 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1671
1672 /* Unlock all pages */
1673 while (start_sector <= end_sector) {
1674 pg = start_sector * pages_per_sector;
1675
1676 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1677 if (r != ERROR_OK)
1678 return r;
1679 start_sector++;
1680 }
1681
1682 return ERROR_OK;
1683 }
1684
1685 /**
1686 * Locks regions
1687 * @param pPrivate - info about the bank
1688 * @param start_sector - first sector to lock
1689 * @param end_sector - last sector (inclusive) to lock
1690 */
1691 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
1692 unsigned start_sector,
1693 unsigned end_sector)
1694 {
1695 uint32_t status;
1696 uint32_t pg;
1697 uint32_t pages_per_sector;
1698 int r;
1699
1700 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1701
1702 /* Lock all pages */
1703 while (start_sector <= end_sector) {
1704 pg = start_sector * pages_per_sector;
1705
1706 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1707 if (r != ERROR_OK)
1708 return r;
1709 start_sector++;
1710 }
1711 return ERROR_OK;
1712 }
1713
1714 /****** END SAM3 CODE ********/
1715
1716 /* begin helpful debug code */
1717 /* print the fieldname, the field value, in dec & hex, and return field value */
1718 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
1719 const char *regname,
1720 uint32_t value,
1721 unsigned shift,
1722 unsigned width)
1723 {
1724 uint32_t v;
1725 int hwidth, dwidth;
1726
1727
1728 /* extract the field */
1729 v = value >> shift;
1730 v = v & ((1 << width)-1);
1731 if (width <= 16) {
1732 hwidth = 4;
1733 dwidth = 5;
1734 } else {
1735 hwidth = 8;
1736 dwidth = 12;
1737 }
1738
1739 /* show the basics */
1740 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1741 REG_NAME_WIDTH, regname,
1742 dwidth, v,
1743 hwidth, v);
1744 return v;
1745 }
1746
1747 static const char _unknown[] = "unknown";
1748 static const char *const eproc_names[] = {
1749 _unknown, /* 0 */
1750 "arm946es", /* 1 */
1751 "arm7tdmi", /* 2 */
1752 "cortex-m3", /* 3 */
1753 "arm920t", /* 4 */
1754 "arm926ejs", /* 5 */
1755 _unknown, /* 6 */
1756 _unknown, /* 7 */
1757 _unknown, /* 8 */
1758 _unknown, /* 9 */
1759 _unknown, /* 10 */
1760 _unknown, /* 11 */
1761 _unknown, /* 12 */
1762 _unknown, /* 13 */
1763 _unknown, /* 14 */
1764 _unknown, /* 15 */
1765 };
1766
1767 #define nvpsize2 nvpsize /* these two tables are identical */
1768 static const char *const nvpsize[] = {
1769 "none", /* 0 */
1770 "8K bytes", /* 1 */
1771 "16K bytes", /* 2 */
1772 "32K bytes", /* 3 */
1773 _unknown, /* 4 */
1774 "64K bytes", /* 5 */
1775 _unknown, /* 6 */
1776 "128K bytes", /* 7 */
1777 _unknown, /* 8 */
1778 "256K bytes", /* 9 */
1779 "512K bytes", /* 10 */
1780 _unknown, /* 11 */
1781 "1024K bytes", /* 12 */
1782 _unknown, /* 13 */
1783 "2048K bytes", /* 14 */
1784 _unknown, /* 15 */
1785 };
1786
1787 static const char *const sramsize[] = {
1788 "48K Bytes", /* 0 */
1789 "1K Bytes", /* 1 */
1790 "2K Bytes", /* 2 */
1791 "6K Bytes", /* 3 */
1792 "112K Bytes", /* 4 */
1793 "4K Bytes", /* 5 */
1794 "80K Bytes", /* 6 */
1795 "160K Bytes", /* 7 */
1796 "8K Bytes", /* 8 */
1797 "16K Bytes", /* 9 */
1798 "32K Bytes", /* 10 */
1799 "64K Bytes", /* 11 */
1800 "128K Bytes", /* 12 */
1801 "256K Bytes", /* 13 */
1802 "96K Bytes", /* 14 */
1803 "512K Bytes", /* 15 */
1804
1805 };
1806
1807 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1808 { 0x19, "AT91SAM9xx Series" },
1809 { 0x29, "AT91SAM9XExx Series" },
1810 { 0x34, "AT91x34 Series" },
1811 { 0x37, "CAP7 Series" },
1812 { 0x39, "CAP9 Series" },
1813 { 0x3B, "CAP11 Series" },
1814 { 0x40, "AT91x40 Series" },
1815 { 0x42, "AT91x42 Series" },
1816 { 0x55, "AT91x55 Series" },
1817 { 0x60, "AT91SAM7Axx Series" },
1818 { 0x61, "AT91SAM7AQxx Series" },
1819 { 0x63, "AT91x63 Series" },
1820 { 0x70, "AT91SAM7Sxx Series" },
1821 { 0x71, "AT91SAM7XCxx Series" },
1822 { 0x72, "AT91SAM7SExx Series" },
1823 { 0x73, "AT91SAM7Lxx Series" },
1824 { 0x75, "AT91SAM7Xxx Series" },
1825 { 0x76, "AT91SAM7SLxx Series" },
1826 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1827 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1828 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1829 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1830 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1831 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1832 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1833 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1834 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1835 { 0x92, "AT91x92 Series" },
1836 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1837 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1838 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1839 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1840 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1841 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1842 { 0xA5, "ATSAM5A" },
1843 { 0xF0, "AT75Cxx Series" },
1844 { -1, NULL },
1845 };
1846
1847 static const char *const nvptype[] = {
1848 "rom", /* 0 */
1849 "romless or onchip flash", /* 1 */
1850 "embedded flash memory",/* 2 */
1851 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1852 "sram emulating flash", /* 4 */
1853 _unknown, /* 5 */
1854 _unknown, /* 6 */
1855 _unknown, /* 7 */
1856 };
1857
1858 static const char *_yes_or_no(uint32_t v)
1859 {
1860 if (v)
1861 return "YES";
1862 else
1863 return "NO";
1864 }
1865
1866 static const char *const _rc_freq[] = {
1867 "4 MHz", "8 MHz", "12 MHz", "reserved"
1868 };
1869
1870 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
1871 {
1872 uint32_t v;
1873 uint32_t rcen;
1874
1875 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1876 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
1877 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1878 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
1879 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
1880 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
1881 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1882 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
1883
1884 pChip->cfg.rc_freq = 0;
1885 if (rcen) {
1886 switch (v) {
1887 default:
1888 pChip->cfg.rc_freq = 0;
1889 break;
1890 case 0:
1891 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1892 break;
1893 case 1:
1894 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1895 break;
1896 case 2:
1897 pChip->cfg.rc_freq = 12 * 1000 * 1000;
1898 break;
1899 }
1900 }
1901
1902 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1903 LOG_USER("(startup clks, time= %f uSecs)",
1904 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1905 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1906 LOG_USER("(mainosc source: %s)",
1907 v ? "external xtal" : "internal RC");
1908
1909 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1910 LOG_USER("(clock failure enabled: %s)",
1911 _yes_or_no(v));
1912 }
1913
1914 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
1915 {
1916 int x;
1917 uint32_t v;
1918 const char *cp;
1919
1920 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1921 LOG_USER_N("\n");
1922
1923 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1924 LOG_USER("%s", eproc_names[v]);
1925
1926 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1927 LOG_USER("%s", nvpsize[v]);
1928
1929 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1930 LOG_USER("%s", nvpsize2[v]);
1931
1932 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
1933 LOG_USER("%s", sramsize[v]);
1934
1935 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1936 cp = _unknown;
1937 for (x = 0; archnames[x].name; x++) {
1938 if (v == archnames[x].value) {
1939 cp = archnames[x].name;
1940 break;
1941 }
1942 }
1943
1944 LOG_USER("%s", cp);
1945
1946 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1947 LOG_USER("%s", nvptype[v]);
1948
1949 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1950 LOG_USER("(exists: %s)", _yes_or_no(v));
1951 }
1952
1953 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
1954 {
1955 uint32_t v;
1956
1957 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1958 LOG_USER("(main ready: %s)", _yes_or_no(v));
1959
1960 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1961
1962 v = (v * pChip->cfg.slow_freq) / 16;
1963 pChip->cfg.mainosc_freq = v;
1964
1965 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
1966 _tomhz(v),
1967 pChip->cfg.slow_freq / 1000,
1968 pChip->cfg.slow_freq % 1000);
1969 }
1970
1971 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
1972 {
1973 uint32_t mula, diva;
1974
1975 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1976 LOG_USER_N("\n");
1977 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1978 LOG_USER_N("\n");
1979 pChip->cfg.plla_freq = 0;
1980 if (mula == 0)
1981 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1982 else if (diva == 0)
1983 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1984 else if (diva == 1) {
1985 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
1986 LOG_USER("\tPLLA Freq: %3.03f MHz",
1987 _tomhz(pChip->cfg.plla_freq));
1988 }
1989 }
1990
1991 static void sam3_explain_mckr(struct sam3_chip *pChip)
1992 {
1993 uint32_t css, pres, fin = 0;
1994 int pdiv = 0;
1995 const char *cp = NULL;
1996
1997 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1998 switch (css & 3) {
1999 case 0:
2000 fin = pChip->cfg.slow_freq;
2001 cp = "slowclk";
2002 break;
2003 case 1:
2004 fin = pChip->cfg.mainosc_freq;
2005 cp = "mainosc";
2006 break;
2007 case 2:
2008 fin = pChip->cfg.plla_freq;
2009 cp = "plla";
2010 break;
2011 case 3:
2012 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2013 fin = 480 * 1000 * 1000;
2014 cp = "upll";
2015 } else {
2016 fin = 0;
2017 cp = "upll (*ERROR* UPLL is disabled)";
2018 }
2019 break;
2020 default:
2021 assert(0);
2022 break;
2023 }
2024
2025 LOG_USER("%s (%3.03f Mhz)",
2026 cp,
2027 _tomhz(fin));
2028 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2029 switch (pres & 0x07) {
2030 case 0:
2031 pdiv = 1;
2032 cp = "selected clock";
2033 break;
2034 case 1:
2035 pdiv = 2;
2036 cp = "clock/2";
2037 break;
2038 case 2:
2039 pdiv = 4;
2040 cp = "clock/4";
2041 break;
2042 case 3:
2043 pdiv = 8;
2044 cp = "clock/8";
2045 break;
2046 case 4:
2047 pdiv = 16;
2048 cp = "clock/16";
2049 break;
2050 case 5:
2051 pdiv = 32;
2052 cp = "clock/32";
2053 break;
2054 case 6:
2055 pdiv = 64;
2056 cp = "clock/64";
2057 break;
2058 case 7:
2059 pdiv = 6;
2060 cp = "clock/6";
2061 break;
2062 default:
2063 assert(0);
2064 break;
2065 }
2066 LOG_USER("(%s)", cp);
2067 fin = fin / pdiv;
2068 /* sam3 has a *SINGLE* clock - */
2069 /* other at91 series parts have divisors for these. */
2070 pChip->cfg.cpu_freq = fin;
2071 pChip->cfg.mclk_freq = fin;
2072 pChip->cfg.fclk_freq = fin;
2073 LOG_USER("\t\tResult CPU Freq: %3.03f",
2074 _tomhz(fin));
2075 }
2076
2077 #if 0
2078 static struct sam3_chip *target2sam3(struct target *pTarget)
2079 {
2080 struct sam3_chip *pChip;
2081
2082 if (pTarget == NULL)
2083 return NULL;
2084
2085 pChip = all_sam3_chips;
2086 while (pChip) {
2087 if (pChip->target == pTarget)
2088 break; /* return below */
2089 else
2090 pChip = pChip->next;
2091 }
2092 return pChip;
2093 }
2094 #endif
2095
2096 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2097 {
2098 /* this function exists to help */
2099 /* keep funky offsetof() errors */
2100 /* and casting from causing bugs */
2101
2102 /* By using prototypes - we can detect what would */
2103 /* be casting errors. */
2104
2105 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2106 }
2107
2108
2109 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2110 struct sam3_cfg, \
2111 NAME), # NAME, FUNC }
2112 static const struct sam3_reg_list sam3_all_regs[] = {
2113 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2114 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2115 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2116 SAM3_ENTRY(CKGR_UCKR, NULL),
2117 SAM3_ENTRY(PMC_FSMR, NULL),
2118 SAM3_ENTRY(PMC_FSPR, NULL),
2119 SAM3_ENTRY(PMC_IMR, NULL),
2120 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2121 SAM3_ENTRY(PMC_PCK0, NULL),
2122 SAM3_ENTRY(PMC_PCK1, NULL),
2123 SAM3_ENTRY(PMC_PCK2, NULL),
2124 SAM3_ENTRY(PMC_PCSR, NULL),
2125 SAM3_ENTRY(PMC_SCSR, NULL),
2126 SAM3_ENTRY(PMC_SR, NULL),
2127 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2128 SAM3_ENTRY(CHIPID_EXID, NULL),
2129
2130 /* TERMINATE THE LIST */
2131 { .name = NULL }
2132 };
2133 #undef SAM3_ENTRY
2134
2135 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2136 {
2137 return (struct sam3_bank_private *)(bank->driver_priv);
2138 }
2139
2140 /**
2141 * Given a pointer to where it goes in the structure,
2142 * determine the register name, address from the all registers table.
2143 */
2144 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2145 {
2146 const struct sam3_reg_list *pReg;
2147
2148 pReg = &(sam3_all_regs[0]);
2149 while (pReg->name) {
2150 uint32_t *pPossible;
2151
2152 /* calculate where this one go.. */
2153 /* it is "possibly" this register. */
2154
2155 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2156
2157 /* well? Is it this register */
2158 if (pPossible == goes_here) {
2159 /* Jump for joy! */
2160 return pReg;
2161 }
2162
2163 /* next... */
2164 pReg++;
2165 }
2166 /* This is *TOTAL*PANIC* - we are totally screwed. */
2167 LOG_ERROR("INVALID SAM3 REGISTER");
2168 return NULL;
2169 }
2170
2171 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2172 {
2173 const struct sam3_reg_list *pReg;
2174 int r;
2175
2176 pReg = sam3_GetReg(pChip, goes_here);
2177 if (!pReg)
2178 return ERROR_FAIL;
2179
2180 r = target_read_u32(pChip->target, pReg->address, goes_here);
2181 if (r != ERROR_OK) {
2182 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2183 pReg->name, (unsigned)(pReg->address), r);
2184 }
2185 return r;
2186 }
2187
2188 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2189 {
2190 int r;
2191 const struct sam3_reg_list *pReg;
2192
2193 pReg = &(sam3_all_regs[0]);
2194 while (pReg->name) {
2195 r = sam3_ReadThisReg(pChip,
2196 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2197 if (r != ERROR_OK) {
2198 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2199 pReg->name, ((unsigned)(pReg->address)), r);
2200 return r;
2201 }
2202
2203 pReg++;
2204 }
2205
2206 return ERROR_OK;
2207 }
2208
2209 static int sam3_GetInfo(struct sam3_chip *pChip)
2210 {
2211 const struct sam3_reg_list *pReg;
2212 uint32_t regval;
2213
2214 pReg = &(sam3_all_regs[0]);
2215 while (pReg->name) {
2216 /* display all regs */
2217 LOG_DEBUG("Start: %s", pReg->name);
2218 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2219 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2220 REG_NAME_WIDTH,
2221 pReg->name,
2222 pReg->address,
2223 regval);
2224 if (pReg->explain_func)
2225 (*(pReg->explain_func))(pChip);
2226 LOG_DEBUG("End: %s", pReg->name);
2227 pReg++;
2228 }
2229 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2230 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2231 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2232 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2233 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2234
2235 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2236 pChip->cfg.unique_id[0],
2237 pChip->cfg.unique_id[1],
2238 pChip->cfg.unique_id[2],
2239 pChip->cfg.unique_id[3]);
2240
2241 return ERROR_OK;
2242 }
2243
2244 static int sam3_erase_check(struct flash_bank *bank)
2245 {
2246 int x;
2247
2248 LOG_DEBUG("Here");
2249 if (bank->target->state != TARGET_HALTED) {
2250 LOG_ERROR("Target not halted");
2251 return ERROR_TARGET_NOT_HALTED;
2252 }
2253 if (0 == bank->num_sectors) {
2254 LOG_ERROR("Target: not supported/not probed");
2255 return ERROR_FAIL;
2256 }
2257
2258 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2259 for (x = 0; x < bank->num_sectors; x++)
2260 bank->sectors[x].is_erased = 1;
2261
2262 LOG_DEBUG("Done");
2263 return ERROR_OK;
2264 }
2265
2266 static int sam3_protect_check(struct flash_bank *bank)
2267 {
2268 int r;
2269 uint32_t v = 0;
2270 unsigned x;
2271 struct sam3_bank_private *pPrivate;
2272
2273 LOG_DEBUG("Begin");
2274 if (bank->target->state != TARGET_HALTED) {
2275 LOG_ERROR("Target not halted");
2276 return ERROR_TARGET_NOT_HALTED;
2277 }
2278
2279 pPrivate = get_sam3_bank_private(bank);
2280 if (!pPrivate) {
2281 LOG_ERROR("no private for this bank?");
2282 return ERROR_FAIL;
2283 }
2284 if (!(pPrivate->probed))
2285 return ERROR_FLASH_BANK_NOT_PROBED;
2286
2287 r = FLASHD_GetLockBits(pPrivate, &v);
2288 if (r != ERROR_OK) {
2289 LOG_DEBUG("Failed: %d", r);
2290 return r;
2291 }
2292
2293 for (x = 0; x < pPrivate->nsectors; x++)
2294 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2295 LOG_DEBUG("Done");
2296 return ERROR_OK;
2297 }
2298
2299 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2300 {
2301 struct sam3_chip *pChip;
2302
2303 pChip = all_sam3_chips;
2304
2305 /* is this an existing chip? */
2306 while (pChip) {
2307 if (pChip->target == bank->target)
2308 break;
2309 pChip = pChip->next;
2310 }
2311
2312 if (!pChip) {
2313 /* this is a *NEW* chip */
2314 pChip = calloc(1, sizeof(struct sam3_chip));
2315 if (!pChip) {
2316 LOG_ERROR("NO RAM!");
2317 return ERROR_FAIL;
2318 }
2319 pChip->target = bank->target;
2320 /* insert at head */
2321 pChip->next = all_sam3_chips;
2322 all_sam3_chips = pChip;
2323 pChip->target = bank->target;
2324 /* assumption is this runs at 32khz */
2325 pChip->cfg.slow_freq = 32768;
2326 pChip->probed = 0;
2327 }
2328
2329 switch (bank->base) {
2330 default:
2331 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2332 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2333 "0x%08x [at91sam3n series])",
2334 ((unsigned int)(bank->base)),
2335 ((unsigned int)(FLASH_BANK0_BASE_U)),
2336 ((unsigned int)(FLASH_BANK1_BASE_U)),
2337 ((unsigned int)(FLASH_BANK_BASE_S)),
2338 ((unsigned int)(FLASH_BANK_BASE_N)));
2339 return ERROR_FAIL;
2340 break;
2341
2342 /* at91sam3u series */
2343 case FLASH_BANK0_BASE_U:
2344 bank->driver_priv = &(pChip->details.bank[0]);
2345 bank->bank_number = 0;
2346 pChip->details.bank[0].pChip = pChip;
2347 pChip->details.bank[0].pBank = bank;
2348 break;
2349 case FLASH_BANK1_BASE_U:
2350 bank->driver_priv = &(pChip->details.bank[1]);
2351 bank->bank_number = 1;
2352 pChip->details.bank[1].pChip = pChip;
2353 pChip->details.bank[1].pBank = bank;
2354 break;
2355
2356 /* at91sam3s and at91sam3n series */
2357 case FLASH_BANK_BASE_S:
2358 bank->driver_priv = &(pChip->details.bank[0]);
2359 bank->bank_number = 0;
2360 pChip->details.bank[0].pChip = pChip;
2361 pChip->details.bank[0].pBank = bank;
2362 break;
2363 }
2364
2365 /* we initialize after probing. */
2366 return ERROR_OK;
2367 }
2368
2369 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2370 {
2371 const struct sam3_chip_details *pDetails;
2372 struct sam3_chip *pChip;
2373 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2374 unsigned x;
2375
2376 LOG_DEBUG("Begin");
2377 pDetails = all_sam3_details;
2378 while (pDetails->name) {
2379 /* Compare cidr without version bits */
2380 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2381 break;
2382 else
2383 pDetails++;
2384 }
2385 if (pDetails->name == NULL) {
2386 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2387 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2388 /* Help the victim, print details about the chip */
2389 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2390 pPrivate->pChip->cfg.CHIPID_CIDR);
2391 sam3_explain_chipid_cidr(pPrivate->pChip);
2392 return ERROR_FAIL;
2393 }
2394
2395 /* DANGER: THERE ARE DRAGONS HERE */
2396
2397 /* get our pChip - it is going */
2398 /* to be over-written shortly */
2399 pChip = pPrivate->pChip;
2400
2401 /* Note that, in reality: */
2402 /* */
2403 /* pPrivate = &(pChip->details.bank[0]) */
2404 /* or pPrivate = &(pChip->details.bank[1]) */
2405 /* */
2406
2407 /* save the "bank" pointers */
2408 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2409 saved_banks[x] = pChip->details.bank[x].pBank;
2410
2411 /* Overwrite the "details" structure. */
2412 memcpy(&(pPrivate->pChip->details),
2413 pDetails,
2414 sizeof(pPrivate->pChip->details));
2415
2416 /* now fix the ghosted pointers */
2417 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2418 pChip->details.bank[x].pChip = pChip;
2419 pChip->details.bank[x].pBank = saved_banks[x];
2420 }
2421
2422 /* update the *BANK*SIZE* */
2423
2424 LOG_DEBUG("End");
2425 return ERROR_OK;
2426 }
2427
2428 static int _sam3_probe(struct flash_bank *bank, int noise)
2429 {
2430 unsigned x;
2431 int r;
2432 struct sam3_bank_private *pPrivate;
2433
2434
2435 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2436 if (bank->target->state != TARGET_HALTED) {
2437 LOG_ERROR("Target not halted");
2438 return ERROR_TARGET_NOT_HALTED;
2439 }
2440
2441 pPrivate = get_sam3_bank_private(bank);
2442 if (!pPrivate) {
2443 LOG_ERROR("Invalid/unknown bank number");
2444 return ERROR_FAIL;
2445 }
2446
2447 r = sam3_ReadAllRegs(pPrivate->pChip);
2448 if (r != ERROR_OK)
2449 return r;
2450
2451 LOG_DEBUG("Here");
2452 if (pPrivate->pChip->probed)
2453 r = sam3_GetInfo(pPrivate->pChip);
2454 else
2455 r = sam3_GetDetails(pPrivate);
2456 if (r != ERROR_OK)
2457 return r;
2458
2459 /* update the flash bank size */
2460 for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2461 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2462 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2463 break;
2464 }
2465 }
2466
2467 if (bank->sectors == NULL) {
2468 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2469 if (bank->sectors == NULL) {
2470 LOG_ERROR("No memory!");
2471 return ERROR_FAIL;
2472 }
2473 bank->num_sectors = pPrivate->nsectors;
2474
2475 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2476 bank->sectors[x].size = pPrivate->sector_size;
2477 bank->sectors[x].offset = x * (pPrivate->sector_size);
2478 /* mark as unknown */
2479 bank->sectors[x].is_erased = -1;
2480 bank->sectors[x].is_protected = -1;
2481 }
2482 }
2483
2484 pPrivate->probed = 1;
2485
2486 r = sam3_protect_check(bank);
2487 if (r != ERROR_OK)
2488 return r;
2489
2490 LOG_DEBUG("Bank = %d, nbanks = %d",
2491 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2492 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2493 /* read unique id, */
2494 /* it appears to be associated with the *last* flash bank. */
2495 FLASHD_ReadUniqueID(pPrivate);
2496 }
2497
2498 return r;
2499 }
2500
2501 static int sam3_probe(struct flash_bank *bank)
2502 {
2503 return _sam3_probe(bank, 1);
2504 }
2505
2506 static int sam3_auto_probe(struct flash_bank *bank)
2507 {
2508 return _sam3_probe(bank, 0);
2509 }
2510
2511 static int sam3_erase(struct flash_bank *bank, int first, int last)
2512 {
2513 struct sam3_bank_private *pPrivate;
2514 int r;
2515
2516 LOG_DEBUG("Here");
2517 if (bank->target->state != TARGET_HALTED) {
2518 LOG_ERROR("Target not halted");
2519 return ERROR_TARGET_NOT_HALTED;
2520 }
2521
2522 r = sam3_auto_probe(bank);
2523 if (r != ERROR_OK) {
2524 LOG_DEBUG("Here,r=%d", r);
2525 return r;
2526 }
2527
2528 pPrivate = get_sam3_bank_private(bank);
2529 if (!(pPrivate->probed))
2530 return ERROR_FLASH_BANK_NOT_PROBED;
2531
2532 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2533 /* whole chip */
2534 LOG_DEBUG("Here");
2535 return FLASHD_EraseEntireBank(pPrivate);
2536 }
2537 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2538 return ERROR_OK;
2539 }
2540
2541 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
2542 {
2543 struct sam3_bank_private *pPrivate;
2544 int r;
2545
2546 LOG_DEBUG("Here");
2547 if (bank->target->state != TARGET_HALTED) {
2548 LOG_ERROR("Target not halted");
2549 return ERROR_TARGET_NOT_HALTED;
2550 }
2551
2552 pPrivate = get_sam3_bank_private(bank);
2553 if (!(pPrivate->probed))
2554 return ERROR_FLASH_BANK_NOT_PROBED;
2555
2556 if (set)
2557 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2558 else
2559 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2560 LOG_DEBUG("End: r=%d", r);
2561
2562 return r;
2563
2564 }
2565
2566 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
2567 {
2568 if (bank->target->state != TARGET_HALTED) {
2569 LOG_ERROR("Target not halted");
2570 return ERROR_TARGET_NOT_HALTED;
2571 }
2572 buf[0] = 0;
2573 return ERROR_OK;
2574 }
2575
2576 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2577 {
2578 uint32_t adr;
2579 int r;
2580
2581 adr = pagenum * pPrivate->page_size;
2582 adr += adr + pPrivate->base_address;
2583
2584 r = target_read_memory(pPrivate->pChip->target,
2585 adr,
2586 4, /* THIS*MUST*BE* in 32bit values */
2587 pPrivate->page_size / 4,
2588 buf);
2589 if (r != ERROR_OK)
2590 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
2591 (unsigned int)(adr));
2592 return r;
2593 }
2594
2595 /* The code below is basically this: */
2596 /* compiled with */
2597 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
2598 /* */
2599 /* Only the *CPU* can write to the flash buffer. */
2600 /* the DAP cannot... so - we download this 28byte thing */
2601 /* Run the algorithm - (below) */
2602 /* to program the device */
2603 /* */
2604 /* ======================================== */
2605 /* #include <stdint.h> */
2606 /* */
2607 /* struct foo { */
2608 /* uint32_t *dst; */
2609 /* const uint32_t *src; */
2610 /* int n; */
2611 /* volatile uint32_t *base; */
2612 /* uint32_t cmd; */
2613 /* }; */
2614 /* */
2615 /* */
2616 /* uint32_t sam3_function(struct foo *p) */
2617 /* { */
2618 /* volatile uint32_t *v; */
2619 /* uint32_t *d; */
2620 /* const uint32_t *s; */
2621 /* int n; */
2622 /* uint32_t r; */
2623 /* */
2624 /* d = p->dst; */
2625 /* s = p->src; */
2626 /* n = p->n; */
2627 /* */
2628 /* do { */
2629 /* *d++ = *s++; */
2630 /* } while (--n) */
2631 /* ; */
2632 /* */
2633 /* v = p->base; */
2634 /* */
2635 /* v[ 1 ] = p->cmd; */
2636 /* do { */
2637 /* r = v[8/4]; */
2638 /* } while (!(r&1)) */
2639 /* ; */
2640 /* return r; */
2641 /* } */
2642 /* ======================================== */
2643
2644 static const uint8_t
2645 sam3_page_write_opcodes[] = {
2646 /* 24 0000 0446 mov r4, r0 */
2647 0x04, 0x46,
2648 /* 25 0002 6168 ldr r1, [r4, #4] */
2649 0x61, 0x68,
2650 /* 26 0004 0068 ldr r0, [r0, #0] */
2651 0x00, 0x68,
2652 /* 27 0006 A268 ldr r2, [r4, #8] */
2653 0xa2, 0x68,
2654 /* 28 @ lr needed for prologue */
2655 /* 29 .L2: */
2656 /* 30 0008 51F8043B ldr r3, [r1], #4 */
2657 0x51, 0xf8, 0x04, 0x3b,
2658 /* 31 000c 12F1FF32 adds r2, r2, #-1 */
2659 0x12, 0xf1, 0xff, 0x32,
2660 /* 32 0010 40F8043B str r3, [r0], #4 */
2661 0x40, 0xf8, 0x04, 0x3b,
2662 /* 33 0014 F8D1 bne .L2 */
2663 0xf8, 0xd1,
2664 /* 34 0016 E268 ldr r2, [r4, #12] */
2665 0xe2, 0x68,
2666 /* 35 0018 2369 ldr r3, [r4, #16] */
2667 0x23, 0x69,
2668 /* 36 001a 5360 str r3, [r2, #4] */
2669 0x53, 0x60,
2670 /* 37 001c 0832 adds r2, r2, #8 */
2671 0x08, 0x32,
2672 /* 38 .L4: */
2673 /* 39 001e 1068 ldr r0, [r2, #0] */
2674 0x10, 0x68,
2675 /* 40 0020 10F0010F tst r0, #1 */
2676 0x10, 0xf0, 0x01, 0x0f,
2677 /* 41 0024 FBD0 beq .L4 */
2678 0xfb, 0xd0,
2679 0x00, 0xBE /* bkpt #0 */
2680 };
2681
2682 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2683 {
2684 uint32_t adr;
2685 uint32_t status;
2686 uint32_t fmr; /* EEFC Flash Mode Register */
2687 int r;
2688
2689 adr = pagenum * pPrivate->page_size;
2690 adr += (adr + pPrivate->base_address);
2691
2692 /* Get flash mode register value */
2693 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2694 if (r != ERROR_OK)
2695 LOG_DEBUG("Error Read failed: read flash mode register");
2696
2697 /* Clear flash wait state field */
2698 fmr &= 0xfffff0ff;
2699
2700 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2701 fmr |= (pPrivate->flash_wait_states << 8);
2702
2703 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2704 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2705 if (r != ERROR_OK)
2706 LOG_DEBUG("Error Write failed: set flash mode register");
2707
2708 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2709 r = target_write_memory(pPrivate->pChip->target,
2710 adr,
2711 4, /* THIS*MUST*BE* in 32bit values */
2712 pPrivate->page_size / 4,
2713 buf);
2714 if (r != ERROR_OK) {
2715 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
2716 (unsigned int)(adr));
2717 return r;
2718 }
2719
2720 r = EFC_PerformCommand(pPrivate,
2721 /* send Erase & Write Page */
2722 AT91C_EFC_FCMD_EWP,
2723 pagenum,
2724 &status);
2725
2726 if (r != ERROR_OK)
2727 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
2728 (unsigned int)(adr));
2729 if (status & (1 << 2)) {
2730 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2731 return ERROR_FAIL;
2732 }
2733 if (status & (1 << 1)) {
2734 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2735 return ERROR_FAIL;
2736 }
2737 return ERROR_OK;
2738 }
2739
2740 static int sam3_write(struct flash_bank *bank,
2741 uint8_t *buffer,
2742 uint32_t offset,
2743 uint32_t count)
2744 {
2745 int n;
2746 unsigned page_cur;
2747 unsigned page_end;
2748 int r;
2749 unsigned page_offset;
2750 struct sam3_bank_private *pPrivate;
2751 uint8_t *pagebuffer;
2752
2753 /* incase we bail further below, set this to null */
2754 pagebuffer = NULL;
2755
2756 /* ignore dumb requests */
2757 if (count == 0) {
2758 r = ERROR_OK;
2759 goto done;
2760 }
2761
2762 if (bank->target->state != TARGET_HALTED) {
2763 LOG_ERROR("Target not halted");
2764 r = ERROR_TARGET_NOT_HALTED;
2765 goto done;
2766 }
2767
2768 pPrivate = get_sam3_bank_private(bank);
2769 if (!(pPrivate->probed)) {
2770 r = ERROR_FLASH_BANK_NOT_PROBED;
2771 goto done;
2772 }
2773
2774 if ((offset + count) > pPrivate->size_bytes) {
2775 LOG_ERROR("Flash write error - past end of bank");
2776 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2777 (unsigned int)(offset),
2778 (unsigned int)(count),
2779 (unsigned int)(pPrivate->size_bytes));
2780 r = ERROR_FAIL;
2781 goto done;
2782 }
2783
2784 pagebuffer = malloc(pPrivate->page_size);
2785 if (!pagebuffer) {
2786 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2787 r = ERROR_FAIL;
2788 goto done;
2789 }
2790
2791 /* what page do we start & end in? */
2792 page_cur = offset / pPrivate->page_size;
2793 page_end = (offset + count - 1) / pPrivate->page_size;
2794
2795 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2796 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2797
2798 /* Special case: all one page */
2799 /* */
2800 /* Otherwise: */
2801 /* (1) non-aligned start */
2802 /* (2) body pages */
2803 /* (3) non-aligned end. */
2804
2805 /* Handle special case - all one page. */
2806 if (page_cur == page_end) {
2807 LOG_DEBUG("Special case, all in one page");
2808 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2809 if (r != ERROR_OK)
2810 goto done;
2811
2812 page_offset = (offset & (pPrivate->page_size-1));
2813 memcpy(pagebuffer + page_offset,
2814 buffer,
2815 count);
2816
2817 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2818 if (r != ERROR_OK)
2819 goto done;
2820 r = ERROR_OK;
2821 goto done;
2822 }
2823
2824 /* non-aligned start */
2825 page_offset = offset & (pPrivate->page_size - 1);
2826 if (page_offset) {
2827 LOG_DEBUG("Not-Aligned start");
2828 /* read the partial */
2829 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2830 if (r != ERROR_OK)
2831 goto done;
2832
2833 /* over-write with new data */
2834 n = (pPrivate->page_size - page_offset);
2835 memcpy(pagebuffer + page_offset,
2836 buffer,
2837 n);
2838
2839 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2840 if (r != ERROR_OK)
2841 goto done;
2842
2843 count -= n;
2844 offset += n;
2845 buffer += n;
2846 page_cur++;
2847 }
2848
2849 /* By checking that offset is correct here, we also
2850 fix a clang warning */
2851 assert(offset % pPrivate->page_size == 0);
2852
2853 /* intermediate large pages */
2854 /* also - the final *terminal* */
2855 /* if that terminal page is a full page */
2856 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2857 (int)page_cur, (int)page_end, (unsigned int)(count));
2858
2859 while ((page_cur < page_end) &&
2860 (count >= pPrivate->page_size)) {
2861 r = sam3_page_write(pPrivate, page_cur, buffer);
2862 if (r != ERROR_OK)
2863 goto done;
2864 count -= pPrivate->page_size;
2865 buffer += pPrivate->page_size;
2866 page_cur += 1;
2867 }
2868
2869 /* terminal partial page? */
2870 if (count) {
2871 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2872 /* we have a partial page */
2873 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
2874 if (r != ERROR_OK)
2875 goto done;
2876 /* data goes at start */
2877 memcpy(pagebuffer, buffer, count);
2878 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
2879 if (r != ERROR_OK)
2880 goto done;
2881 buffer += count;
2882 }
2883 LOG_DEBUG("Done!");
2884 r = ERROR_OK;
2885 done:
2886 if (pagebuffer)
2887 free(pagebuffer);
2888 return r;
2889 }
2890
2891 COMMAND_HANDLER(sam3_handle_info_command)
2892 {
2893 struct sam3_chip *pChip;
2894 pChip = get_current_sam3(CMD_CTX);
2895 if (!pChip)
2896 return ERROR_OK;
2897
2898 unsigned x;
2899 int r;
2900
2901 /* bank0 must exist before we can do anything */
2902 if (pChip->details.bank[0].pBank == NULL) {
2903 x = 0;
2904 need_define:
2905 command_print(CMD_CTX,
2906 "Please define bank %d via command: flash bank %s ... ",
2907 x,
2908 at91sam3_flash.name);
2909 return ERROR_FAIL;
2910 }
2911
2912 /* if bank 0 is not probed, then probe it */
2913 if (!(pChip->details.bank[0].probed)) {
2914 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2915 if (r != ERROR_OK)
2916 return ERROR_FAIL;
2917 }
2918 /* above guarantees the "chip details" structure is valid */
2919 /* and thus, bank private areas are valid */
2920 /* and we have a SAM3 chip, what a concept! */
2921
2922 /* auto-probe other banks, 0 done above */
2923 for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
2924 /* skip banks not present */
2925 if (!(pChip->details.bank[x].present))
2926 continue;
2927
2928 if (pChip->details.bank[x].pBank == NULL)
2929 goto need_define;
2930
2931 if (pChip->details.bank[x].probed)
2932 continue;
2933
2934 r = sam3_auto_probe(pChip->details.bank[x].pBank);
2935 if (r != ERROR_OK)
2936 return r;
2937 }
2938
2939 r = sam3_GetInfo(pChip);
2940 if (r != ERROR_OK) {
2941 LOG_DEBUG("Sam3Info, Failed %d", r);
2942 return r;
2943 }
2944
2945 return ERROR_OK;
2946 }
2947
2948 COMMAND_HANDLER(sam3_handle_gpnvm_command)
2949 {
2950 unsigned x, v;
2951 int r, who;
2952 struct sam3_chip *pChip;
2953
2954 pChip = get_current_sam3(CMD_CTX);
2955 if (!pChip)
2956 return ERROR_OK;
2957
2958 if (pChip->target->state != TARGET_HALTED) {
2959 LOG_ERROR("sam3 - target not halted");
2960 return ERROR_TARGET_NOT_HALTED;
2961 }
2962
2963 if (pChip->details.bank[0].pBank == NULL) {
2964 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2965 at91sam3_flash.name);
2966 return ERROR_FAIL;
2967 }
2968 if (!pChip->details.bank[0].probed) {
2969 r = sam3_auto_probe(pChip->details.bank[0].pBank);
2970 if (r != ERROR_OK)
2971 return r;
2972 }
2973
2974 switch (CMD_ARGC) {
2975 default:
2976 return ERROR_COMMAND_SYNTAX_ERROR;
2977 break;
2978 case 0:
2979 goto showall;
2980 break;
2981 case 1:
2982 who = -1;
2983 break;
2984 case 2:
2985 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
2986 who = -1;
2987 else {
2988 uint32_t v32;
2989 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2990 who = v32;
2991 }
2992 break;
2993 }
2994
2995 if (0 == strcmp("show", CMD_ARGV[0])) {
2996 if (who == -1) {
2997 showall:
2998 r = ERROR_OK;
2999 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3000 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3001 if (r != ERROR_OK)
3002 break;
3003 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3004 }
3005 return r;
3006 }
3007 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3008 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3009 command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3010 return r;
3011 } else {
3012 command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3013 return ERROR_COMMAND_SYNTAX_ERROR;
3014 }
3015 }
3016
3017 if (who == -1) {
3018 command_print(CMD_CTX, "Missing GPNVM number");
3019 return ERROR_COMMAND_SYNTAX_ERROR;
3020 }
3021
3022 if (0 == strcmp("set", CMD_ARGV[0]))
3023 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3024 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3025 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3026 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3027 else {
3028 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3029 r = ERROR_COMMAND_SYNTAX_ERROR;
3030 }
3031 return r;
3032 }
3033
3034 COMMAND_HANDLER(sam3_handle_slowclk_command)
3035 {
3036 struct sam3_chip *pChip;
3037
3038 pChip = get_current_sam3(CMD_CTX);
3039 if (!pChip)
3040 return ERROR_OK;
3041
3042 switch (CMD_ARGC) {
3043 case 0:
3044 /* show */
3045 break;
3046 case 1:
3047 {
3048 /* set */
3049 uint32_t v;
3050 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3051 if (v > 200000) {
3052 /* absurd slow clock of 200Khz? */
3053 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3054 return ERROR_COMMAND_SYNTAX_ERROR;
3055 }
3056 pChip->cfg.slow_freq = v;
3057 break;
3058 }
3059 default:
3060 /* error */
3061 command_print(CMD_CTX, "Too many parameters");
3062 return ERROR_COMMAND_SYNTAX_ERROR;
3063 break;
3064 }
3065 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3066 (int)(pChip->cfg.slow_freq / 1000),
3067 (int)(pChip->cfg.slow_freq % 1000));
3068 return ERROR_OK;
3069 }
3070
3071 static const struct command_registration at91sam3_exec_command_handlers[] = {
3072 {
3073 .name = "gpnvm",
3074 .handler = sam3_handle_gpnvm_command,
3075 .mode = COMMAND_EXEC,
3076 .usage = "[('clr'|'set'|'show') bitnum]",
3077 .help = "Without arguments, shows all bits in the gpnvm "
3078 "register. Otherwise, clears, sets, or shows one "
3079 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3080 },
3081 {
3082 .name = "info",
3083 .handler = sam3_handle_info_command,
3084 .mode = COMMAND_EXEC,
3085 .help = "Print information about the current at91sam3 chip"
3086 "and its flash configuration.",
3087 },
3088 {
3089 .name = "slowclk",
3090 .handler = sam3_handle_slowclk_command,
3091 .mode = COMMAND_EXEC,
3092 .usage = "[clock_hz]",
3093 .help = "Display or set the slowclock frequency "
3094 "(default 32768 Hz).",
3095 },
3096 COMMAND_REGISTRATION_DONE
3097 };
3098 static const struct command_registration at91sam3_command_handlers[] = {
3099 {
3100 .name = "at91sam3",
3101 .mode = COMMAND_ANY,
3102 .help = "at91sam3 flash command group",
3103 .usage = "",
3104 .chain = at91sam3_exec_command_handlers,
3105 },
3106 COMMAND_REGISTRATION_DONE
3107 };
3108
3109 struct flash_driver at91sam3_flash = {
3110 .name = "at91sam3",
3111 .commands = at91sam3_command_handlers,
3112 .flash_bank_command = sam3_flash_bank_command,
3113 .erase = sam3_erase,
3114 .protect = sam3_protect,
3115 .write = sam3_write,
3116 .read = default_flash_read,
3117 .probe = sam3_probe,
3118 .auto_probe = sam3_auto_probe,
3119 .erase_check = sam3_erase_check,
3120 .protect_check = sam3_protect_check,
3121 .info = sam3_info,
3122 };
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