1 #################################################################################################
2 # Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
3 # based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
5 # Generated for In-Circuit i.MX53 SO-Dimm ;#
6 #################################################################################################
8 # The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
9 source [find target/imx53.cfg]
10 # Helper for common memory read/modify/write procedures
11 source [find mem_helper.tcl]
13 echo "i.MX53 SO-Dimm board lodaded."
16 #reset_config srst_only
20 # Slow speed to be sure it will work
22 $_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
24 $_TARGETNAME configure -event "reset-assert" {
29 $_TARGETNAME configure -event reset-init { sodimm_init }
31 global AIPS1_BASE_ADDR
32 set AIPS1_BASE_ADDR 0x53F00000
33 global AIPS2_BASE_ADDR
34 set AIPS2_BASE_ADDR 0x63F00000
36 proc sodimm_init { } {
41 echo "HW version [format %x [mrw 0x48]]"
46 ; # ARM errata ID #468414
47 set tR [arm mrc 15 0 1 0 1]
48 arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
57 ; #reg cpsr 0x000001D3
65 # L2CC Cache setup/invalidation/disable
67 ; #/* explicitly disable L2 cache */
68 ; #mrc 15, 0, r0, c1, c0, 1
69 set tR [arm mrc 15 0 1 0 1]
71 ; #mcr 15, 0, r0, c1, c0, 1
72 arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
74 ; #/* reconfigure L2 cache aux control reg */
75 ; #mov r0, #0xC0 /* tag RAM */
76 ; #add r0, r0, #0x4 /* data RAM */
77 ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
78 ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
79 ; #orr r0, r0, #(1 << 22) /* disable write allocate */
81 ; #mcr 15, 1, r0, c9, c0, 2
82 arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
86 # AIPS setup - Only setup MPROTx registers.
87 # The PACR default values are good.
89 ; # Set all MPROTx to be non-bufferable, trusted for R/W,
90 ; # not forced to user-mode.
91 global AIPS1_BASE_ADDR
92 global AIPS2_BASE_ADDR
96 mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
97 mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
98 mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
99 mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
104 proc init_clock { } {
105 global AIPS1_BASE_ADDR
106 global AIPS2_BASE_ADDR
107 set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
109 set CLKCTL_CBCDR 0x14
110 set CLKCTL_CBCMR 0x18
111 set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
112 set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
113 set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
114 set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
115 set CLKCTL_CSCMR1 0x1C
116 set CLKCTL_CDHIPR 0x48
117 set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
118 set CLKCTL_CSCDR1 0x24
121 ; # Switch ARM to step clock
122 mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
126 setup_pll $PLL1_BASE_ADDR 800
127 setup_pll $PLL3_BASE_ADDR 400
129 ; # Switch peripheral to PLL3
130 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
131 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
132 while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
134 setup_pll $PLL2_BASE_ADDR 400
136 ; # Switch peripheral to PLL2
137 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
139 mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
141 ; # change uart clk parent to pll2
142 mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
144 ; # make sure change is effective
145 while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
147 setup_pll $PLL3_BASE_ADDR 216
149 setup_pll $PLL4_BASE_ADDR 455
151 ; # Set the platform clock dividers
152 mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
154 mww [expr $CCM_BASE_ADDR + 0x10] 0
156 ; # Switch ARM back to PLL 1.
157 mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
160 mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
162 ; # Restore the default values in the Gate registers
163 mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
164 mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
165 mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
166 mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
167 mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
168 mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
169 mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
170 mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
172 mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
174 ; # for cko - for ARM div by 8
175 mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
179 proc setup_pll { PLL_ADDR CLK } {
181 set PLL_DP_CONFIG 0x04
183 set PLL_DP_HFS_OP 0x1C
185 set PLL_DP_HFS_MFD 0x20
187 set PLL_DP_HFS_MFN 0x24
190 set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
191 set DP_MFD [expr (12 - 1)]
193 } elseif {$CLK == 850} {
194 set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
195 set DP_MFD [expr (48 - 1)]
197 } elseif {$CLK == 800} {
198 set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
199 set DP_MFD [expr (3 - 1)]
201 } elseif {$CLK == 700} {
202 set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
203 set DP_MFD [expr (24 - 1)]
205 } elseif {$CLK == 600} {
206 set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
207 set DP_MFD [expr (4 - 1)]
209 } elseif {$CLK == 665} {
210 set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
211 set DP_MFD [expr (96 - 1)]
213 } elseif {$CLK == 532} {
214 set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
215 set DP_MFD [expr (24 - 1)]
217 } elseif {$CLK == 455} {
218 set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
219 set DP_MFD [expr (48 - 1)]
221 } elseif {$CLK == 400} {
222 set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
223 set DP_MFD [expr (3 - 1)]
225 } elseif {$CLK == 216} {
226 set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
227 set DP_MFD [expr (4 - 1)]
230 error "Error (setup_dll): clock not found!"
233 mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
234 mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
236 mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
237 mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
239 mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
240 mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
242 mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
243 mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
245 mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
246 while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
250 proc CPU_2_BE_32 { L } {
251 return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
255 # Device Configuration Data
258 #*========================================================================================== ======
259 # Initialization script for 32 bit DDR3 (CS0+CS1)
260 #*========================================================================================== ======
261 # Remux D24/D25 to perform Flash-access
262 mww 0x53fa818C 0x00000000 ; #EIM_RW
263 mww 0x53fa8180 0x00000000 ; #EIM_CS0
264 mww 0x53fa8188 0x00000000 ; #EIM_OE
265 mww 0x53fa817C 0x00000000 ; #A16
266 mww 0x53fa8178 0x00000000 ; #A17
267 mww 0x53fa8174 0x00000000 ; #A18
268 mww 0x53fa8170 0x00000000 ; #A19
269 mww 0x53fa816C 0x00000000 ; #A20
270 mww 0x53fa8168 0x00000000 ; #A21
271 mww 0x53fa819C 0x00000000 ; #DA0
272 mww 0x53fa81A0 0x00000000 ; #DA1
273 mww 0x53fa81A4 0x00000000 ; #DA2
274 mww 0x53fa81A8 0x00000000 ; #DA3
275 mww 0x53fa81AC 0x00000000 ; #DA4
276 mww 0x53fa81B0 0x00000000 ; #DA5
277 mww 0x53fa81B4 0x00000000 ; #DA6
278 mww 0x53fa81B8 0x00000000 ; #DA7
279 mww 0x53fa81BC 0x00000000 ; #DA8
280 mww 0x53fa81C0 0x00000000 ; #DA9
281 mww 0x53fa81C4 0x00000000 ; #DA10
282 mww 0x53fa81C8 0x00000000 ; #DA11
283 mww 0x53fa81CC 0x00000000 ; #DA12
284 mww 0x53fa81D0 0x00000000 ; #DA13
285 mww 0x53fa81D4 0x00000000 ; #DA14
286 mww 0x53fa81D8 0x00000000 ; #DA15
287 mww 0x53fa8118 0x00000000 ; #D16
288 mww 0x53fa811C 0x00000000 ; #D17
289 mww 0x53fa8120 0x00000000 ; #D18
290 mww 0x53fa8124 0x00000000 ; #D19
291 mww 0x53fa8128 0x00000000 ; #D20
292 mww 0x53fa812C 0x00000000 ; #D21
293 mww 0x53fa8130 0x00000000 ; #D22
294 mww 0x53fa8134 0x00000000 ; #D23
295 mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
296 mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
297 mww 0x53fa8144 0x00000000 ; #D26
298 mww 0x53fa8148 0x00000000 ; #D27
299 mww 0x53fa814C 0x00000000 ; #D28
300 mww 0x53fa8150 0x00000000 ; #D29
301 mww 0x53fa8154 0x00000000 ; #D30
302 mww 0x53fa8158 0x00000000 ; #D31
304 # DDR3 IOMUX configuration
305 #* Global pad control options */
306 mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
307 mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
308 mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
309 mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
310 mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
311 mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
312 mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
313 mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
314 mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
315 mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
316 mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
317 mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
318 mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
319 mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
320 mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
321 mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
322 mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
323 # mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
324 mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
325 mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
326 mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
327 mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
328 mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
329 mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
330 mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
331 # mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
332 # mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
333 # mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
334 # mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
336 #* Data bus byte lane pad drive strength control options */
337 # mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
338 # mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
339 # mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
340 # mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
341 # mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
342 # mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
343 # mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
344 # mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
345 # mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
346 # mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
347 # mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
348 # mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
350 #* SDCLK pad drive strength control options */
351 # mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
352 # mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
354 #* Control and addr bus pad drive strength control options */
355 # mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
356 # mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
357 # mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
358 # mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
360 # mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
361 # mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
363 # Initialize DDR3 memory - Micron MT41J128M16-187Er
364 #** Keep for now, same setting as CPU3 board **#
365 mww 0x63fd901c 0x00008000
366 # mww 0x63fd904c 0x01680172 ; #write leveling reg 0
367 # mww 0x63fd9050 0x0021017f ; #write leveling reg 1
368 mww 0x63fd9088 0x32383535 ; #read delay lines
369 mww 0x63fd9090 0x40383538 ; #write delay lines
370 # mww 0x63fd90F8 0x00000800 ; #Measure unit
371 mww 0x63fd907c 0x0136014d ; #DQS gating 0
372 mww 0x63fd9080 0x01510141 ; #DQS gating 1
373 #* CPU3 Board settingr
374 # Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
375 # mww 0x63fd9018 0x00091740 ; #Misc register:
376 #* Quick Silver board setting
377 # Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
378 mww 0x63fd9018 0x00011740 ; #Misc register
380 # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
381 # mww 0x63fd9000 0xc3190000 ; #Main control register
382 # Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
383 mww 0x63fd9000 0x83190000 ; #Main control register
384 # tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
385 mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
386 # tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
387 mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
388 # tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
389 mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
390 mww 0x63fd902c 0x000026d2 ; #command delay (default)
391 mww 0x63fd9030 0x009f0e21 ; #out of reset delays
392 # Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
393 mww 0x63fd9008 0x12273030 ; #ODT timings
394 # tCKE=3; tCKSRX=5; tCKSRE=5
395 mww 0x63fd9004 0x0002002d
397 #**********************************
398 #DDR device configuration:
399 #**********************************
400 #**********************************
402 #**********************************
403 mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
404 # Full array self refresh
405 # Rtt_WR disabled (no ODT at IO CMOS operation)
406 # Manual self refresh
408 mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
409 mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
410 # out impedance = RZQ/7
411 # Rtt_nom disabled (no ODT at IO CMOS operation)
412 # Aditive latency off
413 # write leveling disabled
414 # tdqs (differential?) disabled
416 mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
417 mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
418 #**********************************
420 #**********************************
421 # mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
422 # mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
423 # mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
424 # mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
425 # mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
426 #**********************************
429 mww 0x63fd9020 0x00001800 ; # Refresh control register
430 mww 0x63fd9040 0x04b80003 ; # ZQ HW control
431 mww 0x63fd9058 0x00022227 ; # ODT control register
433 mww 0x63fd901c 0x00000000
435 # CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
438 # mww 0x53FD4060 0x01e900f0
444 $_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
446 flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME