1 # Renesas R-Car Generation 3 SOCs
2 # - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC
3 # - Each SOC can boot through any of the, up to 3, core types that it has
4 # e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7
6 # Supported Gen3 SOCs and their cores:
7 # H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
8 # M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
9 # M3N: Cortex-A57 x 2, Cortex-R7 x 2 (Lock-Step)
10 # V3H: Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
11 # V3M: Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
12 # E3: Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
16 # There are 2 configuration options:
17 # SOC: Selects the supported SOC. (Default 'H3')
18 # BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7'
19 # Defaults to 'CA57' if the SOC has one, else defaults to 'CA53'
21 if { [info exists SOC] } {
27 # Set configuration for each SOC and the default 'BOOT_CORE'
30 set _CHIPNAME r8a77950
37 set _CHIPNAME r8a77960
44 set _CHIPNAME r8a77965
51 set _CHIPNAME r8a77970
58 set _CHIPNAME r8a77980
65 set _CHIPNAME r8a77990
72 set _CHIPNAME r8a77995
79 echo "'$_soc' is invalid!"
83 # If configured, override the default 'CHIPNAME'
84 if { [info exists CHIPNAME] } {
85 set _CHIPNAME $CHIPNAME
88 # If configured, override the default 'BOOT_CORE'
89 if { [info exists BOOT_CORE] } {
90 set _boot_core $BOOT_CORE
93 if { [info exists DAP_TAPID] } {
94 set _DAP_TAPID $DAP_TAPID
96 set _DAP_TAPID 0x5ba00477
99 echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s)"
100 echo "\tBoot Core - $_boot_core\n"
102 set _DAPNAME $_CHIPNAME.dap
105 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
106 dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
108 set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
109 set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
110 set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
111 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
112 set CR7_DBGBASE 0x80910000
113 set CR7_CTIBASE 0x80918000
117 proc setup_a5x {core_name dbgbase ctibase num boot} {
121 for { set _core 0 } { $_core < $num } { incr _core } {
122 set _TARGETNAME $_CHIPNAME.$core_name.$_core
123 set _CTINAME $_TARGETNAME.cti
124 cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \
125 -ctibase [lindex $ctibase $_core]
126 set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \
127 -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME"
128 if { $_core == 0 && $boot == 1 } {
129 set _targets "$_TARGETNAME"
131 set _command "$_command -defer-examine"
133 set smp_targets "$smp_targets $_TARGETNAME"
138 proc setup_cr7 {dbgbase ctibase boot} {
141 set _TARGETNAME $_CHIPNAME.r7
142 set _CTINAME $_TARGETNAME.cti
143 cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -ctibase $ctibase
144 set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
145 -ap-num 1 -dbgbase $dbgbase"
147 set _targets "$_TARGETNAME"
149 set _command "$_command -defer-examine"
154 # Organize target list based on the boot core
155 if { [string equal $_boot_core CA57] } {
156 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
157 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
158 setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
159 } elseif { [string equal $_boot_core CA53] } {
160 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
161 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
162 setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 0
164 setup_cr7 $CR7_DBGBASE $CR7_CTIBASE 1
165 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
166 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
169 eval "target smp $smp_targets"