1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 #include "arm_disassembler.h"
32 #include "binarybuffer.h"
35 bitfield_desc_t armv4_5_psr_bitfield_desc
[] =
51 char* armv4_5_core_reg_list
[] =
53 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
55 "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
65 "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
68 char * armv4_5_mode_strings_list
[] =
70 "Illegal mode value", "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
73 /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
74 char** armv4_5_mode_strings
= armv4_5_mode_strings_list
+1;
76 char* armv4_5_state_strings
[] =
78 "ARM", "Thumb", "Jazelle"
81 int armv4_5_core_reg_arch_type
= -1;
83 armv4_5_core_reg_t armv4_5_core_reg_list_arch_info
[] =
85 {0, ARMV4_5_MODE_ANY
, NULL
, NULL
},
86 {1, ARMV4_5_MODE_ANY
, NULL
, NULL
},
87 {2, ARMV4_5_MODE_ANY
, NULL
, NULL
},
88 {3, ARMV4_5_MODE_ANY
, NULL
, NULL
},
89 {4, ARMV4_5_MODE_ANY
, NULL
, NULL
},
90 {5, ARMV4_5_MODE_ANY
, NULL
, NULL
},
91 {6, ARMV4_5_MODE_ANY
, NULL
, NULL
},
92 {7, ARMV4_5_MODE_ANY
, NULL
, NULL
},
93 {8, ARMV4_5_MODE_ANY
, NULL
, NULL
},
94 {9, ARMV4_5_MODE_ANY
, NULL
, NULL
},
95 {10, ARMV4_5_MODE_ANY
, NULL
, NULL
},
96 {11, ARMV4_5_MODE_ANY
, NULL
, NULL
},
97 {12, ARMV4_5_MODE_ANY
, NULL
, NULL
},
98 {13, ARMV4_5_MODE_USR
, NULL
, NULL
},
99 {14, ARMV4_5_MODE_USR
, NULL
, NULL
},
100 {15, ARMV4_5_MODE_ANY
, NULL
, NULL
},
102 {8, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
103 {9, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
104 {10, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
105 {11, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
106 {12, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
107 {13, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
108 {14, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
110 {13, ARMV4_5_MODE_IRQ
, NULL
, NULL
},
111 {14, ARMV4_5_MODE_IRQ
, NULL
, NULL
},
113 {13, ARMV4_5_MODE_SVC
, NULL
, NULL
},
114 {14, ARMV4_5_MODE_SVC
, NULL
, NULL
},
116 {13, ARMV4_5_MODE_ABT
, NULL
, NULL
},
117 {14, ARMV4_5_MODE_ABT
, NULL
, NULL
},
119 {13, ARMV4_5_MODE_UND
, NULL
, NULL
},
120 {14, ARMV4_5_MODE_UND
, NULL
, NULL
},
122 {16, ARMV4_5_MODE_ANY
, NULL
, NULL
},
123 {16, ARMV4_5_MODE_FIQ
, NULL
, NULL
},
124 {16, ARMV4_5_MODE_IRQ
, NULL
, NULL
},
125 {16, ARMV4_5_MODE_SVC
, NULL
, NULL
},
126 {16, ARMV4_5_MODE_ABT
, NULL
, NULL
},
127 {16, ARMV4_5_MODE_UND
, NULL
, NULL
}
130 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
131 int armv4_5_core_reg_map
[7][17] =
134 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
137 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
140 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
143 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
146 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
149 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
152 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
156 u8 armv4_5_gdb_dummy_fp_value
[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
158 reg_t armv4_5_gdb_dummy_fp_reg
=
160 "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value
, 0, 1, 96, NULL
, 0, NULL
, 0
163 u8 armv4_5_gdb_dummy_fps_value
[] = {0, 0, 0, 0};
165 reg_t armv4_5_gdb_dummy_fps_reg
=
167 "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value
, 0, 1, 32, NULL
, 0, NULL
, 0
170 int armv4_5_get_core_reg(reg_t
*reg
)
173 armv4_5_core_reg_t
*armv4_5
= reg
->arch_info
;
174 target_t
*target
= armv4_5
->target
;
176 if (target
->state
!= TARGET_HALTED
)
178 LOG_ERROR("Target not halted");
179 return ERROR_TARGET_NOT_HALTED
;
182 /* retval = armv4_5->armv4_5_common->full_context(target); */
183 retval
= armv4_5
->armv4_5_common
->read_core_reg(target
, armv4_5
->num
, armv4_5
->mode
);
188 int armv4_5_set_core_reg(reg_t
*reg
, u8
*buf
)
190 armv4_5_core_reg_t
*armv4_5
= reg
->arch_info
;
191 target_t
*target
= armv4_5
->target
;
192 armv4_5_common_t
*armv4_5_target
= target
->arch_info
;
193 u32 value
= buf_get_u32(buf
, 0, 32);
195 if (target
->state
!= TARGET_HALTED
)
197 return ERROR_TARGET_NOT_HALTED
;
200 if (reg
== &armv4_5_target
->core_cache
->reg_list
[ARMV4_5_CPSR
])
204 /* T bit should be set */
205 if (armv4_5_target
->core_state
== ARMV4_5_STATE_ARM
)
207 /* change state to Thumb */
208 LOG_DEBUG("changing to Thumb state");
209 armv4_5_target
->core_state
= ARMV4_5_STATE_THUMB
;
214 /* T bit should be cleared */
215 if (armv4_5_target
->core_state
== ARMV4_5_STATE_THUMB
)
217 /* change state to ARM */
218 LOG_DEBUG("changing to ARM state");
219 armv4_5_target
->core_state
= ARMV4_5_STATE_ARM
;
223 if (armv4_5_target
->core_mode
!= (enum armv4_5_mode
)(value
& 0x1f))
225 LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings
[armv4_5_mode_to_number(value
& 0x1f)]);
226 armv4_5_target
->core_mode
= value
& 0x1f;
227 armv4_5_target
->write_core_reg(target
, 16, ARMV4_5_MODE_ANY
, value
);
231 buf_set_u32(reg
->value
, 0, 32, value
);
238 int armv4_5_invalidate_core_regs(target_t
*target
)
240 armv4_5_common_t
*armv4_5
= target
->arch_info
;
243 for (i
= 0; i
< 37; i
++)
245 armv4_5
->core_cache
->reg_list
[i
].valid
= 0;
246 armv4_5
->core_cache
->reg_list
[i
].dirty
= 0;
252 reg_cache_t
* armv4_5_build_reg_cache(target_t
*target
, armv4_5_common_t
*armv4_5_common
)
255 reg_cache_t
*cache
= malloc(sizeof(reg_cache_t
));
256 reg_t
*reg_list
= malloc(sizeof(reg_t
) * num_regs
);
257 armv4_5_core_reg_t
*arch_info
= malloc(sizeof(armv4_5_core_reg_t
) * num_regs
);
260 cache
->name
= "arm v4/5 registers";
262 cache
->reg_list
= reg_list
;
263 cache
->num_regs
= num_regs
;
265 if (armv4_5_core_reg_arch_type
== -1)
266 armv4_5_core_reg_arch_type
= register_reg_arch_type(armv4_5_get_core_reg
, armv4_5_set_core_reg
);
268 register_init_dummy(&armv4_5_gdb_dummy_fp_reg
);
269 register_init_dummy(&armv4_5_gdb_dummy_fps_reg
);
271 for (i
= 0; i
< 37; i
++)
273 arch_info
[i
] = armv4_5_core_reg_list_arch_info
[i
];
274 arch_info
[i
].target
= target
;
275 arch_info
[i
].armv4_5_common
= armv4_5_common
;
276 reg_list
[i
].name
= armv4_5_core_reg_list
[i
];
277 reg_list
[i
].size
= 32;
278 reg_list
[i
].value
= calloc(1, 4);
279 reg_list
[i
].dirty
= 0;
280 reg_list
[i
].valid
= 0;
281 reg_list
[i
].bitfield_desc
= NULL
;
282 reg_list
[i
].num_bitfields
= 0;
283 reg_list
[i
].arch_type
= armv4_5_core_reg_arch_type
;
284 reg_list
[i
].arch_info
= &arch_info
[i
];
290 int armv4_5_arch_state(struct target_s
*target
)
292 armv4_5_common_t
*armv4_5
= target
->arch_info
;
294 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
296 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
300 LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
301 armv4_5_state_strings
[armv4_5
->core_state
],
302 Jim_Nvp_value2name_simple( nvp_target_debug_reason
, target
->debug_reason
)->name
,
303 armv4_5_mode_strings
[armv4_5_mode_to_number(armv4_5
->core_mode
)],
304 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
305 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
310 int handle_armv4_5_reg_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
315 target_t
*target
= get_current_target(cmd_ctx
);
316 armv4_5_common_t
*armv4_5
= target
->arch_info
;
318 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
320 command_print(cmd_ctx
, "current target isn't an ARMV4/5 target");
324 if (target
->state
!= TARGET_HALTED
)
326 command_print(cmd_ctx
, "error: target must be halted for register accesses");
330 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
333 for (num
= 0; num
<= 15; num
++)
336 for (mode
= 0; mode
< 6; mode
++)
338 if (!ARMV4_5_CORE_REG_MODENUM(armv4_5
->core_cache
, mode
, num
).valid
)
340 armv4_5
->full_context(target
);
342 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5
->core_cache
, mode
, num
).name
,
343 buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5
->core_cache
, mode
, num
).value
, 0, 32));
345 command_print(cmd_ctx
, "%s", output
);
347 command_print(cmd_ctx
, " cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
348 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32),
349 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_SPSR_FIQ
].value
, 0, 32),
350 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_SPSR_IRQ
].value
, 0, 32),
351 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_SPSR_SVC
].value
, 0, 32),
352 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_SPSR_ABT
].value
, 0, 32),
353 buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_SPSR_UND
].value
, 0, 32));
358 int handle_armv4_5_core_state_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
360 target_t
*target
= get_current_target(cmd_ctx
);
361 armv4_5_common_t
*armv4_5
= target
->arch_info
;
363 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
365 command_print(cmd_ctx
, "current target isn't an ARMV4/5 target");
371 if (strcmp(args
[0], "arm") == 0)
373 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
375 if (strcmp(args
[0], "thumb") == 0)
377 armv4_5
->core_state
= ARMV4_5_STATE_THUMB
;
381 command_print(cmd_ctx
, "core state: %s", armv4_5_state_strings
[armv4_5
->core_state
]);
386 int handle_armv4_5_disassemble_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
388 int retval
= ERROR_OK
;
389 target_t
*target
= get_current_target(cmd_ctx
);
390 armv4_5_common_t
*armv4_5
= target
->arch_info
;
394 arm_instruction_t cur_instruction
;
399 if (armv4_5
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
401 command_print(cmd_ctx
, "current target isn't an ARMV4/5 target");
407 command_print(cmd_ctx
, "usage: armv4_5 disassemble <address> <count> ['thumb']");
411 address
= strtoul(args
[0], NULL
, 0);
412 count
= strtoul(args
[1], NULL
, 0);
415 if (strcmp(args
[2], "thumb") == 0)
418 for (i
= 0; i
< count
; i
++)
422 if ((retval
= target_read_u16(target
, address
, &thumb_opcode
)) != ERROR_OK
)
426 if ((retval
= thumb_evaluate_opcode(thumb_opcode
, address
, &cur_instruction
)) != ERROR_OK
)
432 if ((retval
= target_read_u32(target
, address
, &opcode
)) != ERROR_OK
)
436 if ((retval
= arm_evaluate_opcode(opcode
, address
, &cur_instruction
)) != ERROR_OK
)
441 command_print(cmd_ctx
, "%s", cur_instruction
.text
);
442 address
+= (thumb
) ? 2 : 4;
448 int armv4_5_register_commands(struct command_context_s
*cmd_ctx
)
450 command_t
*armv4_5_cmd
;
452 armv4_5_cmd
= register_command(cmd_ctx
, NULL
, "armv4_5", NULL
, COMMAND_ANY
, "armv4/5 specific commands");
454 register_command(cmd_ctx
, armv4_5_cmd
, "reg", handle_armv4_5_reg_command
, COMMAND_EXEC
, "display ARM core registers");
455 register_command(cmd_ctx
, armv4_5_cmd
, "core_state", handle_armv4_5_core_state_command
, COMMAND_EXEC
, "display/change ARM core state <arm|thumb>");
457 register_command(cmd_ctx
, armv4_5_cmd
, "disassemble", handle_armv4_5_disassemble_command
, COMMAND_EXEC
, "disassemble instructions <address> <count> ['thumb']");
461 int armv4_5_get_gdb_reg_list(target_t
*target
, reg_t
**reg_list
[], int *reg_list_size
)
463 armv4_5_common_t
*armv4_5
= target
->arch_info
;
466 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
470 *reg_list
= malloc(sizeof(reg_t
*) * (*reg_list_size
));
472 for (i
= 0; i
< 16; i
++)
474 (*reg_list
)[i
] = &ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5
->core_mode
, i
);
477 for (i
= 16; i
< 24; i
++)
479 (*reg_list
)[i
] = &armv4_5_gdb_dummy_fp_reg
;
482 (*reg_list
)[24] = &armv4_5_gdb_dummy_fps_reg
;
483 (*reg_list
)[25] = &armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
];
488 /* wait for execution to complete and check exit point */
489 static int armv4_5_run_algorithm_completion(struct target_s
*target
, u32 exit_point
, int timeout_ms
, void *arch_info
)
492 armv4_5_common_t
*armv4_5
= target
->arch_info
;
494 if ((retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
)) != ERROR_OK
)
498 if (target
->state
!= TARGET_HALTED
)
500 if ((retval
=target_halt(target
))!=ERROR_OK
)
502 if ((retval
=target_wait_state(target
, TARGET_HALTED
, 500))!=ERROR_OK
)
506 return ERROR_TARGET_TIMEOUT
;
508 if (buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32) != exit_point
)
510 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
511 buf_get_u32(armv4_5
->core_cache
->reg_list
[15].value
, 0, 32));
512 return ERROR_TARGET_TIMEOUT
;
518 int armv4_5_run_algorithm_inner(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
, int (*run_it
)(struct target_s
*target
, u32 exit_point
, int timeout_ms
, void *arch_info
))
520 armv4_5_common_t
*armv4_5
= target
->arch_info
;
521 armv4_5_algorithm_t
*armv4_5_algorithm_info
= arch_info
;
522 enum armv4_5_state core_state
= armv4_5
->core_state
;
523 enum armv4_5_mode core_mode
= armv4_5
->core_mode
;
526 int exit_breakpoint_size
= 0;
528 int retval
= ERROR_OK
;
529 LOG_DEBUG("Running algorithm");
531 if (armv4_5_algorithm_info
->common_magic
!= ARMV4_5_COMMON_MAGIC
)
533 LOG_ERROR("current target isn't an ARMV4/5 target");
534 return ERROR_TARGET_INVALID
;
537 if (target
->state
!= TARGET_HALTED
)
539 LOG_WARNING("target not halted");
540 return ERROR_TARGET_NOT_HALTED
;
543 if (armv4_5_mode_to_number(armv4_5
->core_mode
)==-1)
546 for (i
= 0; i
<= 16; i
++)
548 if (!ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).valid
)
549 armv4_5
->read_core_reg(target
, i
, armv4_5_algorithm_info
->core_mode
);
550 context
[i
] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).value
, 0, 32);
552 cpsr
= buf_get_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32);
554 for (i
= 0; i
< num_mem_params
; i
++)
556 if ((retval
= target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
562 for (i
= 0; i
< num_reg_params
; i
++)
564 reg_t
*reg
= register_get_by_name(armv4_5
->core_cache
, reg_params
[i
].reg_name
, 0);
567 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
571 if (reg
->size
!= reg_params
[i
].size
)
573 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
577 if ((retval
= armv4_5_set_core_reg(reg
, reg_params
[i
].value
)) != ERROR_OK
)
583 armv4_5
->core_state
= armv4_5_algorithm_info
->core_state
;
584 if (armv4_5
->core_state
== ARMV4_5_STATE_ARM
)
585 exit_breakpoint_size
= 4;
586 else if (armv4_5
->core_state
== ARMV4_5_STATE_THUMB
)
587 exit_breakpoint_size
= 2;
590 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
594 if (armv4_5_algorithm_info
->core_mode
!= ARMV4_5_MODE_ANY
)
596 LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info
->core_mode
);
597 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 5, armv4_5_algorithm_info
->core_mode
);
598 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
599 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
602 if ((retval
= breakpoint_add(target
, exit_point
, exit_breakpoint_size
, BKPT_HARD
)) != ERROR_OK
)
604 LOG_ERROR("can't add breakpoint to finish algorithm execution");
605 return ERROR_TARGET_FAILURE
;
608 if ((retval
= target_resume(target
, 0, entry_point
, 1, 1)) != ERROR_OK
)
613 retval
=run_it(target
, exit_point
, timeout_ms
, arch_info
);
615 breakpoint_remove(target
, exit_point
);
617 if (retval
!=ERROR_OK
)
620 for (i
= 0; i
< num_mem_params
; i
++)
622 if (mem_params
[i
].direction
!= PARAM_OUT
)
623 if ((retvaltemp
= target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
629 for (i
= 0; i
< num_reg_params
; i
++)
631 if (reg_params
[i
].direction
!= PARAM_OUT
)
634 reg_t
*reg
= register_get_by_name(armv4_5
->core_cache
, reg_params
[i
].reg_name
, 0);
637 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
641 if (reg
->size
!= reg_params
[i
].size
)
643 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
647 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
651 for (i
= 0; i
<= 16; i
++)
654 regvalue
= buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).value
, 0, 32);
655 if (regvalue
!= context
[i
])
657 LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).name
, context
[i
]);
658 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).value
, 0, 32, context
[i
]);
659 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).valid
= 1;
660 ARMV4_5_CORE_REG_MODE(armv4_5
->core_cache
, armv4_5_algorithm_info
->core_mode
, i
).dirty
= 1;
663 buf_set_u32(armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].value
, 0, 32, cpsr
);
664 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].valid
= 1;
665 armv4_5
->core_cache
->reg_list
[ARMV4_5_CPSR
].dirty
= 1;
667 armv4_5
->core_state
= core_state
;
668 armv4_5
->core_mode
= core_mode
;
673 int armv4_5_run_algorithm(struct target_s
*target
, int num_mem_params
, mem_param_t
*mem_params
, int num_reg_params
, reg_param_t
*reg_params
, u32 entry_point
, u32 exit_point
, int timeout_ms
, void *arch_info
)
675 return armv4_5_run_algorithm_inner(target
, num_mem_params
, mem_params
, num_reg_params
, reg_params
, entry_point
, exit_point
, timeout_ms
, arch_info
, armv4_5_run_algorithm_completion
);
678 int armv4_5_init_arch_info(target_t
*target
, armv4_5_common_t
*armv4_5
)
680 target
->arch_info
= armv4_5
;
682 armv4_5
->common_magic
= ARMV4_5_COMMON_MAGIC
;
683 armv4_5
->core_state
= ARMV4_5_STATE_ARM
;
684 armv4_5
->core_mode
= ARMV4_5_MODE_USR
;