1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32l5x family
6 # stm32l5 devices support both JTAG and SWD transports.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32l5x
19 # Work-area is a space in RAM used for flash programming
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x10000
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
32 # See STM Document RM0438
33 # RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
34 # Corresponds to Cortex®-M33 JTAG debug port ID code
35 set _CPUTAPID 0x0ba04477
37 # SWD IDCODE (single drop, arm)
38 set _CPUTAPID 0x0be12477
42 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
43 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
46 jtag newtap $_CHIPNAME bs -irlen 5
49 set _TARGETNAME $_CHIPNAME.cpu
50 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
52 # use non-secure RAM by default
53 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
55 # declare non-secure flash
56 flash bank $_CHIPNAME.flash_ns stm32l4x 0 0 0 0 $_TARGETNAME
58 # Common knowledges tells JTAG speed should be <= F_CPU/6.
59 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
62 # Note that there is a pretty wide band where things are
63 # more or less stable, see http://openocd.zylin.com/#/c/3366/
66 adapter srst delay 100
71 reset_config srst_nogate
74 # if srst is not fitted use SYSRESETREQ to
75 # perform a soft reset
76 cortex_m reset_config sysresetreq
79 proc clock_config_110_mhz {} {
80 # MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
81 # RCC_APB1ENR1 = PWREN
82 mww 0x40021058 0x10000000
83 # delay for register clock enable (read back reg)
85 # PWR_CR1 : VOS Range 0
87 # while (PWR_SR2 & VOSF)
88 while {([mrw 0x40007014] & 0x0400)} {}
89 # FLASH_ACR : 5 WS for 110 MHz HCLK
90 mww 0x40022000 0x00000005
91 # RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
92 # fVCO = 4 x 55 /1 = 220
93 # SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
94 mww 0x4002100C 0x01003711
96 mmw 0x40021000 0x01000000 0
97 # while !(RCC_CR & PLLRDY)
98 while {!([mrw 0x40021000] & 0x02000000)} {}
100 mmw 0x40021008 0x00000003 0
101 # while ((RCC_CFGR & SWS) != PLL)
102 while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
105 $_TARGETNAME configure -event reset-init {
107 # Boost JTAG frequency
111 $_TARGETNAME configure -event reset-start {
112 # Reset clock is MSI (4 MHz)
116 $_TARGETNAME configure -event examine-end {
117 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
118 mmw 0xE0044004 0x00000006 0
120 # Stop watchdog counters during halt
121 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
122 mmw 0xE0044008 0x00001800 0
125 $_TARGETNAME configure -event trace-config {
126 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
127 # change this value accordingly to configure trace pins
129 mmw 0xE0044004 0x00000020 0