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aarch64: use symbolic opcodes instead of hex values
[openocd.git] / src / flash / nand / mx3.c
blobb61e47535fbf5bb5363302798d63c0712845a80e
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20
21 /*
22 * Freescale iMX3* OpenOCD NAND Flash controller support.
23 *
24 * Many thanks to Ben Dooks for writing s3c24xx driver.
25 */
26
27 /*
28 driver tested with STMicro NAND512W3A @imx31
29 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
30 get_next_halfword_from_sram_buffer() not tested
31 */
32 #ifdef HAVE_CONFIG_H
33 #include "config.h"
34 #endif
35
36 #include "imp.h"
37 #include "mx3.h"
38 #include <target/target.h>
39
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %" PRId32 " is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
46 static const char get_status_register_err_msg[] = "can't get NAND status";
47 static uint32_t in_sram_address;
48 static unsigned char sign_of_sequental_byte_read;
49
50 static int test_iomux_settings(struct target *target, uint32_t value,
51 uint32_t mask, const char *text);
52 static int initialize_nf_controller(struct nand_device *nand);
53 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value);
54 static int get_next_halfword_from_sram_buffer(struct target *target,
55 uint16_t *value);
56 static int poll_for_complete_op(struct target *target, const char *text);
57 static int validate_target_state(struct nand_device *nand);
58 static int do_data_output(struct nand_device *nand);
59
60 static int imx31_command(struct nand_device *nand, uint8_t command);
61 static int imx31_address(struct nand_device *nand, uint8_t address);
62
63 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command)
64 {
65 struct mx3_nf_controller *mx3_nf_info;
66 mx3_nf_info = malloc(sizeof(struct mx3_nf_controller));
67 if (mx3_nf_info == NULL) {
68 LOG_ERROR("no memory for nand controller");
69 return ERROR_FAIL;
70 }
71
72 nand->controller_priv = mx3_nf_info;
73
74 if (CMD_ARGC < 3)
75 return ERROR_COMMAND_SYNTAX_ERROR;
76 /*
77 * check hwecc requirements
78 */
79 {
80 int hwecc_needed;
81 hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
82 if (hwecc_needed == 0)
83 mx3_nf_info->flags.hw_ecc_enabled = 1;
84 else
85 mx3_nf_info->flags.hw_ecc_enabled = 0;
86 }
87
88 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
89 mx3_nf_info->fin = MX3_NF_FIN_NONE;
90 mx3_nf_info->flags.target_little_endian =
91 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
92
93 return ERROR_OK;
94 }
95
96 static int imx31_init(struct nand_device *nand)
97 {
98 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
99 struct target *target = nand->target;
100
101 {
102 /*
103 * validate target state
104 */
105 int validate_target_result;
106 validate_target_result = validate_target_state(nand);
107 if (validate_target_result != ERROR_OK)
108 return validate_target_result;
109 }
110
111 {
112 uint16_t buffsize_register_content;
113 target_read_u16(target, MX3_NF_BUFSIZ, &buffsize_register_content);
114 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
115 }
116
117 {
118 uint32_t pcsr_register_content;
119 target_read_u32(target, MX3_PCSR, &pcsr_register_content);
120 if (!nand->bus_width) {
121 nand->bus_width = (pcsr_register_content & 0x80000000) ? 16 : 8;
122 } else {
123 pcsr_register_content |= ((nand->bus_width == 16) ? 0x80000000 : 0x00000000);
124 target_write_u32(target, MX3_PCSR, pcsr_register_content);
125 }
126
127 if (!nand->page_size) {
128 nand->page_size = (pcsr_register_content & 0x40000000) ? 2048 : 512;
129 } else {
130 pcsr_register_content |= ((nand->page_size == 2048) ? 0x40000000 : 0x00000000);
131 target_write_u32(target, MX3_PCSR, pcsr_register_content);
132 }
133 if (mx3_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
134 LOG_ERROR("NAND controller have only 1 kb SRAM, "
135 "so pagesize 2048 is incompatible with it");
136 }
137 }
138
139 {
140 uint32_t cgr_register_content;
141 target_read_u32(target, MX3_CCM_CGR2, &cgr_register_content);
142 if (!(cgr_register_content & 0x00000300)) {
143 LOG_ERROR("clock gating to EMI disabled");
144 return ERROR_FAIL;
145 }
146 }
147
148 {
149 uint32_t gpr_register_content;
150 target_read_u32(target, MX3_GPR, &gpr_register_content);
151 if (gpr_register_content & 0x00000060) {
152 LOG_ERROR("pins mode overrided by GPR");
153 return ERROR_FAIL;
154 }
155 }
156
157 {
158 /*
159 * testing IOMUX settings; must be in "functional-mode output and
160 * functional-mode input" mode
161 */
162 int test_iomux;
163 test_iomux = ERROR_OK;
164 test_iomux |= test_iomux_settings(target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
165 test_iomux |= test_iomux_settings(target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
166 test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x0000007f, "d7");
167 if (nand->bus_width == 16) {
168 test_iomux |= test_iomux_settings(target, 0x43fac0c8, 0x7f7f7f00, "d8,d9,d10");
169 test_iomux |= test_iomux_settings(target, 0x43fac0cc, 0x7f7f7f7f, "d11,d12,d13,d14");
170 test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x0000007f, "d15");
171 }
172 test_iomux |= test_iomux_settings(target, 0x43fac0d0, 0x7f7f7f00, "nfwp,nfce,nfrb");
173 test_iomux |= test_iomux_settings(target, 0x43fac0d4, 0x7f7f7f7f,
174 "nfwe,nfre,nfale,nfcle");
175 if (test_iomux != ERROR_OK)
176 return ERROR_FAIL;
177 }
178
179 initialize_nf_controller(nand);
180
181 {
182 int retval;
183 uint16_t nand_status_content;
184 retval = ERROR_OK;
185 retval |= imx31_command(nand, NAND_CMD_STATUS);
186 retval |= imx31_address(nand, 0x00);
187 retval |= do_data_output(nand);
188 if (retval != ERROR_OK) {
189 LOG_ERROR(get_status_register_err_msg);
190 return ERROR_FAIL;
191 }
192 target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
193 if (!(nand_status_content & 0x0080)) {
194 /*
195 * is host-big-endian correctly ??
196 */
197 LOG_INFO("NAND read-only");
198 mx3_nf_info->flags.nand_readonly = 1;
199 } else
200 mx3_nf_info->flags.nand_readonly = 0;
201 }
202 return ERROR_OK;
203 }
204
205 static int imx31_read_data(struct nand_device *nand, void *data)
206 {
207 struct target *target = nand->target;
208 {
209 /*
210 * validate target state
211 */
212 int validate_target_result;
213 validate_target_result = validate_target_state(nand);
214 if (validate_target_result != ERROR_OK)
215 return validate_target_result;
216 }
217
218 {
219 /*
220 * get data from nand chip
221 */
222 int try_data_output_from_nand_chip;
223 try_data_output_from_nand_chip = do_data_output(nand);
224 if (try_data_output_from_nand_chip != ERROR_OK)
225 return try_data_output_from_nand_chip;
226 }
227
228 if (nand->bus_width == 16)
229 get_next_halfword_from_sram_buffer(target, data);
230 else
231 get_next_byte_from_sram_buffer(target, data);
232
233 return ERROR_OK;
234 }
235
236 static int imx31_write_data(struct nand_device *nand, uint16_t data)
237 {
238 LOG_ERROR("write_data() not implemented");
239 return ERROR_NAND_OPERATION_FAILED;
240 }
241
242 static int imx31_reset(struct nand_device *nand)
243 {
244 /*
245 * validate target state
246 */
247 int validate_target_result;
248 validate_target_result = validate_target_state(nand);
249 if (validate_target_result != ERROR_OK)
250 return validate_target_result;
251 initialize_nf_controller(nand);
252 return ERROR_OK;
253 }
254
255 static int imx31_command(struct nand_device *nand, uint8_t command)
256 {
257 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
258 struct target *target = nand->target;
259 {
260 /*
261 * validate target state
262 */
263 int validate_target_result;
264 validate_target_result = validate_target_state(nand);
265 if (validate_target_result != ERROR_OK)
266 return validate_target_result;
267 }
268
269 switch (command) {
270 case NAND_CMD_READOOB:
271 command = NAND_CMD_READ0;
272 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
273 * data_read() and
274 * read_block_data() to
275 * spare area in SRAM
276 * buffer */
277 break;
278 case NAND_CMD_READ1:
279 command = NAND_CMD_READ0;
280 /*
281 * offset == one half of page size
282 */
283 in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
284 default:
285 in_sram_address = MX3_NF_MAIN_BUFFER0;
286 }
287
288 target_write_u16(target, MX3_NF_FCMD, command);
289 /*
290 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
291 */
292 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
293 {
294 int poll_result;
295 poll_result = poll_for_complete_op(target, "command");
296 if (poll_result != ERROR_OK)
297 return poll_result;
298 }
299 /*
300 * reset cursor to begin of the buffer
301 */
302 sign_of_sequental_byte_read = 0;
303 switch (command) {
304 case NAND_CMD_READID:
305 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
306 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
307 break;
308 case NAND_CMD_STATUS:
309 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
310 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
311 break;
312 case NAND_CMD_READ0:
313 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
314 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
315 break;
316 default:
317 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
318 }
319 return ERROR_OK;
320 }
321
322 static int imx31_address(struct nand_device *nand, uint8_t address)
323 {
324 struct target *target = nand->target;
325 {
326 /*
327 * validate target state
328 */
329 int validate_target_result;
330 validate_target_result = validate_target_state(nand);
331 if (validate_target_result != ERROR_OK)
332 return validate_target_result;
333 }
334
335 target_write_u16(target, MX3_NF_FADDR, address);
336 /*
337 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
338 */
339 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
340 {
341 int poll_result;
342 poll_result = poll_for_complete_op(target, "address");
343 if (poll_result != ERROR_OK)
344 return poll_result;
345 }
346 return ERROR_OK;
347 }
348
349 static int imx31_nand_ready(struct nand_device *nand, int tout)
350 {
351 uint16_t poll_complete_status;
352 struct target *target = nand->target;
353
354 {
355 /*
356 * validate target state
357 */
358 int validate_target_result;
359 validate_target_result = validate_target_state(nand);
360 if (validate_target_result != ERROR_OK)
361 return validate_target_result;
362 }
363
364 do {
365 target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
366 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
367 return tout;
368 alive_sleep(1);
369 } while (tout-- > 0);
370 return tout;
371 }
372
373 static int imx31_write_page(struct nand_device *nand, uint32_t page,
374 uint8_t *data, uint32_t data_size, uint8_t *oob,
375 uint32_t oob_size)
376 {
377 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
378 struct target *target = nand->target;
379
380 if (data_size % 2) {
381 LOG_ERROR(data_block_size_err_msg, data_size);
382 return ERROR_NAND_OPERATION_FAILED;
383 }
384 if (oob_size % 2) {
385 LOG_ERROR(data_block_size_err_msg, oob_size);
386 return ERROR_NAND_OPERATION_FAILED;
387 }
388 if (!data) {
389 LOG_ERROR("nothing to program");
390 return ERROR_NAND_OPERATION_FAILED;
391 }
392 {
393 /*
394 * validate target state
395 */
396 int retval;
397 retval = validate_target_state(nand);
398 if (retval != ERROR_OK)
399 return retval;
400 }
401 {
402 int retval = ERROR_OK;
403 retval |= imx31_command(nand, NAND_CMD_SEQIN);
404 retval |= imx31_address(nand, 0x00);
405 retval |= imx31_address(nand, page & 0xff);
406 retval |= imx31_address(nand, (page >> 8) & 0xff);
407 if (nand->address_cycles >= 4) {
408 retval |= imx31_address(nand, (page >> 16) & 0xff);
409 if (nand->address_cycles >= 5)
410 retval |= imx31_address(nand, (page >> 24) & 0xff);
411 }
412 target_write_buffer(target, MX3_NF_MAIN_BUFFER0, data_size, data);
413 if (oob) {
414 if (mx3_nf_info->flags.hw_ecc_enabled) {
415 /*
416 * part of spare block will be overrided by hardware
417 * ECC generator
418 */
419 LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
420 }
421 target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
422 }
423 /*
424 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
425 */
426 target_write_u16(target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
427 {
428 int poll_result;
429 poll_result = poll_for_complete_op(target, "data input");
430 if (poll_result != ERROR_OK)
431 return poll_result;
432 }
433 retval |= imx31_command(nand, NAND_CMD_PAGEPROG);
434 if (retval != ERROR_OK)
435 return retval;
436
437 /*
438 * check status register
439 */
440 {
441 uint16_t nand_status_content;
442 retval = ERROR_OK;
443 retval |= imx31_command(nand, NAND_CMD_STATUS);
444 retval |= imx31_address(nand, 0x00);
445 retval |= do_data_output(nand);
446 if (retval != ERROR_OK) {
447 LOG_ERROR(get_status_register_err_msg);
448 return retval;
449 }
450 target_read_u16(target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
451 if (nand_status_content & 0x0001) {
452 /*
453 * is host-big-endian correctly ??
454 */
455 return ERROR_NAND_OPERATION_FAILED;
456 }
457 }
458 }
459 return ERROR_OK;
460 }
461
462 static int imx31_read_page(struct nand_device *nand, uint32_t page,
463 uint8_t *data, uint32_t data_size, uint8_t *oob,
464 uint32_t oob_size)
465 {
466 struct target *target = nand->target;
467
468 if (data_size % 2) {
469 LOG_ERROR(data_block_size_err_msg, data_size);
470 return ERROR_NAND_OPERATION_FAILED;
471 }
472 if (oob_size % 2) {
473 LOG_ERROR(data_block_size_err_msg, oob_size);
474 return ERROR_NAND_OPERATION_FAILED;
475 }
476
477 {
478 /*
479 * validate target state
480 */
481 int retval;
482 retval = validate_target_state(nand);
483 if (retval != ERROR_OK)
484 return retval;
485 }
486 {
487 int retval = ERROR_OK;
488 retval |= imx31_command(nand, NAND_CMD_READ0);
489 retval |= imx31_address(nand, 0x00);
490 retval |= imx31_address(nand, page & 0xff);
491 retval |= imx31_address(nand, (page >> 8) & 0xff);
492 if (nand->address_cycles >= 4) {
493 retval |= imx31_address(nand, (page >> 16) & 0xff);
494 if (nand->address_cycles >= 5) {
495 retval |= imx31_address(nand, (page >> 24) & 0xff);
496 retval |= imx31_command(nand, NAND_CMD_READSTART);
497 }
498 }
499 retval |= do_data_output(nand);
500 if (retval != ERROR_OK)
501 return retval;
502
503 if (data) {
504 target_read_buffer(target, MX3_NF_MAIN_BUFFER0, data_size,
505 data);
506 }
507 if (oob) {
508 target_read_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size,
509 oob);
510 }
511 }
512 return ERROR_OK;
513 }
514
515 static int test_iomux_settings(struct target *target, uint32_t address,
516 uint32_t mask, const char *text)
517 {
518 uint32_t register_content;
519 target_read_u32(target, address, &register_content);
520 if ((register_content & mask) != (0x12121212 & mask)) {
521 LOG_ERROR("IOMUX for {%s} is bad", text);
522 return ERROR_FAIL;
523 }
524 return ERROR_OK;
525 }
526
527 static int initialize_nf_controller(struct nand_device *nand)
528 {
529 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
530 struct target *target = nand->target;
531 /*
532 * resets NAND flash controller in zero time ? I dont know.
533 */
534 target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
535 {
536 uint16_t work_mode;
537 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
538 if (target->endianness == TARGET_BIG_ENDIAN)
539 work_mode |= MX3_NF_BIT_BE_EN;
540 if (mx3_nf_info->flags.hw_ecc_enabled)
541 work_mode |= MX3_NF_BIT_ECC_EN;
542 target_write_u16(target, MX3_NF_CFG1, work_mode);
543 }
544 /*
545 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
546 */
547 target_write_u16(target, MX3_NF_BUFCFG, 2);
548 {
549 uint16_t temp;
550 target_read_u16(target, MX3_NF_FWP, &temp);
551 if ((temp & 0x0007) == 1) {
552 LOG_ERROR("NAND flash is tight-locked, reset needed");
553 return ERROR_FAIL;
554 }
555
556 }
557 /*
558 * unlock NAND flash for write
559 */
560 target_write_u16(target, MX3_NF_FWP, 4);
561 target_write_u16(target, MX3_NF_LOCKSTART, 0x0000);
562 target_write_u16(target, MX3_NF_LOCKEND, 0xFFFF);
563 /*
564 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
565 */
566 target_write_u16(target, MX3_NF_BUFADDR, 0x0000);
567 /*
568 * address of SRAM buffer
569 */
570 in_sram_address = MX3_NF_MAIN_BUFFER0;
571 sign_of_sequental_byte_read = 0;
572 return ERROR_OK;
573 }
574
575 static int get_next_byte_from_sram_buffer(struct target *target, uint8_t *value)
576 {
577 static uint8_t even_byte;
578 /*
579 * host-big_endian ??
580 */
581 if (sign_of_sequental_byte_read == 0)
582 even_byte = 0;
583 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
584 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
585 *value = 0;
586 sign_of_sequental_byte_read = 0;
587 even_byte = 0;
588 return ERROR_NAND_OPERATION_FAILED;
589 } else {
590 uint16_t temp;
591 target_read_u16(target, in_sram_address, &temp);
592 if (even_byte) {
593 *value = temp >> 8;
594 even_byte = 0;
595 in_sram_address += 2;
596 } else {
597 *value = temp & 0xff;
598 even_byte = 1;
599 }
600 }
601 sign_of_sequental_byte_read = 1;
602 return ERROR_OK;
603 }
604
605 static int get_next_halfword_from_sram_buffer(struct target *target,
606 uint16_t *value)
607 {
608 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR) {
609 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
610 *value = 0;
611 return ERROR_NAND_OPERATION_FAILED;
612 } else {
613 target_read_u16(target, in_sram_address, value);
614 in_sram_address += 2;
615 }
616 return ERROR_OK;
617 }
618
619 static int poll_for_complete_op(struct target *target, const char *text)
620 {
621 uint16_t poll_complete_status;
622 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
623 usleep(25);
624 target_read_u16(target, MX3_NF_CFG2, &poll_complete_status);
625 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
626 break;
627 }
628 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE)) {
629 LOG_ERROR("%s sending timeout", text);
630 return ERROR_NAND_OPERATION_FAILED;
631 }
632 return ERROR_OK;
633 }
634
635 static int validate_target_state(struct nand_device *nand)
636 {
637 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
638 struct target *target = nand->target;
639
640 if (target->state != TARGET_HALTED) {
641 LOG_ERROR(target_not_halted_err_msg);
642 return ERROR_NAND_OPERATION_FAILED;
643 }
644
645 if (mx3_nf_info->flags.target_little_endian !=
646 (target->endianness == TARGET_LITTLE_ENDIAN)) {
647 /*
648 * endianness changed after NAND controller probed
649 */
650 return ERROR_NAND_OPERATION_FAILED;
651 }
652 return ERROR_OK;
653 }
654
655 static int do_data_output(struct nand_device *nand)
656 {
657 struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
658 struct target *target = nand->target;
659 switch (mx3_nf_info->fin) {
660 case MX3_NF_FIN_DATAOUT:
661 /*
662 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
663 */
664 target_write_u16 (target, MX3_NF_CFG2,
665 MX3_NF_BIT_DATAOUT_TYPE(mx3_nf_info->optype));
666 {
667 int poll_result;
668 poll_result = poll_for_complete_op(target, "data output");
669 if (poll_result != ERROR_OK)
670 return poll_result;
671 }
672 mx3_nf_info->fin = MX3_NF_FIN_NONE;
673 /*
674 * ECC stuff
675 */
676 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
677 && mx3_nf_info->flags.hw_ecc_enabled) {
678 uint16_t ecc_status;
679 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
680 switch (ecc_status & 0x000c) {
681 case 1 << 2:
682 LOG_DEBUG("main area readed with 1 (correctable) error");
683 break;
684 case 2 << 2:
685 LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
686 return ERROR_NAND_OPERATION_FAILED;
687 break;
688 }
689 switch (ecc_status & 0x0003) {
690 case 1:
691 LOG_DEBUG("spare area readed with 1 (correctable) error");
692 break;
693 case 2:
694 LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
695 return ERROR_NAND_OPERATION_FAILED;
696 break;
697 }
698 }
699 break;
700 case MX3_NF_FIN_NONE:
701 break;
702 }
703 return ERROR_OK;
704 }
705
706 struct nand_flash_controller imx31_nand_flash_controller = {
707 .name = "imx31",
708 .usage = "nand device imx31 target noecc|hwecc",
709 .nand_device_command = &imx31_nand_device_command,
710 .init = &imx31_init,
711 .reset = &imx31_reset,
712 .command = &imx31_command,
713 .address = &imx31_address,
714 .write_data = &imx31_write_data,
715 .read_data = &imx31_read_data,
716 .write_page = &imx31_write_page,
717 .read_page = &imx31_read_page,
718 .nand_ready = &imx31_nand_ready,
719 };
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