2 # FreeScale Cortex-M0plus with 128kB Flash and 16kB Local On-Chip SRAM
4 if { [info exists CHIPNAME] == 0 } {
8 if { [info exists CPUTAPID] == 0 } {
9 set _CPUTAPID 0x0BC11477
12 if { [info exists WORKAREASIZE] == 0 } {
13 set _WORKAREASIZE 0x3000
16 if { [info exists TRANSPORT] == 0 } {
17 set _TRANSPORT hla_swd
20 transport select $_TRANSPORT
22 hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
24 set _TARGETNAME $_CHIPNAME.cpu
25 target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
27 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
29 flash bank pflash kinetis 0x00000000 0x20000 0 4 $_TARGETNAME
31 proc kl25z_enable_pll {} {
32 echo "KL25Z: Enabling PLL"
33 # SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
34 mww 0x40048044 0x00020000
35 # /* Switch to FEI Mode */
36 # MCG->C1 = (uint8_t)0x06U;
38 # MCG->C2 = (uint8_t)0x00U;
40 # /* MCG->C4: DMX32=0,DRST_DRS=1 */
41 # MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
43 #OSC0->CR = (uint8_t)0x80U;
45 # MCG->C5 = (uint8_t)0x00U;
47 # MCG->C6 = (uint8_t)0x00U;
52 $_TARGETNAME configure -event reset-init {